Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 946
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T764 /workspace/coverage/cover_reg_top/3.gpio_intr_test.1152644755 Jun 10 04:42:15 PM PDT 24 Jun 10 04:42:16 PM PDT 24 42023522 ps
T765 /workspace/coverage/cover_reg_top/23.gpio_intr_test.4028338809 Jun 10 04:45:07 PM PDT 24 Jun 10 04:45:08 PM PDT 24 47279970 ps
T39 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2566298179 Jun 10 04:44:56 PM PDT 24 Jun 10 04:44:58 PM PDT 24 115034375 ps
T766 /workspace/coverage/cover_reg_top/12.gpio_intr_test.3485252738 Jun 10 04:44:57 PM PDT 24 Jun 10 04:44:58 PM PDT 24 12555662 ps
T38 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1737060681 Jun 10 04:45:07 PM PDT 24 Jun 10 04:45:09 PM PDT 24 81744046 ps
T40 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.17159065 Jun 10 04:44:53 PM PDT 24 Jun 10 04:44:55 PM PDT 24 255627232 ps
T767 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1560561429 Jun 10 04:45:02 PM PDT 24 Jun 10 04:45:05 PM PDT 24 445210262 ps
T768 /workspace/coverage/cover_reg_top/8.gpio_intr_test.4260355525 Jun 10 04:44:55 PM PDT 24 Jun 10 04:44:56 PM PDT 24 14633586 ps
T769 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2251028592 Jun 10 04:45:06 PM PDT 24 Jun 10 04:45:07 PM PDT 24 193058378 ps
T770 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1337337701 Jun 10 04:42:20 PM PDT 24 Jun 10 04:42:22 PM PDT 24 16605239 ps
T771 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.2161268684 Jun 10 04:44:49 PM PDT 24 Jun 10 04:44:51 PM PDT 24 30427980 ps
T772 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.189520955 Jun 10 04:45:14 PM PDT 24 Jun 10 04:45:20 PM PDT 24 34846963 ps
T41 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1755018555 Jun 10 04:42:34 PM PDT 24 Jun 10 04:42:36 PM PDT 24 156502645 ps
T773 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.320273442 Jun 10 04:44:55 PM PDT 24 Jun 10 04:44:56 PM PDT 24 109944254 ps
T774 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2218340672 Jun 10 04:44:52 PM PDT 24 Jun 10 04:44:53 PM PDT 24 178722879 ps
T775 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.454283572 Jun 10 04:42:16 PM PDT 24 Jun 10 04:42:18 PM PDT 24 236875643 ps
T776 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.509476988 Jun 10 04:44:49 PM PDT 24 Jun 10 04:44:50 PM PDT 24 28237309 ps
T777 /workspace/coverage/cover_reg_top/18.gpio_intr_test.2018791025 Jun 10 04:45:40 PM PDT 24 Jun 10 04:45:41 PM PDT 24 15480875 ps
T778 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3898436061 Jun 10 04:42:32 PM PDT 24 Jun 10 04:42:35 PM PDT 24 149280088 ps
T779 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.488812291 Jun 10 04:42:16 PM PDT 24 Jun 10 04:42:19 PM PDT 24 111311239 ps
T780 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3273935081 Jun 10 04:42:17 PM PDT 24 Jun 10 04:42:19 PM PDT 24 18517631 ps
T781 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1413197469 Jun 10 04:42:35 PM PDT 24 Jun 10 04:42:36 PM PDT 24 24162414 ps
T782 /workspace/coverage/cover_reg_top/37.gpio_intr_test.2708834285 Jun 10 04:45:15 PM PDT 24 Jun 10 04:45:16 PM PDT 24 12851590 ps
T97 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3117474791 Jun 10 04:42:17 PM PDT 24 Jun 10 04:42:20 PM PDT 24 218665609 ps
T783 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.2438592800 Jun 10 04:44:56 PM PDT 24 Jun 10 04:44:57 PM PDT 24 44240877 ps
T784 /workspace/coverage/cover_reg_top/24.gpio_intr_test.4272352548 Jun 10 04:45:09 PM PDT 24 Jun 10 04:45:10 PM PDT 24 67211670 ps
T785 /workspace/coverage/cover_reg_top/36.gpio_intr_test.1317569844 Jun 10 04:44:58 PM PDT 24 Jun 10 04:44:59 PM PDT 24 34996430 ps
T786 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1229334544 Jun 10 04:42:18 PM PDT 24 Jun 10 04:42:21 PM PDT 24 94066229 ps
T787 /workspace/coverage/cover_reg_top/46.gpio_intr_test.2897518980 Jun 10 04:45:01 PM PDT 24 Jun 10 04:45:02 PM PDT 24 46477144 ps
T788 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3373911189 Jun 10 04:45:03 PM PDT 24 Jun 10 04:45:10 PM PDT 24 39689245 ps
T789 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.2960531832 Jun 10 04:45:45 PM PDT 24 Jun 10 04:45:47 PM PDT 24 200736564 ps
T95 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3096014219 Jun 10 04:42:18 PM PDT 24 Jun 10 04:42:21 PM PDT 24 25845703 ps
T790 /workspace/coverage/cover_reg_top/22.gpio_intr_test.2874685862 Jun 10 04:45:07 PM PDT 24 Jun 10 04:45:08 PM PDT 24 58253501 ps
T791 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.2914953311 Jun 10 04:44:59 PM PDT 24 Jun 10 04:45:00 PM PDT 24 147156225 ps
T792 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3705102305 Jun 10 04:45:45 PM PDT 24 Jun 10 04:45:46 PM PDT 24 201193058 ps
T793 /workspace/coverage/cover_reg_top/40.gpio_intr_test.1927671882 Jun 10 04:44:58 PM PDT 24 Jun 10 04:44:59 PM PDT 24 21050830 ps
T794 /workspace/coverage/cover_reg_top/29.gpio_intr_test.1520513786 Jun 10 04:45:00 PM PDT 24 Jun 10 04:45:01 PM PDT 24 59522822 ps
T795 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.3436454790 Jun 10 04:44:58 PM PDT 24 Jun 10 04:45:00 PM PDT 24 51418684 ps
T796 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.750513002 Jun 10 04:44:53 PM PDT 24 Jun 10 04:44:54 PM PDT 24 36995653 ps
T797 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.2658781896 Jun 10 04:44:57 PM PDT 24 Jun 10 04:45:00 PM PDT 24 42980148 ps
T798 /workspace/coverage/cover_reg_top/21.gpio_intr_test.1487600330 Jun 10 04:45:24 PM PDT 24 Jun 10 04:45:25 PM PDT 24 45523126 ps
T799 /workspace/coverage/cover_reg_top/44.gpio_intr_test.4136147594 Jun 10 04:45:01 PM PDT 24 Jun 10 04:45:01 PM PDT 24 33811649 ps
T800 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.208039746 Jun 10 04:44:57 PM PDT 24 Jun 10 04:44:59 PM PDT 24 78846172 ps
T801 /workspace/coverage/cover_reg_top/6.gpio_intr_test.2224761618 Jun 10 04:44:53 PM PDT 24 Jun 10 04:44:53 PM PDT 24 22481060 ps
T802 /workspace/coverage/cover_reg_top/2.gpio_intr_test.4240989229 Jun 10 04:42:26 PM PDT 24 Jun 10 04:42:27 PM PDT 24 271586824 ps
T803 /workspace/coverage/cover_reg_top/31.gpio_intr_test.1724387726 Jun 10 04:45:07 PM PDT 24 Jun 10 04:45:09 PM PDT 24 45235914 ps
T98 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.3608420287 Jun 10 04:42:22 PM PDT 24 Jun 10 04:42:23 PM PDT 24 117549120 ps
T804 /workspace/coverage/cover_reg_top/28.gpio_intr_test.3320356188 Jun 10 04:45:00 PM PDT 24 Jun 10 04:45:01 PM PDT 24 18144895 ps
T805 /workspace/coverage/cover_reg_top/1.gpio_intr_test.1250949536 Jun 10 04:42:39 PM PDT 24 Jun 10 04:42:40 PM PDT 24 17068192 ps
T806 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1116295094 Jun 10 04:44:58 PM PDT 24 Jun 10 04:45:00 PM PDT 24 78585011 ps
T807 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.474759527 Jun 10 04:42:16 PM PDT 24 Jun 10 04:42:19 PM PDT 24 14281290 ps
T808 /workspace/coverage/cover_reg_top/42.gpio_intr_test.475678492 Jun 10 04:45:02 PM PDT 24 Jun 10 04:45:03 PM PDT 24 49481826 ps
T33 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.825537264 Jun 10 04:42:17 PM PDT 24 Jun 10 04:42:21 PM PDT 24 393084146 ps
T91 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.394596906 Jun 10 04:45:02 PM PDT 24 Jun 10 04:45:03 PM PDT 24 37890911 ps
T809 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3634884414 Jun 10 04:44:47 PM PDT 24 Jun 10 04:44:48 PM PDT 24 27535278 ps
T810 /workspace/coverage/cover_reg_top/9.gpio_intr_test.120032280 Jun 10 04:44:59 PM PDT 24 Jun 10 04:45:00 PM PDT 24 14130559 ps
T100 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.3951769525 Jun 10 04:42:25 PM PDT 24 Jun 10 04:42:26 PM PDT 24 21509714 ps
T811 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3457049144 Jun 10 04:44:41 PM PDT 24 Jun 10 04:44:42 PM PDT 24 36065286 ps
T99 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.1621617520 Jun 10 04:44:54 PM PDT 24 Jun 10 04:44:55 PM PDT 24 23849761 ps
T812 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.561288431 Jun 10 04:42:23 PM PDT 24 Jun 10 04:42:24 PM PDT 24 32814142 ps
T813 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.1142545157 Jun 10 04:45:40 PM PDT 24 Jun 10 04:45:42 PM PDT 24 142320585 ps
T814 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2855608663 Jun 10 04:44:58 PM PDT 24 Jun 10 04:44:59 PM PDT 24 133838222 ps
T815 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1483549546 Jun 10 04:44:51 PM PDT 24 Jun 10 04:44:54 PM PDT 24 103466976 ps
T816 /workspace/coverage/cover_reg_top/25.gpio_intr_test.2484950446 Jun 10 04:44:56 PM PDT 24 Jun 10 04:44:57 PM PDT 24 44963464 ps
T817 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3495742529 Jun 10 04:42:18 PM PDT 24 Jun 10 04:42:22 PM PDT 24 78801090 ps
T818 /workspace/coverage/cover_reg_top/5.gpio_intr_test.3537290552 Jun 10 04:44:53 PM PDT 24 Jun 10 04:44:55 PM PDT 24 14819791 ps
T819 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2918882565 Jun 10 04:42:25 PM PDT 24 Jun 10 04:42:26 PM PDT 24 17582504 ps
T820 /workspace/coverage/cover_reg_top/7.gpio_intr_test.3460051703 Jun 10 04:44:49 PM PDT 24 Jun 10 04:44:50 PM PDT 24 29131523 ps
T821 /workspace/coverage/cover_reg_top/47.gpio_intr_test.1713380805 Jun 10 04:45:04 PM PDT 24 Jun 10 04:45:05 PM PDT 24 46292463 ps
T822 /workspace/coverage/cover_reg_top/27.gpio_intr_test.1748197539 Jun 10 04:44:58 PM PDT 24 Jun 10 04:44:59 PM PDT 24 12783712 ps
T823 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.4089611680 Jun 10 04:42:35 PM PDT 24 Jun 10 04:42:38 PM PDT 24 96960256 ps
T824 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3877626960 Jun 10 04:44:59 PM PDT 24 Jun 10 04:45:00 PM PDT 24 12801416 ps
T825 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.530865203 Jun 10 04:42:18 PM PDT 24 Jun 10 04:42:23 PM PDT 24 132522717 ps
T826 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.3672785242 Jun 10 04:42:25 PM PDT 24 Jun 10 04:42:29 PM PDT 24 350602359 ps
T827 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.4216146381 Jun 10 04:45:30 PM PDT 24 Jun 10 04:45:31 PM PDT 24 23746169 ps
T828 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2372666867 Jun 10 04:45:39 PM PDT 24 Jun 10 04:45:41 PM PDT 24 70647688 ps
T829 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3940525161 Jun 10 04:42:32 PM PDT 24 Jun 10 04:42:45 PM PDT 24 587061051 ps
T830 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3247058606 Jun 10 04:44:52 PM PDT 24 Jun 10 04:44:54 PM PDT 24 92139205 ps
T831 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3279194634 Jun 10 04:44:57 PM PDT 24 Jun 10 04:44:58 PM PDT 24 22443673 ps
T832 /workspace/coverage/cover_reg_top/48.gpio_intr_test.2173786776 Jun 10 04:45:27 PM PDT 24 Jun 10 04:45:28 PM PDT 24 43499938 ps
T833 /workspace/coverage/cover_reg_top/19.gpio_intr_test.729776965 Jun 10 04:45:04 PM PDT 24 Jun 10 04:45:05 PM PDT 24 20313212 ps
T834 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2285639353 Jun 10 04:44:44 PM PDT 24 Jun 10 04:44:47 PM PDT 24 176898555 ps
T835 /workspace/coverage/cover_reg_top/49.gpio_intr_test.3021744587 Jun 10 04:45:11 PM PDT 24 Jun 10 04:45:12 PM PDT 24 14762652 ps
T836 /workspace/coverage/cover_reg_top/35.gpio_intr_test.3190175183 Jun 10 04:44:57 PM PDT 24 Jun 10 04:44:58 PM PDT 24 16128132 ps
T837 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.147971254 Jun 10 04:44:57 PM PDT 24 Jun 10 04:45:04 PM PDT 24 42245407 ps
T96 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.2581132796 Jun 10 04:42:17 PM PDT 24 Jun 10 04:42:20 PM PDT 24 38325740 ps
T838 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2320796194 Jun 10 04:44:56 PM PDT 24 Jun 10 04:44:57 PM PDT 24 18914198 ps
T839 /workspace/coverage/cover_reg_top/26.gpio_intr_test.3357294298 Jun 10 04:45:01 PM PDT 24 Jun 10 04:45:02 PM PDT 24 17033545 ps
T840 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.1165592330 Jun 10 04:45:00 PM PDT 24 Jun 10 04:45:03 PM PDT 24 525709976 ps
T841 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2416192022 Jun 10 04:42:28 PM PDT 24 Jun 10 04:42:30 PM PDT 24 34133058 ps
T92 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2300045330 Jun 10 04:42:21 PM PDT 24 Jun 10 04:42:22 PM PDT 24 34244845 ps
T842 /workspace/coverage/cover_reg_top/20.gpio_intr_test.1417325863 Jun 10 04:45:02 PM PDT 24 Jun 10 04:45:03 PM PDT 24 124615030 ps
T843 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.851670923 Jun 10 04:44:44 PM PDT 24 Jun 10 04:44:46 PM PDT 24 48624925 ps
T844 /workspace/coverage/cover_reg_top/16.gpio_intr_test.346191754 Jun 10 04:45:35 PM PDT 24 Jun 10 04:45:36 PM PDT 24 15612750 ps
T845 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.285259415 Jun 10 04:42:17 PM PDT 24 Jun 10 04:42:21 PM PDT 24 63902350 ps
T846 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3086791813 Jun 10 04:44:58 PM PDT 24 Jun 10 04:44:59 PM PDT 24 39048517 ps
T847 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1281895588 Jun 10 05:50:00 PM PDT 24 Jun 10 05:50:01 PM PDT 24 39188957 ps
T848 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.728455258 Jun 10 05:50:09 PM PDT 24 Jun 10 05:50:10 PM PDT 24 45685251 ps
T849 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4154462251 Jun 10 05:49:57 PM PDT 24 Jun 10 05:49:58 PM PDT 24 43363119 ps
T850 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2934798367 Jun 10 05:49:58 PM PDT 24 Jun 10 05:50:00 PM PDT 24 131692122 ps
T851 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2768830654 Jun 10 05:50:11 PM PDT 24 Jun 10 05:50:12 PM PDT 24 652273266 ps
T852 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.289052555 Jun 10 05:50:08 PM PDT 24 Jun 10 05:50:10 PM PDT 24 123600150 ps
T853 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1511255725 Jun 10 05:50:19 PM PDT 24 Jun 10 05:50:20 PM PDT 24 69782443 ps
T854 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.532595733 Jun 10 05:49:56 PM PDT 24 Jun 10 05:49:58 PM PDT 24 63077151 ps
T855 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2695919250 Jun 10 05:50:15 PM PDT 24 Jun 10 05:50:17 PM PDT 24 420029631 ps
T856 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1052948803 Jun 10 05:50:02 PM PDT 24 Jun 10 05:50:04 PM PDT 24 158557199 ps
T857 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4214115297 Jun 10 05:50:16 PM PDT 24 Jun 10 05:50:17 PM PDT 24 34542247 ps
T858 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1878470704 Jun 10 05:50:11 PM PDT 24 Jun 10 05:50:12 PM PDT 24 40707679 ps
T859 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1674780480 Jun 10 05:50:13 PM PDT 24 Jun 10 05:50:14 PM PDT 24 922550135 ps
T860 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1458726305 Jun 10 05:50:12 PM PDT 24 Jun 10 05:50:13 PM PDT 24 58967724 ps
T861 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1000625006 Jun 10 05:50:14 PM PDT 24 Jun 10 05:50:16 PM PDT 24 123397798 ps
T862 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3062056934 Jun 10 05:50:18 PM PDT 24 Jun 10 05:50:20 PM PDT 24 138004944 ps
T863 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2824475820 Jun 10 05:50:11 PM PDT 24 Jun 10 05:50:12 PM PDT 24 537275332 ps
T864 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2181860544 Jun 10 05:50:12 PM PDT 24 Jun 10 05:50:14 PM PDT 24 60405144 ps
T865 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.555277938 Jun 10 05:50:14 PM PDT 24 Jun 10 05:50:15 PM PDT 24 36666420 ps
T866 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3863863755 Jun 10 05:50:09 PM PDT 24 Jun 10 05:50:10 PM PDT 24 465906439 ps
T867 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2120250949 Jun 10 05:50:03 PM PDT 24 Jun 10 05:50:05 PM PDT 24 66419393 ps
T868 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2587523609 Jun 10 05:50:19 PM PDT 24 Jun 10 05:50:20 PM PDT 24 114227728 ps
T869 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2912583714 Jun 10 05:50:15 PM PDT 24 Jun 10 05:50:17 PM PDT 24 46344522 ps
T870 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3397461484 Jun 10 05:50:19 PM PDT 24 Jun 10 05:50:21 PM PDT 24 126877446 ps
T871 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.692511424 Jun 10 05:50:20 PM PDT 24 Jun 10 05:50:22 PM PDT 24 64060985 ps
T872 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4223056719 Jun 10 05:50:14 PM PDT 24 Jun 10 05:50:16 PM PDT 24 173144549 ps
T873 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.664508719 Jun 10 05:50:18 PM PDT 24 Jun 10 05:50:20 PM PDT 24 46847688 ps
T874 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.938799942 Jun 10 05:50:13 PM PDT 24 Jun 10 05:50:14 PM PDT 24 224022238 ps
T875 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1046712120 Jun 10 05:50:15 PM PDT 24 Jun 10 05:50:16 PM PDT 24 31457471 ps
T876 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2130102916 Jun 10 05:50:10 PM PDT 24 Jun 10 05:50:11 PM PDT 24 44041395 ps
T877 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.98237761 Jun 10 05:49:58 PM PDT 24 Jun 10 05:50:00 PM PDT 24 53008008 ps
T878 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1334931893 Jun 10 05:50:18 PM PDT 24 Jun 10 05:50:20 PM PDT 24 276262764 ps
T879 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.628338499 Jun 10 05:50:12 PM PDT 24 Jun 10 05:50:13 PM PDT 24 79959275 ps
T880 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1379878484 Jun 10 05:50:02 PM PDT 24 Jun 10 05:50:03 PM PDT 24 38336264 ps
T881 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3208368375 Jun 10 05:50:20 PM PDT 24 Jun 10 05:50:21 PM PDT 24 84972148 ps
T882 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2059042564 Jun 10 05:50:02 PM PDT 24 Jun 10 05:50:03 PM PDT 24 43746016 ps
T883 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3167007939 Jun 10 05:50:09 PM PDT 24 Jun 10 05:50:11 PM PDT 24 72113889 ps
T884 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.179284130 Jun 10 05:50:18 PM PDT 24 Jun 10 05:50:20 PM PDT 24 102879051 ps
T885 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1258188501 Jun 10 05:50:02 PM PDT 24 Jun 10 05:50:03 PM PDT 24 637702297 ps
T886 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.958701441 Jun 10 05:50:14 PM PDT 24 Jun 10 05:50:15 PM PDT 24 35277320 ps
T887 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2079998109 Jun 10 05:49:56 PM PDT 24 Jun 10 05:49:58 PM PDT 24 268970681 ps
T888 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.157090276 Jun 10 05:50:02 PM PDT 24 Jun 10 05:50:03 PM PDT 24 471693147 ps
T889 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.225052940 Jun 10 05:50:11 PM PDT 24 Jun 10 05:50:13 PM PDT 24 101689064 ps
T890 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.4188278849 Jun 10 05:50:15 PM PDT 24 Jun 10 05:50:16 PM PDT 24 68750547 ps
T891 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.684957582 Jun 10 05:50:11 PM PDT 24 Jun 10 05:50:13 PM PDT 24 40477395 ps
T892 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2404217480 Jun 10 05:50:06 PM PDT 24 Jun 10 05:50:08 PM PDT 24 72667853 ps
T893 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1803150399 Jun 10 05:50:13 PM PDT 24 Jun 10 05:50:15 PM PDT 24 193911627 ps
T894 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.758435700 Jun 10 05:50:13 PM PDT 24 Jun 10 05:50:15 PM PDT 24 47351743 ps
T895 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1216512839 Jun 10 05:50:04 PM PDT 24 Jun 10 05:50:05 PM PDT 24 54847984 ps
T896 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2079576329 Jun 10 05:49:58 PM PDT 24 Jun 10 05:50:00 PM PDT 24 33422327 ps
T897 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3652396011 Jun 10 05:50:18 PM PDT 24 Jun 10 05:50:19 PM PDT 24 137539325 ps
T898 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3236057071 Jun 10 05:50:00 PM PDT 24 Jun 10 05:50:01 PM PDT 24 27275043 ps
T899 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2539435294 Jun 10 05:50:18 PM PDT 24 Jun 10 05:50:20 PM PDT 24 96343194 ps
T900 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3070774728 Jun 10 05:49:59 PM PDT 24 Jun 10 05:50:01 PM PDT 24 698755000 ps
T901 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3676869504 Jun 10 05:50:01 PM PDT 24 Jun 10 05:50:02 PM PDT 24 26893293 ps
T902 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3716444784 Jun 10 05:50:13 PM PDT 24 Jun 10 05:50:14 PM PDT 24 75789634 ps
T903 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3986651476 Jun 10 05:50:11 PM PDT 24 Jun 10 05:50:13 PM PDT 24 264732316 ps
T904 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.568645609 Jun 10 05:50:15 PM PDT 24 Jun 10 05:50:16 PM PDT 24 73918241 ps
T905 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.844149702 Jun 10 05:50:05 PM PDT 24 Jun 10 05:50:07 PM PDT 24 59377862 ps
T906 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.4040599932 Jun 10 05:50:07 PM PDT 24 Jun 10 05:50:09 PM PDT 24 59322039 ps
T907 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3206746636 Jun 10 05:50:00 PM PDT 24 Jun 10 05:50:02 PM PDT 24 172351163 ps
T908 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2168383335 Jun 10 05:50:18 PM PDT 24 Jun 10 05:50:19 PM PDT 24 136514727 ps
T909 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.296342683 Jun 10 05:50:15 PM PDT 24 Jun 10 05:50:17 PM PDT 24 92732161 ps
T910 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4249383708 Jun 10 05:50:16 PM PDT 24 Jun 10 05:50:17 PM PDT 24 103952872 ps
T911 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3915527303 Jun 10 05:50:12 PM PDT 24 Jun 10 05:50:14 PM PDT 24 42779680 ps
T912 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1909056902 Jun 10 05:50:13 PM PDT 24 Jun 10 05:50:15 PM PDT 24 78782919 ps
T913 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2886297431 Jun 10 05:50:11 PM PDT 24 Jun 10 05:50:13 PM PDT 24 38377216 ps
T914 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.2611998550 Jun 10 05:50:16 PM PDT 24 Jun 10 05:50:17 PM PDT 24 64535620 ps
T915 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3080426943 Jun 10 05:50:04 PM PDT 24 Jun 10 05:50:05 PM PDT 24 41864792 ps
T916 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1655706422 Jun 10 05:50:15 PM PDT 24 Jun 10 05:50:16 PM PDT 24 254174950 ps
T917 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3392544706 Jun 10 05:50:01 PM PDT 24 Jun 10 05:50:02 PM PDT 24 78484139 ps
T918 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1763860036 Jun 10 05:49:58 PM PDT 24 Jun 10 05:50:00 PM PDT 24 205254922 ps
T919 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1436546298 Jun 10 05:50:03 PM PDT 24 Jun 10 05:50:05 PM PDT 24 234467244 ps
T920 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2956773733 Jun 10 05:50:06 PM PDT 24 Jun 10 05:50:08 PM PDT 24 47980557 ps
T921 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2861170425 Jun 10 05:50:07 PM PDT 24 Jun 10 05:50:08 PM PDT 24 36357801 ps
T922 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3718201591 Jun 10 05:50:15 PM PDT 24 Jun 10 05:50:17 PM PDT 24 326070093 ps
T923 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3588522175 Jun 10 05:50:13 PM PDT 24 Jun 10 05:50:14 PM PDT 24 1122846933 ps
T924 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4140847647 Jun 10 05:50:02 PM PDT 24 Jun 10 05:50:04 PM PDT 24 55320304 ps
T925 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3906896401 Jun 10 05:50:06 PM PDT 24 Jun 10 05:50:07 PM PDT 24 93437713 ps
T926 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.441331197 Jun 10 05:49:58 PM PDT 24 Jun 10 05:49:59 PM PDT 24 808593383 ps
T927 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.510003171 Jun 10 05:50:03 PM PDT 24 Jun 10 05:50:05 PM PDT 24 44254061 ps
T928 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3449341543 Jun 10 05:50:12 PM PDT 24 Jun 10 05:50:13 PM PDT 24 58145970 ps
T929 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3673491026 Jun 10 05:50:11 PM PDT 24 Jun 10 05:50:12 PM PDT 24 158270051 ps
T930 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2926650178 Jun 10 05:50:12 PM PDT 24 Jun 10 05:50:13 PM PDT 24 102452276 ps
T931 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4091542 Jun 10 05:50:04 PM PDT 24 Jun 10 05:50:05 PM PDT 24 1085313680 ps
T932 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3433413289 Jun 10 05:50:00 PM PDT 24 Jun 10 05:50:01 PM PDT 24 43923172 ps
T933 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1165332087 Jun 10 05:49:59 PM PDT 24 Jun 10 05:50:01 PM PDT 24 257641451 ps
T934 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3175611851 Jun 10 05:50:15 PM PDT 24 Jun 10 05:50:16 PM PDT 24 26712890 ps
T935 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1297096099 Jun 10 05:50:03 PM PDT 24 Jun 10 05:50:05 PM PDT 24 146627347 ps
T936 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2439459015 Jun 10 05:50:02 PM PDT 24 Jun 10 05:50:03 PM PDT 24 113824942 ps
T937 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.4133533913 Jun 10 05:50:15 PM PDT 24 Jun 10 05:50:17 PM PDT 24 272427535 ps
T938 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.2692718142 Jun 10 05:50:17 PM PDT 24 Jun 10 05:50:18 PM PDT 24 78053264 ps
T939 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2958694337 Jun 10 05:50:02 PM PDT 24 Jun 10 05:50:03 PM PDT 24 144604684 ps
T940 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2873981644 Jun 10 05:50:07 PM PDT 24 Jun 10 05:50:09 PM PDT 24 83719984 ps
T941 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1938463006 Jun 10 05:50:07 PM PDT 24 Jun 10 05:50:08 PM PDT 24 54229890 ps
T942 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1126231519 Jun 10 05:50:07 PM PDT 24 Jun 10 05:50:09 PM PDT 24 39209232 ps
T943 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3615611997 Jun 10 05:50:11 PM PDT 24 Jun 10 05:50:13 PM PDT 24 82166111 ps
T944 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.422263592 Jun 10 05:49:56 PM PDT 24 Jun 10 05:49:58 PM PDT 24 551465786 ps
T945 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3346375332 Jun 10 05:50:08 PM PDT 24 Jun 10 05:50:09 PM PDT 24 57935628 ps
T946 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3680598532 Jun 10 05:50:19 PM PDT 24 Jun 10 05:50:20 PM PDT 24 157778235 ps

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.2758523746
Short name T1
Test name
Test status
Simulation time 124636645036 ps
CPU time 546.72 seconds
Started Jun 10 05:54:43 PM PDT 24
Finished Jun 10 06:03:50 PM PDT 24
Peak memory 198256 kb
Host smart-38e3caa7-9694-437c-91c3-f75c79e6cba8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2758523746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.2758523746
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.2101377339
Short name T16
Test name
Test status
Simulation time 255111038 ps
CPU time 1.72 seconds
Started Jun 10 05:55:25 PM PDT 24
Finished Jun 10 05:55:27 PM PDT 24
Peak memory 197964 kb
Host smart-528e8dce-0fe4-444d-b45c-867d647e7026
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101377339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.2101377339
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3829405596
Short name T25
Test name
Test status
Simulation time 101935247 ps
CPU time 1.38 seconds
Started Jun 10 04:42:22 PM PDT 24
Finished Jun 10 04:42:24 PM PDT 24
Peak memory 197844 kb
Host smart-35fcce06-444a-4dc7-b0df-017282bb139d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829405596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.3829405596
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.39321673
Short name T77
Test name
Test status
Simulation time 38655670 ps
CPU time 0.62 seconds
Started Jun 10 04:44:56 PM PDT 24
Finished Jun 10 04:44:58 PM PDT 24
Peak memory 195636 kb
Host smart-ce795228-f5dc-4d9a-be99-b112136b7b32
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39321673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_
csr_rw.39321673
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/default/13.gpio_alert_test.236927321
Short name T141
Test name
Test status
Simulation time 20792296 ps
CPU time 0.59 seconds
Started Jun 10 05:54:09 PM PDT 24
Finished Jun 10 05:54:10 PM PDT 24
Peak memory 194648 kb
Host smart-17ae5510-d548-4f45-bd06-d66c39e97fa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236927321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.236927321
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_full_random.978842171
Short name T3
Test name
Test status
Simulation time 399126497 ps
CPU time 0.99 seconds
Started Jun 10 05:54:34 PM PDT 24
Finished Jun 10 05:54:35 PM PDT 24
Peak memory 197076 kb
Host smart-dc11a544-7759-4cf3-9909-2f3cc91a0361
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978842171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.978842171
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.3622687604
Short name T43
Test name
Test status
Simulation time 38143674 ps
CPU time 0.79 seconds
Started Jun 10 05:53:37 PM PDT 24
Finished Jun 10 05:53:38 PM PDT 24
Peak memory 213780 kb
Host smart-936b500c-bb9a-4639-8150-491f25f3ff7e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622687604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.3622687604
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1073324246
Short name T101
Test name
Test status
Simulation time 75957252 ps
CPU time 0.72 seconds
Started Jun 10 04:42:22 PM PDT 24
Finished Jun 10 04:42:23 PM PDT 24
Peak memory 196168 kb
Host smart-3282f2e2-7e4d-47b0-9f72-21ca42f9ece2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073324246 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.1073324246
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2372666867
Short name T828
Test name
Test status
Simulation time 70647688 ps
CPU time 1.22 seconds
Started Jun 10 04:45:39 PM PDT 24
Finished Jun 10 04:45:41 PM PDT 24
Peak memory 197880 kb
Host smart-cd2d3555-d153-436e-87dc-fe8e113ac384
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372666867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.2372666867
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.825537264
Short name T33
Test name
Test status
Simulation time 393084146 ps
CPU time 1.36 seconds
Started Jun 10 04:42:17 PM PDT 24
Finished Jun 10 04:42:21 PM PDT 24
Peak memory 197896 kb
Host smart-faad7d48-e570-45b3-a86b-3ffa117a97ed
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825537264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.gpio_tl_intg_err.825537264
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3620642603
Short name T93
Test name
Test status
Simulation time 58169911 ps
CPU time 0.85 seconds
Started Jun 10 04:42:22 PM PDT 24
Finished Jun 10 04:42:24 PM PDT 24
Peak memory 195912 kb
Host smart-314220aa-42d0-4f7e-8671-0d00d7db796e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620642603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.3620642603
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1568142655
Short name T751
Test name
Test status
Simulation time 764731007 ps
CPU time 3.4 seconds
Started Jun 10 04:42:21 PM PDT 24
Finished Jun 10 04:42:25 PM PDT 24
Peak memory 196656 kb
Host smart-25c21342-56ba-4363-b037-2186e722f83c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568142655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.1568142655
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1337337701
Short name T770
Test name
Test status
Simulation time 16605239 ps
CPU time 0.61 seconds
Started Jun 10 04:42:20 PM PDT 24
Finished Jun 10 04:42:22 PM PDT 24
Peak memory 194104 kb
Host smart-938fd8aa-c2d7-4c14-b0f7-d0136471e9ad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337337701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.1337337701
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.3595244954
Short name T732
Test name
Test status
Simulation time 54822829 ps
CPU time 0.81 seconds
Started Jun 10 04:42:39 PM PDT 24
Finished Jun 10 04:42:40 PM PDT 24
Peak memory 197796 kb
Host smart-bf7d3261-baf1-45a2-97e6-de3036396c12
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595244954 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.3595244954
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.3553498670
Short name T90
Test name
Test status
Simulation time 31199151 ps
CPU time 0.6 seconds
Started Jun 10 04:42:32 PM PDT 24
Finished Jun 10 04:42:33 PM PDT 24
Peak memory 194772 kb
Host smart-11edfada-acea-4e1c-8ee0-12d6c8520eff
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553498670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.3553498670
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.1142582604
Short name T735
Test name
Test status
Simulation time 46577205 ps
CPU time 0.56 seconds
Started Jun 10 04:42:18 PM PDT 24
Finished Jun 10 04:42:21 PM PDT 24
Peak memory 193684 kb
Host smart-1ac66423-c0b4-4147-9059-374b56071f74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142582604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.1142582604
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2416192022
Short name T841
Test name
Test status
Simulation time 34133058 ps
CPU time 0.71 seconds
Started Jun 10 04:42:28 PM PDT 24
Finished Jun 10 04:42:30 PM PDT 24
Peak memory 195580 kb
Host smart-4b1f4844-08d3-431f-b860-a9aa936a2836
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416192022 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.2416192022
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.530865203
Short name T825
Test name
Test status
Simulation time 132522717 ps
CPU time 2.79 seconds
Started Jun 10 04:42:18 PM PDT 24
Finished Jun 10 04:42:23 PM PDT 24
Peak memory 197460 kb
Host smart-34659325-1cb9-4716-aab9-b7ff77d32df2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530865203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.530865203
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1755018555
Short name T41
Test name
Test status
Simulation time 156502645 ps
CPU time 1.17 seconds
Started Jun 10 04:42:34 PM PDT 24
Finished Jun 10 04:42:36 PM PDT 24
Peak memory 197852 kb
Host smart-941f4dcb-7ce4-4c26-897d-b3c09ba66042
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755018555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.1755018555
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2300045330
Short name T92
Test name
Test status
Simulation time 34244845 ps
CPU time 0.75 seconds
Started Jun 10 04:42:21 PM PDT 24
Finished Jun 10 04:42:22 PM PDT 24
Peak memory 196332 kb
Host smart-280feeb2-8989-4d46-beb4-beb77bc01da6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300045330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.2300045330
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.3672785242
Short name T826
Test name
Test status
Simulation time 350602359 ps
CPU time 3.22 seconds
Started Jun 10 04:42:25 PM PDT 24
Finished Jun 10 04:42:29 PM PDT 24
Peak memory 196604 kb
Host smart-86d970d8-1b6b-4b50-81fc-3f591deb2cfb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672785242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.3672785242
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2918882565
Short name T819
Test name
Test status
Simulation time 17582504 ps
CPU time 0.63 seconds
Started Jun 10 04:42:25 PM PDT 24
Finished Jun 10 04:42:26 PM PDT 24
Peak memory 194564 kb
Host smart-fcd84838-2a0a-4baa-9c34-6f7581af18b8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918882565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.2918882565
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3100617262
Short name T734
Test name
Test status
Simulation time 93550423 ps
CPU time 0.82 seconds
Started Jun 10 04:42:33 PM PDT 24
Finished Jun 10 04:42:34 PM PDT 24
Peak memory 198008 kb
Host smart-2fb5379c-743b-49cb-b2fe-1d4a59a0475a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100617262 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.3100617262
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1413197469
Short name T781
Test name
Test status
Simulation time 24162414 ps
CPU time 0.63 seconds
Started Jun 10 04:42:35 PM PDT 24
Finished Jun 10 04:42:36 PM PDT 24
Peak memory 195216 kb
Host smart-2614a6db-41fc-4c34-bd95-3a90b1655173
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413197469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.1413197469
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.1250949536
Short name T805
Test name
Test status
Simulation time 17068192 ps
CPU time 0.56 seconds
Started Jun 10 04:42:39 PM PDT 24
Finished Jun 10 04:42:40 PM PDT 24
Peak memory 194088 kb
Host smart-02dca0b9-874c-4129-b386-95dc06ba1607
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250949536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.1250949536
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3940525161
Short name T829
Test name
Test status
Simulation time 587061051 ps
CPU time 3.05 seconds
Started Jun 10 04:42:32 PM PDT 24
Finished Jun 10 04:42:45 PM PDT 24
Peak memory 198120 kb
Host smart-fdad557a-51ae-4a0c-9e4f-3021929a921e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940525161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.3940525161
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3476722095
Short name T35
Test name
Test status
Simulation time 74223186 ps
CPU time 1.14 seconds
Started Jun 10 04:42:23 PM PDT 24
Finished Jun 10 04:42:24 PM PDT 24
Peak memory 198112 kb
Host smart-717cd55f-e250-4704-80d0-c692513d5f04
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476722095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.3476722095
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.208039746
Short name T800
Test name
Test status
Simulation time 78846172 ps
CPU time 1 seconds
Started Jun 10 04:44:57 PM PDT 24
Finished Jun 10 04:44:59 PM PDT 24
Peak memory 197800 kb
Host smart-58fca7d5-5d87-4797-9db2-7feaeeb3605a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208039746 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.208039746
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.677251286
Short name T725
Test name
Test status
Simulation time 16082013 ps
CPU time 0.58 seconds
Started Jun 10 04:44:55 PM PDT 24
Finished Jun 10 04:44:56 PM PDT 24
Peak memory 193536 kb
Host smart-f076deca-3cff-4804-975e-5763e1b4e3b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677251286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.677251286
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3365829115
Short name T102
Test name
Test status
Simulation time 115527136 ps
CPU time 0.83 seconds
Started Jun 10 04:45:00 PM PDT 24
Finished Jun 10 04:45:01 PM PDT 24
Peak memory 196008 kb
Host smart-f59c3d9f-cf43-49cf-9acf-f24ab8660173
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365829115 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.3365829115
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.687561190
Short name T728
Test name
Test status
Simulation time 139796118 ps
CPU time 1.86 seconds
Started Jun 10 04:44:54 PM PDT 24
Finished Jun 10 04:44:56 PM PDT 24
Peak memory 197880 kb
Host smart-04a97def-0d40-402a-a4dc-616dcccec3df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687561190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.687561190
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1577315310
Short name T37
Test name
Test status
Simulation time 45211287 ps
CPU time 0.86 seconds
Started Jun 10 04:45:00 PM PDT 24
Finished Jun 10 04:45:01 PM PDT 24
Peak memory 197028 kb
Host smart-f99766f7-153e-459b-b489-bf17dcbaa1e8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577315310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.1577315310
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.509476988
Short name T776
Test name
Test status
Simulation time 28237309 ps
CPU time 0.85 seconds
Started Jun 10 04:44:49 PM PDT 24
Finished Jun 10 04:44:50 PM PDT 24
Peak memory 197820 kb
Host smart-9f85165c-9aeb-4cda-8783-1bfa08844b08
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509476988 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.509476988
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.49994737
Short name T71
Test name
Test status
Simulation time 32995387 ps
CPU time 0.59 seconds
Started Jun 10 04:45:09 PM PDT 24
Finished Jun 10 04:45:09 PM PDT 24
Peak memory 194568 kb
Host smart-65de199e-ee98-404c-919a-5a84bfccb79d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49994737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_
csr_rw.49994737
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.967370309
Short name T746
Test name
Test status
Simulation time 36941340 ps
CPU time 0.56 seconds
Started Jun 10 04:44:53 PM PDT 24
Finished Jun 10 04:44:55 PM PDT 24
Peak memory 193520 kb
Host smart-d2eef29b-3d05-48cc-8864-fb47b39ac8b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967370309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.967370309
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1113533733
Short name T105
Test name
Test status
Simulation time 40968917 ps
CPU time 0.64 seconds
Started Jun 10 04:44:54 PM PDT 24
Finished Jun 10 04:44:55 PM PDT 24
Peak memory 194388 kb
Host smart-94e63e62-6218-421b-b0df-21fbc59d73de
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113533733 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.1113533733
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.3436454790
Short name T795
Test name
Test status
Simulation time 51418684 ps
CPU time 1.33 seconds
Started Jun 10 04:44:58 PM PDT 24
Finished Jun 10 04:45:00 PM PDT 24
Peak memory 197864 kb
Host smart-456de89e-fc34-4f9e-bace-03a7635098a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436454790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.3436454790
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.147971254
Short name T837
Test name
Test status
Simulation time 42245407 ps
CPU time 0.85 seconds
Started Jun 10 04:44:57 PM PDT 24
Finished Jun 10 04:45:04 PM PDT 24
Peak memory 196904 kb
Host smart-f96ff6c7-2a87-4ab0-b08e-b95f0b9448b0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147971254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.gpio_tl_intg_err.147971254
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2251028592
Short name T769
Test name
Test status
Simulation time 193058378 ps
CPU time 0.81 seconds
Started Jun 10 04:45:06 PM PDT 24
Finished Jun 10 04:45:07 PM PDT 24
Peak memory 197908 kb
Host smart-a7eb3e71-1736-468c-9803-3b2187ee0034
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251028592 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.2251028592
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2218340672
Short name T774
Test name
Test status
Simulation time 178722879 ps
CPU time 0.6 seconds
Started Jun 10 04:44:52 PM PDT 24
Finished Jun 10 04:44:53 PM PDT 24
Peak memory 195352 kb
Host smart-8678b137-0a28-4fe5-95cd-0ed51b1abb71
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218340672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.2218340672
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.3485252738
Short name T766
Test name
Test status
Simulation time 12555662 ps
CPU time 0.61 seconds
Started Jun 10 04:44:57 PM PDT 24
Finished Jun 10 04:44:58 PM PDT 24
Peak memory 194224 kb
Host smart-46a62d8d-e8d8-4ee2-ba15-4b82c0c801fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485252738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.3485252738
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2855608663
Short name T814
Test name
Test status
Simulation time 133838222 ps
CPU time 0.74 seconds
Started Jun 10 04:44:58 PM PDT 24
Finished Jun 10 04:44:59 PM PDT 24
Peak memory 195804 kb
Host smart-6efc8c41-93c2-41f7-a531-3114237b6392
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855608663 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2855608663
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3895669174
Short name T738
Test name
Test status
Simulation time 35889612 ps
CPU time 0.98 seconds
Started Jun 10 04:45:00 PM PDT 24
Finished Jun 10 04:45:02 PM PDT 24
Peak memory 197724 kb
Host smart-7eb1c546-d8bb-400a-b428-69c932b717bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895669174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.3895669174
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1116295094
Short name T806
Test name
Test status
Simulation time 78585011 ps
CPU time 0.82 seconds
Started Jun 10 04:44:58 PM PDT 24
Finished Jun 10 04:45:00 PM PDT 24
Peak memory 196856 kb
Host smart-9fcf8dd8-3bc1-4162-a361-40d1218901dd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116295094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.1116295094
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.3577890324
Short name T737
Test name
Test status
Simulation time 19454042 ps
CPU time 1.04 seconds
Started Jun 10 04:44:56 PM PDT 24
Finished Jun 10 04:44:57 PM PDT 24
Peak memory 197812 kb
Host smart-3f8c4cb1-4090-435c-8120-6a14ac0e47a5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577890324 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.3577890324
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.158055465
Short name T89
Test name
Test status
Simulation time 44005090 ps
CPU time 0.58 seconds
Started Jun 10 04:44:57 PM PDT 24
Finished Jun 10 04:44:58 PM PDT 24
Peak memory 194304 kb
Host smart-26547a13-8a3e-4c99-815a-ef997816580d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158055465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio
_csr_rw.158055465
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.734940562
Short name T749
Test name
Test status
Simulation time 12517907 ps
CPU time 0.56 seconds
Started Jun 10 04:44:55 PM PDT 24
Finished Jun 10 04:44:56 PM PDT 24
Peak memory 193484 kb
Host smart-72c6ac58-b233-4864-aaf4-f572ac65b99c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734940562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.734940562
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.2914953311
Short name T791
Test name
Test status
Simulation time 147156225 ps
CPU time 0.78 seconds
Started Jun 10 04:44:59 PM PDT 24
Finished Jun 10 04:45:00 PM PDT 24
Peak memory 196152 kb
Host smart-96676ef6-384e-4347-8b02-3e43e197af8d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914953311 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.2914953311
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.2960531832
Short name T789
Test name
Test status
Simulation time 200736564 ps
CPU time 2.29 seconds
Started Jun 10 04:45:45 PM PDT 24
Finished Jun 10 04:45:47 PM PDT 24
Peak memory 197868 kb
Host smart-72332e02-bdf4-4f14-b6ad-34866d140a63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960531832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.2960531832
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.968546259
Short name T36
Test name
Test status
Simulation time 148488640 ps
CPU time 0.86 seconds
Started Jun 10 04:44:56 PM PDT 24
Finished Jun 10 04:44:57 PM PDT 24
Peak memory 197116 kb
Host smart-a0ddfa44-729f-4a03-8df6-370f0fbc6a0b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968546259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.gpio_tl_intg_err.968546259
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.320273442
Short name T773
Test name
Test status
Simulation time 109944254 ps
CPU time 0.86 seconds
Started Jun 10 04:44:55 PM PDT 24
Finished Jun 10 04:44:56 PM PDT 24
Peak memory 197824 kb
Host smart-60761ed2-188f-4d25-8776-e1f22db9c69f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320273442 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.320273442
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.4252793283
Short name T76
Test name
Test status
Simulation time 15501197 ps
CPU time 0.58 seconds
Started Jun 10 04:45:01 PM PDT 24
Finished Jun 10 04:45:02 PM PDT 24
Peak memory 194608 kb
Host smart-d973c290-7540-46af-b7b0-b18a1c41d44f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252793283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.4252793283
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.3038127201
Short name T757
Test name
Test status
Simulation time 122586923 ps
CPU time 0.64 seconds
Started Jun 10 04:44:59 PM PDT 24
Finished Jun 10 04:45:00 PM PDT 24
Peak memory 193508 kb
Host smart-b44564aa-7ea9-4f5e-a01e-a88e355c291d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038127201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.3038127201
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3086791813
Short name T846
Test name
Test status
Simulation time 39048517 ps
CPU time 0.63 seconds
Started Jun 10 04:44:58 PM PDT 24
Finished Jun 10 04:44:59 PM PDT 24
Peak memory 194488 kb
Host smart-1b158e28-9eef-44ac-96c8-afde42dac5d7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086791813 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.3086791813
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.1142545157
Short name T813
Test name
Test status
Simulation time 142320585 ps
CPU time 1.61 seconds
Started Jun 10 04:45:40 PM PDT 24
Finished Jun 10 04:45:42 PM PDT 24
Peak memory 197840 kb
Host smart-39759c7a-00d5-49f1-991e-f6473f333981
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142545157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.1142545157
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2566298179
Short name T39
Test name
Test status
Simulation time 115034375 ps
CPU time 1.42 seconds
Started Jun 10 04:44:56 PM PDT 24
Finished Jun 10 04:44:58 PM PDT 24
Peak memory 197820 kb
Host smart-06692c06-d37b-4513-bdb2-4de4b238711b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566298179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.2566298179
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1487948581
Short name T740
Test name
Test status
Simulation time 17627062 ps
CPU time 0.71 seconds
Started Jun 10 04:45:05 PM PDT 24
Finished Jun 10 04:45:06 PM PDT 24
Peak memory 197880 kb
Host smart-6c07c388-4a01-44c9-a203-15e76a8627af
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487948581 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.1487948581
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.3533847553
Short name T70
Test name
Test status
Simulation time 48337116 ps
CPU time 0.71 seconds
Started Jun 10 04:44:53 PM PDT 24
Finished Jun 10 04:44:55 PM PDT 24
Peak memory 194980 kb
Host smart-28bc7550-64d9-41f0-b0f4-5ea2e2b6f90a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533847553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.3533847553
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.2251929449
Short name T750
Test name
Test status
Simulation time 30029355 ps
CPU time 0.56 seconds
Started Jun 10 04:44:57 PM PDT 24
Finished Jun 10 04:44:58 PM PDT 24
Peak memory 193476 kb
Host smart-1c00c44e-afd5-4e71-ad44-2b62b8317b05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251929449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.2251929449
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1488631321
Short name T104
Test name
Test status
Simulation time 15310298 ps
CPU time 0.73 seconds
Started Jun 10 04:44:57 PM PDT 24
Finished Jun 10 04:44:58 PM PDT 24
Peak memory 195944 kb
Host smart-79b845f3-245a-4b82-a775-c4fbe593188a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488631321 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.1488631321
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.1165592330
Short name T840
Test name
Test status
Simulation time 525709976 ps
CPU time 2.54 seconds
Started Jun 10 04:45:00 PM PDT 24
Finished Jun 10 04:45:03 PM PDT 24
Peak memory 197948 kb
Host smart-4f733ba8-b2d7-4863-9581-272d6b802dae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165592330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.1165592330
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2320796194
Short name T838
Test name
Test status
Simulation time 18914198 ps
CPU time 0.96 seconds
Started Jun 10 04:44:56 PM PDT 24
Finished Jun 10 04:44:57 PM PDT 24
Peak memory 197900 kb
Host smart-7e280d4e-4b12-43d6-b932-321075fefe82
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320796194 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.2320796194
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.4216146381
Short name T827
Test name
Test status
Simulation time 23746169 ps
CPU time 0.63 seconds
Started Jun 10 04:45:30 PM PDT 24
Finished Jun 10 04:45:31 PM PDT 24
Peak memory 194600 kb
Host smart-d49bcc2e-94fb-47ca-91d8-212c6f4c9836
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216146381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.4216146381
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.346191754
Short name T844
Test name
Test status
Simulation time 15612750 ps
CPU time 0.58 seconds
Started Jun 10 04:45:35 PM PDT 24
Finished Jun 10 04:45:36 PM PDT 24
Peak memory 193412 kb
Host smart-d458c97f-39bd-45b6-bde6-a624ba955f47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346191754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.346191754
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.189520955
Short name T772
Test name
Test status
Simulation time 34846963 ps
CPU time 0.83 seconds
Started Jun 10 04:45:14 PM PDT 24
Finished Jun 10 04:45:20 PM PDT 24
Peak memory 196788 kb
Host smart-e5b28602-c114-4dd8-a46b-50e2b9a522a2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189520955 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 16.gpio_same_csr_outstanding.189520955
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1281637295
Short name T744
Test name
Test status
Simulation time 331649464 ps
CPU time 1.99 seconds
Started Jun 10 04:45:00 PM PDT 24
Finished Jun 10 04:45:02 PM PDT 24
Peak memory 197944 kb
Host smart-0ac94256-84df-4f88-b4a3-595147900a01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281637295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1281637295
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.1774306683
Short name T110
Test name
Test status
Simulation time 87916422 ps
CPU time 0.88 seconds
Started Jun 10 04:45:12 PM PDT 24
Finished Jun 10 04:45:14 PM PDT 24
Peak memory 197148 kb
Host smart-ede3a4c9-ae83-42ac-8924-9d3670a8f196
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774306683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.1774306683
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3786270264
Short name T758
Test name
Test status
Simulation time 41932827 ps
CPU time 0.9 seconds
Started Jun 10 04:44:58 PM PDT 24
Finished Jun 10 04:44:59 PM PDT 24
Peak memory 197820 kb
Host smart-166b16c1-5c54-4e00-8bda-21156f36b01d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786270264 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.3786270264
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3364786439
Short name T75
Test name
Test status
Simulation time 11378203 ps
CPU time 0.57 seconds
Started Jun 10 04:45:31 PM PDT 24
Finished Jun 10 04:45:32 PM PDT 24
Peak memory 193500 kb
Host smart-04d53b96-5aa3-45b6-83c0-0f257ab43bc8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364786439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.3364786439
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.2406966912
Short name T733
Test name
Test status
Simulation time 14802042 ps
CPU time 0.57 seconds
Started Jun 10 04:44:56 PM PDT 24
Finished Jun 10 04:44:57 PM PDT 24
Peak memory 194184 kb
Host smart-ea734f8e-cd2e-4419-a010-6eb083e74ed8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406966912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.2406966912
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3487833343
Short name T107
Test name
Test status
Simulation time 79869660 ps
CPU time 0.68 seconds
Started Jun 10 04:45:00 PM PDT 24
Finished Jun 10 04:45:01 PM PDT 24
Peak memory 194600 kb
Host smart-31e89851-b3ad-4ec4-9887-11410a6970ac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487833343 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.3487833343
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3373911189
Short name T788
Test name
Test status
Simulation time 39689245 ps
CPU time 1.03 seconds
Started Jun 10 04:45:03 PM PDT 24
Finished Jun 10 04:45:10 PM PDT 24
Peak memory 197792 kb
Host smart-19ca9caf-e97d-4bfb-afcb-d86adf2b65d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373911189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.3373911189
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.2507314785
Short name T26
Test name
Test status
Simulation time 100992131 ps
CPU time 0.99 seconds
Started Jun 10 04:45:37 PM PDT 24
Finished Jun 10 04:45:38 PM PDT 24
Peak memory 197436 kb
Host smart-de810f00-de1c-40e9-8708-630be08e3712
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507314785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.2507314785
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.184876173
Short name T745
Test name
Test status
Simulation time 56292330 ps
CPU time 0.83 seconds
Started Jun 10 04:45:00 PM PDT 24
Finished Jun 10 04:45:01 PM PDT 24
Peak memory 197812 kb
Host smart-ab230f05-3bb4-409c-94c4-167b412f5709
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184876173 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.184876173
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.1645007465
Short name T752
Test name
Test status
Simulation time 50024672 ps
CPU time 0.59 seconds
Started Jun 10 04:44:59 PM PDT 24
Finished Jun 10 04:45:00 PM PDT 24
Peak memory 195064 kb
Host smart-356be5ad-c901-44d8-bdbd-28852fb8b198
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645007465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.1645007465
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.2018791025
Short name T777
Test name
Test status
Simulation time 15480875 ps
CPU time 0.66 seconds
Started Jun 10 04:45:40 PM PDT 24
Finished Jun 10 04:45:41 PM PDT 24
Peak memory 194228 kb
Host smart-2f66557e-90e4-4da8-8ce6-9918383dc5aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018791025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.2018791025
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3877626960
Short name T824
Test name
Test status
Simulation time 12801416 ps
CPU time 0.64 seconds
Started Jun 10 04:44:59 PM PDT 24
Finished Jun 10 04:45:00 PM PDT 24
Peak memory 194532 kb
Host smart-f0ac41c2-118f-42a7-8178-8c7c8e7e4785
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877626960 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.3877626960
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.2658781896
Short name T797
Test name
Test status
Simulation time 42980148 ps
CPU time 2.18 seconds
Started Jun 10 04:44:57 PM PDT 24
Finished Jun 10 04:45:00 PM PDT 24
Peak memory 197872 kb
Host smart-9e25b18e-ca9d-4efb-af74-5f2f040ffcf8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658781896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.2658781896
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1737060681
Short name T38
Test name
Test status
Simulation time 81744046 ps
CPU time 1.12 seconds
Started Jun 10 04:45:07 PM PDT 24
Finished Jun 10 04:45:09 PM PDT 24
Peak memory 197936 kb
Host smart-ed3df2eb-ba6b-4f5a-8b76-4bcf9663db8a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737060681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.1737060681
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3414630414
Short name T743
Test name
Test status
Simulation time 215670134 ps
CPU time 1.17 seconds
Started Jun 10 04:44:58 PM PDT 24
Finished Jun 10 04:45:00 PM PDT 24
Peak memory 197948 kb
Host smart-5ea839d5-ae6a-4f9e-94e8-9f57c94aa289
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414630414 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.3414630414
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.394596906
Short name T91
Test name
Test status
Simulation time 37890911 ps
CPU time 0.59 seconds
Started Jun 10 04:45:02 PM PDT 24
Finished Jun 10 04:45:03 PM PDT 24
Peak memory 194496 kb
Host smart-5b3cbb2d-e0c7-4507-8474-fbb7c46f7493
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394596906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio
_csr_rw.394596906
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.729776965
Short name T833
Test name
Test status
Simulation time 20313212 ps
CPU time 0.56 seconds
Started Jun 10 04:45:04 PM PDT 24
Finished Jun 10 04:45:05 PM PDT 24
Peak memory 194128 kb
Host smart-f8af95a6-b421-4c75-9d87-0c37455960b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729776965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.729776965
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3394144887
Short name T73
Test name
Test status
Simulation time 54263478 ps
CPU time 0.8 seconds
Started Jun 10 04:44:59 PM PDT 24
Finished Jun 10 04:45:00 PM PDT 24
Peak memory 196256 kb
Host smart-49a75be5-b7c7-446c-b5c3-53444834fdd7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394144887 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.3394144887
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1560561429
Short name T767
Test name
Test status
Simulation time 445210262 ps
CPU time 2.65 seconds
Started Jun 10 04:45:02 PM PDT 24
Finished Jun 10 04:45:05 PM PDT 24
Peak memory 197796 kb
Host smart-7cf96818-0177-41b1-a865-a1b0a5e1d01d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560561429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.1560561429
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3705102305
Short name T792
Test name
Test status
Simulation time 201193058 ps
CPU time 1.04 seconds
Started Jun 10 04:45:45 PM PDT 24
Finished Jun 10 04:45:46 PM PDT 24
Peak memory 197496 kb
Host smart-937d387e-48f6-42df-abeb-97e8768334b4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705102305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.3705102305
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.3608420287
Short name T98
Test name
Test status
Simulation time 117549120 ps
CPU time 0.64 seconds
Started Jun 10 04:42:22 PM PDT 24
Finished Jun 10 04:42:23 PM PDT 24
Peak memory 194096 kb
Host smart-d1471172-67a8-4ea8-bf29-b37515dcaccf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608420287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.3608420287
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.285259415
Short name T845
Test name
Test status
Simulation time 63902350 ps
CPU time 2.19 seconds
Started Jun 10 04:42:17 PM PDT 24
Finished Jun 10 04:42:21 PM PDT 24
Peak memory 196788 kb
Host smart-43c4910c-5aa5-4b0d-b3d7-0593fde49b2f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285259415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.285259415
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.2581132796
Short name T96
Test name
Test status
Simulation time 38325740 ps
CPU time 0.65 seconds
Started Jun 10 04:42:17 PM PDT 24
Finished Jun 10 04:42:20 PM PDT 24
Peak memory 194844 kb
Host smart-9194cb34-c467-4dfe-9f0a-1e2e89788d91
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581132796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.2581132796
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.843931846
Short name T747
Test name
Test status
Simulation time 76548435 ps
CPU time 0.73 seconds
Started Jun 10 04:42:35 PM PDT 24
Finished Jun 10 04:42:36 PM PDT 24
Peak memory 197788 kb
Host smart-bd6a4e50-d4c9-4a47-b1e2-a775a140bf98
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843931846 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.843931846
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.3951769525
Short name T100
Test name
Test status
Simulation time 21509714 ps
CPU time 0.58 seconds
Started Jun 10 04:42:25 PM PDT 24
Finished Jun 10 04:42:26 PM PDT 24
Peak memory 194736 kb
Host smart-37693289-6f21-4dd9-ac24-b8ac74a853f2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951769525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.3951769525
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.4240989229
Short name T802
Test name
Test status
Simulation time 271586824 ps
CPU time 0.61 seconds
Started Jun 10 04:42:26 PM PDT 24
Finished Jun 10 04:42:27 PM PDT 24
Peak memory 193544 kb
Host smart-88fb5d9d-a24b-43be-81c7-11b86d0682cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240989229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.4240989229
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.561288431
Short name T812
Test name
Test status
Simulation time 32814142 ps
CPU time 0.83 seconds
Started Jun 10 04:42:23 PM PDT 24
Finished Jun 10 04:42:24 PM PDT 24
Peak memory 196968 kb
Host smart-04e24392-4e8f-46dc-bb50-77a6d152dc5e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561288431 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.gpio_same_csr_outstanding.561288431
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.4089611680
Short name T823
Test name
Test status
Simulation time 96960256 ps
CPU time 2.07 seconds
Started Jun 10 04:42:35 PM PDT 24
Finished Jun 10 04:42:38 PM PDT 24
Peak memory 197832 kb
Host smart-6f124d40-4313-42e2-9644-299283f5ff16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089611680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.4089611680
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.1417325863
Short name T842
Test name
Test status
Simulation time 124615030 ps
CPU time 0.6 seconds
Started Jun 10 04:45:02 PM PDT 24
Finished Jun 10 04:45:03 PM PDT 24
Peak memory 194192 kb
Host smart-067b07ba-d50f-49a9-8bf7-5355caa24168
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417325863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.1417325863
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.1487600330
Short name T798
Test name
Test status
Simulation time 45523126 ps
CPU time 0.62 seconds
Started Jun 10 04:45:24 PM PDT 24
Finished Jun 10 04:45:25 PM PDT 24
Peak memory 193560 kb
Host smart-7a918dd9-f117-44de-9497-99218a0af091
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487600330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.1487600330
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.2874685862
Short name T790
Test name
Test status
Simulation time 58253501 ps
CPU time 0.62 seconds
Started Jun 10 04:45:07 PM PDT 24
Finished Jun 10 04:45:08 PM PDT 24
Peak memory 194168 kb
Host smart-48da5431-ac58-4708-bda3-917f0ed3e5ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874685862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.2874685862
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.4028338809
Short name T765
Test name
Test status
Simulation time 47279970 ps
CPU time 0.59 seconds
Started Jun 10 04:45:07 PM PDT 24
Finished Jun 10 04:45:08 PM PDT 24
Peak memory 193424 kb
Host smart-a22a8328-e0cb-4c71-a5be-a3a9071099e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028338809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.4028338809
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.4272352548
Short name T784
Test name
Test status
Simulation time 67211670 ps
CPU time 0.58 seconds
Started Jun 10 04:45:09 PM PDT 24
Finished Jun 10 04:45:10 PM PDT 24
Peak memory 193516 kb
Host smart-0604756b-e9d4-4979-84c4-56de205af4b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272352548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.4272352548
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.2484950446
Short name T816
Test name
Test status
Simulation time 44963464 ps
CPU time 0.55 seconds
Started Jun 10 04:44:56 PM PDT 24
Finished Jun 10 04:44:57 PM PDT 24
Peak memory 193568 kb
Host smart-25e8a045-4113-4436-b6a6-a2948885c095
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484950446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.2484950446
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.3357294298
Short name T839
Test name
Test status
Simulation time 17033545 ps
CPU time 0.6 seconds
Started Jun 10 04:45:01 PM PDT 24
Finished Jun 10 04:45:02 PM PDT 24
Peak memory 193644 kb
Host smart-3dedc8e8-e6a3-4d94-b518-7df2f124625a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357294298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.3357294298
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.1748197539
Short name T822
Test name
Test status
Simulation time 12783712 ps
CPU time 0.57 seconds
Started Jun 10 04:44:58 PM PDT 24
Finished Jun 10 04:44:59 PM PDT 24
Peak memory 193444 kb
Host smart-7de4caeb-775a-44b1-9f46-66f2f7541447
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748197539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.1748197539
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.3320356188
Short name T804
Test name
Test status
Simulation time 18144895 ps
CPU time 0.6 seconds
Started Jun 10 04:45:00 PM PDT 24
Finished Jun 10 04:45:01 PM PDT 24
Peak memory 193468 kb
Host smart-0b7cc032-1fdc-47ca-97e3-10210669f9d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320356188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.3320356188
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.1520513786
Short name T794
Test name
Test status
Simulation time 59522822 ps
CPU time 0.59 seconds
Started Jun 10 04:45:00 PM PDT 24
Finished Jun 10 04:45:01 PM PDT 24
Peak memory 194048 kb
Host smart-bb6dee11-b6e4-40b2-9ec2-8c33e9109914
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520513786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.1520513786
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.4233394575
Short name T759
Test name
Test status
Simulation time 86026082 ps
CPU time 0.73 seconds
Started Jun 10 04:42:18 PM PDT 24
Finished Jun 10 04:42:21 PM PDT 24
Peak memory 195728 kb
Host smart-a306a027-ce73-4510-a378-cbd130627088
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233394575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.4233394575
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.3506440573
Short name T94
Test name
Test status
Simulation time 84768655 ps
CPU time 3.04 seconds
Started Jun 10 04:42:16 PM PDT 24
Finished Jun 10 04:42:21 PM PDT 24
Peak memory 196944 kb
Host smart-1ff23365-7d11-4c6e-afa9-4cb47a759614
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506440573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.3506440573
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3117474791
Short name T97
Test name
Test status
Simulation time 218665609 ps
CPU time 0.66 seconds
Started Jun 10 04:42:17 PM PDT 24
Finished Jun 10 04:42:20 PM PDT 24
Peak memory 195396 kb
Host smart-26565758-7a58-4a2e-bead-fdf2ecb82ce5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117474791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.3117474791
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.454283572
Short name T775
Test name
Test status
Simulation time 236875643 ps
CPU time 0.67 seconds
Started Jun 10 04:42:16 PM PDT 24
Finished Jun 10 04:42:18 PM PDT 24
Peak memory 197416 kb
Host smart-d3aafbd7-7a3b-4f85-8cf2-874b8f53a40c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454283572 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.454283572
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.474759527
Short name T807
Test name
Test status
Simulation time 14281290 ps
CPU time 0.58 seconds
Started Jun 10 04:42:16 PM PDT 24
Finished Jun 10 04:42:19 PM PDT 24
Peak memory 195056 kb
Host smart-dff75143-d8f1-4363-ba3a-fa43ba3548fe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474759527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_
csr_rw.474759527
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.1152644755
Short name T764
Test name
Test status
Simulation time 42023522 ps
CPU time 0.56 seconds
Started Jun 10 04:42:15 PM PDT 24
Finished Jun 10 04:42:16 PM PDT 24
Peak memory 194192 kb
Host smart-62571ba3-3730-4ac1-b693-40f678cdcf38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152644755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.1152644755
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.488812291
Short name T779
Test name
Test status
Simulation time 111311239 ps
CPU time 0.73 seconds
Started Jun 10 04:42:16 PM PDT 24
Finished Jun 10 04:42:19 PM PDT 24
Peak memory 195960 kb
Host smart-dbb82387-af17-4a8a-9031-ac15f54b0964
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488812291 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.gpio_same_csr_outstanding.488812291
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3627633391
Short name T763
Test name
Test status
Simulation time 114199193 ps
CPU time 2.51 seconds
Started Jun 10 04:42:16 PM PDT 24
Finished Jun 10 04:42:20 PM PDT 24
Peak memory 197892 kb
Host smart-5ec98ebc-ad90-4cac-8e69-790a6ffa5f8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627633391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.3627633391
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.2306303987
Short name T730
Test name
Test status
Simulation time 24853656 ps
CPU time 0.63 seconds
Started Jun 10 04:45:29 PM PDT 24
Finished Jun 10 04:45:30 PM PDT 24
Peak memory 193424 kb
Host smart-f05fec47-4e42-42eb-a2b0-2314f5dc885f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306303987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.2306303987
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.1724387726
Short name T803
Test name
Test status
Simulation time 45235914 ps
CPU time 0.58 seconds
Started Jun 10 04:45:07 PM PDT 24
Finished Jun 10 04:45:09 PM PDT 24
Peak memory 194112 kb
Host smart-8f0f0f30-2382-4485-937e-67578056283a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724387726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.1724387726
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.2612995915
Short name T760
Test name
Test status
Simulation time 62821092 ps
CPU time 0.6 seconds
Started Jun 10 04:45:04 PM PDT 24
Finished Jun 10 04:45:05 PM PDT 24
Peak memory 193500 kb
Host smart-4390e74a-3570-4ef2-8e2a-77b98d3badf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612995915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.2612995915
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.1638387679
Short name T741
Test name
Test status
Simulation time 19057471 ps
CPU time 0.55 seconds
Started Jun 10 04:44:59 PM PDT 24
Finished Jun 10 04:45:00 PM PDT 24
Peak memory 194132 kb
Host smart-c3a9adb0-da50-42c6-8fb4-93000b9e18b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638387679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.1638387679
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.2923599738
Short name T742
Test name
Test status
Simulation time 42063498 ps
CPU time 0.6 seconds
Started Jun 10 04:45:02 PM PDT 24
Finished Jun 10 04:45:03 PM PDT 24
Peak memory 194188 kb
Host smart-a86cc4e4-c543-490c-8733-5c4b17e1ed87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923599738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.2923599738
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.3190175183
Short name T836
Test name
Test status
Simulation time 16128132 ps
CPU time 0.59 seconds
Started Jun 10 04:44:57 PM PDT 24
Finished Jun 10 04:44:58 PM PDT 24
Peak memory 194208 kb
Host smart-634970a4-f38c-48bb-a6cf-d9a77f0a9442
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190175183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.3190175183
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.1317569844
Short name T785
Test name
Test status
Simulation time 34996430 ps
CPU time 0.58 seconds
Started Jun 10 04:44:58 PM PDT 24
Finished Jun 10 04:44:59 PM PDT 24
Peak memory 194292 kb
Host smart-a6e18bcc-6f3d-4f66-bbbd-80afd8c09dd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317569844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.1317569844
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.2708834285
Short name T782
Test name
Test status
Simulation time 12851590 ps
CPU time 0.56 seconds
Started Jun 10 04:45:15 PM PDT 24
Finished Jun 10 04:45:16 PM PDT 24
Peak memory 194124 kb
Host smart-f6221354-5070-48f3-ac97-9a301a4d5d88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708834285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.2708834285
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.1837926188
Short name T731
Test name
Test status
Simulation time 61636631 ps
CPU time 0.57 seconds
Started Jun 10 04:45:30 PM PDT 24
Finished Jun 10 04:45:31 PM PDT 24
Peak memory 193520 kb
Host smart-e00234d7-a6a8-4675-9608-43a598f39030
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837926188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.1837926188
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.325812703
Short name T753
Test name
Test status
Simulation time 12547128 ps
CPU time 0.59 seconds
Started Jun 10 04:44:57 PM PDT 24
Finished Jun 10 04:44:58 PM PDT 24
Peak memory 193536 kb
Host smart-6a4fcdb6-82bb-4952-ad35-3424d3eba060
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325812703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.325812703
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3096014219
Short name T95
Test name
Test status
Simulation time 25845703 ps
CPU time 0.75 seconds
Started Jun 10 04:42:18 PM PDT 24
Finished Jun 10 04:42:21 PM PDT 24
Peak memory 196380 kb
Host smart-e0b7ae3f-21f8-4979-9b05-d3b4e38e661c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096014219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.3096014219
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2285639353
Short name T834
Test name
Test status
Simulation time 176898555 ps
CPU time 2.35 seconds
Started Jun 10 04:44:44 PM PDT 24
Finished Jun 10 04:44:47 PM PDT 24
Peak memory 197788 kb
Host smart-0b9c21f2-c799-40de-be2d-987b8432ce53
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285639353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.2285639353
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3279194634
Short name T831
Test name
Test status
Simulation time 22443673 ps
CPU time 0.65 seconds
Started Jun 10 04:44:57 PM PDT 24
Finished Jun 10 04:44:58 PM PDT 24
Peak memory 195332 kb
Host smart-e26b6b5b-3c78-4f0e-b1b4-6b6b6d649f78
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279194634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.3279194634
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3273935081
Short name T780
Test name
Test status
Simulation time 18517631 ps
CPU time 0.63 seconds
Started Jun 10 04:42:17 PM PDT 24
Finished Jun 10 04:42:19 PM PDT 24
Peak memory 196276 kb
Host smart-604d7d12-b2d6-4df3-8013-8ab3e0c44cc8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273935081 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.3273935081
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1219088212
Short name T88
Test name
Test status
Simulation time 13800162 ps
CPU time 0.6 seconds
Started Jun 10 04:42:24 PM PDT 24
Finished Jun 10 04:42:25 PM PDT 24
Peak memory 195256 kb
Host smart-636ea7aa-c57c-4abe-8224-6dd8067ec4fb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219088212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.1219088212
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.239336296
Short name T754
Test name
Test status
Simulation time 43289749 ps
CPU time 0.57 seconds
Started Jun 10 04:42:28 PM PDT 24
Finished Jun 10 04:42:30 PM PDT 24
Peak memory 193408 kb
Host smart-d7ca3b24-5490-49b7-9822-a612cf965751
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239336296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.239336296
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1229334544
Short name T786
Test name
Test status
Simulation time 94066229 ps
CPU time 0.74 seconds
Started Jun 10 04:42:18 PM PDT 24
Finished Jun 10 04:42:21 PM PDT 24
Peak memory 196736 kb
Host smart-3932086e-ace5-4030-8819-89b908bb077a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229334544 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.1229334544
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3898436061
Short name T778
Test name
Test status
Simulation time 149280088 ps
CPU time 1.79 seconds
Started Jun 10 04:42:32 PM PDT 24
Finished Jun 10 04:42:35 PM PDT 24
Peak memory 197900 kb
Host smart-8da51215-d13d-49b1-ba89-497dd0c12f67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898436061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.3898436061
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3495742529
Short name T817
Test name
Test status
Simulation time 78801090 ps
CPU time 1.11 seconds
Started Jun 10 04:42:18 PM PDT 24
Finished Jun 10 04:42:22 PM PDT 24
Peak memory 197852 kb
Host smart-7abd1277-b6c4-4e4b-9e0e-132917d81fd1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495742529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.3495742529
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.1927671882
Short name T793
Test name
Test status
Simulation time 21050830 ps
CPU time 0.6 seconds
Started Jun 10 04:44:58 PM PDT 24
Finished Jun 10 04:44:59 PM PDT 24
Peak memory 193560 kb
Host smart-b17546b9-0417-48da-8d84-861a57cf48b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927671882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.1927671882
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.2676265841
Short name T727
Test name
Test status
Simulation time 44067633 ps
CPU time 0.61 seconds
Started Jun 10 04:45:00 PM PDT 24
Finished Jun 10 04:45:01 PM PDT 24
Peak memory 193588 kb
Host smart-5a025764-2cef-4438-b989-a7a18cfa102b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676265841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.2676265841
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.475678492
Short name T808
Test name
Test status
Simulation time 49481826 ps
CPU time 0.57 seconds
Started Jun 10 04:45:02 PM PDT 24
Finished Jun 10 04:45:03 PM PDT 24
Peak memory 194100 kb
Host smart-44c7cddb-f7c9-46fe-a4c2-a7e42e67f9fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475678492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.475678492
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.2459053962
Short name T755
Test name
Test status
Simulation time 32524000 ps
CPU time 0.57 seconds
Started Jun 10 04:45:04 PM PDT 24
Finished Jun 10 04:45:05 PM PDT 24
Peak memory 193456 kb
Host smart-792ef266-d7c1-48a0-9fab-20f77dfb9596
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459053962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.2459053962
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.4136147594
Short name T799
Test name
Test status
Simulation time 33811649 ps
CPU time 0.56 seconds
Started Jun 10 04:45:01 PM PDT 24
Finished Jun 10 04:45:01 PM PDT 24
Peak memory 193512 kb
Host smart-73bcfbc7-4a6d-4a68-9afe-677f8dc21942
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136147594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.4136147594
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.3247092908
Short name T762
Test name
Test status
Simulation time 13743177 ps
CPU time 0.55 seconds
Started Jun 10 04:45:19 PM PDT 24
Finished Jun 10 04:45:20 PM PDT 24
Peak memory 194128 kb
Host smart-6aa1e3c8-33c4-4f53-982b-baf4a32ad346
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247092908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.3247092908
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.2897518980
Short name T787
Test name
Test status
Simulation time 46477144 ps
CPU time 0.57 seconds
Started Jun 10 04:45:01 PM PDT 24
Finished Jun 10 04:45:02 PM PDT 24
Peak memory 193532 kb
Host smart-584a6101-105f-4932-bae2-b760d6fea004
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897518980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.2897518980
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.1713380805
Short name T821
Test name
Test status
Simulation time 46292463 ps
CPU time 0.59 seconds
Started Jun 10 04:45:04 PM PDT 24
Finished Jun 10 04:45:05 PM PDT 24
Peak memory 194132 kb
Host smart-ec8c7d9b-5cde-449b-b163-92ef62048183
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713380805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.1713380805
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.2173786776
Short name T832
Test name
Test status
Simulation time 43499938 ps
CPU time 0.61 seconds
Started Jun 10 04:45:27 PM PDT 24
Finished Jun 10 04:45:28 PM PDT 24
Peak memory 194196 kb
Host smart-bd461bb5-696a-4c3b-9ef9-09c06b520e96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173786776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.2173786776
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.3021744587
Short name T835
Test name
Test status
Simulation time 14762652 ps
CPU time 0.59 seconds
Started Jun 10 04:45:11 PM PDT 24
Finished Jun 10 04:45:12 PM PDT 24
Peak memory 193472 kb
Host smart-0b1fbeb8-4422-4358-aa8a-e0afdfd0d1aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021744587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.3021744587
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2129191383
Short name T726
Test name
Test status
Simulation time 38366349 ps
CPU time 1.5 seconds
Started Jun 10 04:44:54 PM PDT 24
Finished Jun 10 04:44:56 PM PDT 24
Peak memory 197880 kb
Host smart-a6c7e4b6-cf1e-405b-98e8-88184b4c43ce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129191383 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.2129191383
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.2503089581
Short name T74
Test name
Test status
Simulation time 11958671 ps
CPU time 0.54 seconds
Started Jun 10 04:44:52 PM PDT 24
Finished Jun 10 04:44:53 PM PDT 24
Peak memory 193152 kb
Host smart-9924e113-6df2-4454-9629-ecb996b9afee
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503089581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.2503089581
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.3537290552
Short name T818
Test name
Test status
Simulation time 14819791 ps
CPU time 0.6 seconds
Started Jun 10 04:44:53 PM PDT 24
Finished Jun 10 04:44:55 PM PDT 24
Peak memory 193504 kb
Host smart-d441d4f2-da49-42f1-93d8-4f484b717562
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537290552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.3537290552
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3358649425
Short name T108
Test name
Test status
Simulation time 26629127 ps
CPU time 0.65 seconds
Started Jun 10 04:44:45 PM PDT 24
Finished Jun 10 04:44:46 PM PDT 24
Peak memory 195472 kb
Host smart-4674ce96-75d6-460d-ae62-3652d4963ec1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358649425 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.3358649425
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3910715216
Short name T729
Test name
Test status
Simulation time 106748154 ps
CPU time 1.37 seconds
Started Jun 10 04:44:49 PM PDT 24
Finished Jun 10 04:44:51 PM PDT 24
Peak memory 197920 kb
Host smart-d96d66dc-e62d-46b2-913e-dd46d6cc1479
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910715216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.3910715216
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.2438592800
Short name T783
Test name
Test status
Simulation time 44240877 ps
CPU time 0.89 seconds
Started Jun 10 04:44:56 PM PDT 24
Finished Jun 10 04:44:57 PM PDT 24
Peak memory 197084 kb
Host smart-e19756ab-684d-4122-885c-3daddcf2250e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438592800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.2438592800
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1770382153
Short name T761
Test name
Test status
Simulation time 32964037 ps
CPU time 0.85 seconds
Started Jun 10 04:44:52 PM PDT 24
Finished Jun 10 04:44:54 PM PDT 24
Peak memory 197864 kb
Host smart-6e52a906-9df4-4e47-8286-0d6ae14b77a0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770382153 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.1770382153
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.227074589
Short name T87
Test name
Test status
Simulation time 11805707 ps
CPU time 0.6 seconds
Started Jun 10 04:44:53 PM PDT 24
Finished Jun 10 04:44:54 PM PDT 24
Peak memory 194716 kb
Host smart-a72edf5b-d5e8-4931-82e9-c197ae6a7c79
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227074589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_
csr_rw.227074589
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.2224761618
Short name T801
Test name
Test status
Simulation time 22481060 ps
CPU time 0.55 seconds
Started Jun 10 04:44:53 PM PDT 24
Finished Jun 10 04:44:53 PM PDT 24
Peak memory 193432 kb
Host smart-57beeac9-6960-471c-bcbf-8849ae2a5a67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224761618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.2224761618
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.750513002
Short name T796
Test name
Test status
Simulation time 36995653 ps
CPU time 0.88 seconds
Started Jun 10 04:44:53 PM PDT 24
Finished Jun 10 04:44:54 PM PDT 24
Peak memory 197712 kb
Host smart-7544c27b-f63b-43ed-acf1-e20a96d8ba35
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750513002 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 6.gpio_same_csr_outstanding.750513002
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.851670923
Short name T843
Test name
Test status
Simulation time 48624925 ps
CPU time 0.91 seconds
Started Jun 10 04:44:44 PM PDT 24
Finished Jun 10 04:44:46 PM PDT 24
Peak memory 197792 kb
Host smart-bba47858-b006-4a4c-ba30-3e57cf5716fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851670923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.851670923
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3247058606
Short name T830
Test name
Test status
Simulation time 92139205 ps
CPU time 1.21 seconds
Started Jun 10 04:44:52 PM PDT 24
Finished Jun 10 04:44:54 PM PDT 24
Peak memory 197572 kb
Host smart-269d1f1d-0773-4058-96a0-5df84a133f53
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247058606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.3247058606
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.3109209478
Short name T756
Test name
Test status
Simulation time 30028782 ps
CPU time 0.8 seconds
Started Jun 10 04:44:55 PM PDT 24
Finished Jun 10 04:44:56 PM PDT 24
Peak memory 197848 kb
Host smart-505dd82c-6fdc-4939-88de-1f7581ea7b6a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109209478 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.3109209478
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3457049144
Short name T811
Test name
Test status
Simulation time 36065286 ps
CPU time 0.64 seconds
Started Jun 10 04:44:41 PM PDT 24
Finished Jun 10 04:44:42 PM PDT 24
Peak memory 194696 kb
Host smart-81119f4d-4ead-4535-9655-00c0d6bbdced
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457049144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.3457049144
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.3460051703
Short name T820
Test name
Test status
Simulation time 29131523 ps
CPU time 0.59 seconds
Started Jun 10 04:44:49 PM PDT 24
Finished Jun 10 04:44:50 PM PDT 24
Peak memory 193504 kb
Host smart-41fdb677-5776-4f9e-9bce-4bd0f56cafe0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460051703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.3460051703
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3035400516
Short name T106
Test name
Test status
Simulation time 53013087 ps
CPU time 0.75 seconds
Started Jun 10 04:44:57 PM PDT 24
Finished Jun 10 04:44:59 PM PDT 24
Peak memory 196716 kb
Host smart-2e03cad8-0193-4b58-a612-ba9afe59d825
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035400516 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.3035400516
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3061498310
Short name T736
Test name
Test status
Simulation time 325001956 ps
CPU time 2.61 seconds
Started Jun 10 04:44:59 PM PDT 24
Finished Jun 10 04:45:02 PM PDT 24
Peak memory 197880 kb
Host smart-d83c9896-8183-4713-99ef-dc433bb9d1e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061498310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.3061498310
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.17159065
Short name T40
Test name
Test status
Simulation time 255627232 ps
CPU time 0.83 seconds
Started Jun 10 04:44:53 PM PDT 24
Finished Jun 10 04:44:55 PM PDT 24
Peak memory 197840 kb
Host smart-db0f9390-0896-4ca2-9ca2-fc18809917fb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17159065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
7.gpio_tl_intg_err.17159065
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.2161268684
Short name T771
Test name
Test status
Simulation time 30427980 ps
CPU time 0.83 seconds
Started Jun 10 04:44:49 PM PDT 24
Finished Jun 10 04:44:51 PM PDT 24
Peak memory 197764 kb
Host smart-f1c6dde9-2ef4-4814-8669-5daf2a44c9f1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161268684 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.2161268684
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.1621617520
Short name T99
Test name
Test status
Simulation time 23849761 ps
CPU time 0.58 seconds
Started Jun 10 04:44:54 PM PDT 24
Finished Jun 10 04:44:55 PM PDT 24
Peak memory 194704 kb
Host smart-9cace71a-7758-4a24-b5d6-707d1ea1dfc6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621617520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.1621617520
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.4260355525
Short name T768
Test name
Test status
Simulation time 14633586 ps
CPU time 0.62 seconds
Started Jun 10 04:44:55 PM PDT 24
Finished Jun 10 04:44:56 PM PDT 24
Peak memory 194188 kb
Host smart-ee2d23ad-f234-4a28-8cde-6decbb36d929
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260355525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.4260355525
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.2457870056
Short name T72
Test name
Test status
Simulation time 239030284 ps
CPU time 0.67 seconds
Started Jun 10 04:44:51 PM PDT 24
Finished Jun 10 04:44:52 PM PDT 24
Peak memory 195000 kb
Host smart-fe6de2c7-8db1-4896-a469-13e5d694e3dc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457870056 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.2457870056
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1013037350
Short name T748
Test name
Test status
Simulation time 2016254111 ps
CPU time 2.3 seconds
Started Jun 10 04:44:57 PM PDT 24
Finished Jun 10 04:45:00 PM PDT 24
Peak memory 197816 kb
Host smart-15c0fe05-42dc-4088-8c59-cde20c2e3c9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013037350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.1013037350
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.4204212210
Short name T24
Test name
Test status
Simulation time 123635656 ps
CPU time 1.21 seconds
Started Jun 10 04:44:38 PM PDT 24
Finished Jun 10 04:44:39 PM PDT 24
Peak memory 197872 kb
Host smart-52bd686e-9ab1-43e3-bdf6-fc10346e8236
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204212210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.4204212210
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.867982855
Short name T739
Test name
Test status
Simulation time 30838932 ps
CPU time 0.9 seconds
Started Jun 10 04:44:54 PM PDT 24
Finished Jun 10 04:44:55 PM PDT 24
Peak memory 197892 kb
Host smart-4577a483-30c5-47e4-b5c2-e86f94e8dd70
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867982855 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.867982855
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3634884414
Short name T809
Test name
Test status
Simulation time 27535278 ps
CPU time 0.57 seconds
Started Jun 10 04:44:47 PM PDT 24
Finished Jun 10 04:44:48 PM PDT 24
Peak memory 194436 kb
Host smart-044ed6bf-2813-4068-97e5-aa2c909961f6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634884414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.3634884414
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.120032280
Short name T810
Test name
Test status
Simulation time 14130559 ps
CPU time 0.59 seconds
Started Jun 10 04:44:59 PM PDT 24
Finished Jun 10 04:45:00 PM PDT 24
Peak memory 193540 kb
Host smart-36e29e0b-7601-48b1-ae1f-2446ccb41879
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120032280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.120032280
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.1045890758
Short name T103
Test name
Test status
Simulation time 19608782 ps
CPU time 0.63 seconds
Started Jun 10 04:44:51 PM PDT 24
Finished Jun 10 04:44:52 PM PDT 24
Peak memory 195408 kb
Host smart-fc88da9b-374d-4ef5-972f-2bf6de22b906
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045890758 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.1045890758
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1483549546
Short name T815
Test name
Test status
Simulation time 103466976 ps
CPU time 2.34 seconds
Started Jun 10 04:44:51 PM PDT 24
Finished Jun 10 04:44:54 PM PDT 24
Peak memory 197892 kb
Host smart-1507c494-6b3c-4dfb-bc7b-5cb7ac1b750f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483549546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.1483549546
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3130817096
Short name T34
Test name
Test status
Simulation time 238764542 ps
CPU time 1.5 seconds
Started Jun 10 04:44:57 PM PDT 24
Finished Jun 10 04:44:58 PM PDT 24
Peak memory 197944 kb
Host smart-c2047555-83a8-4225-9bbf-87799ea6ee38
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130817096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.3130817096
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.2456807206
Short name T632
Test name
Test status
Simulation time 28948441 ps
CPU time 0.59 seconds
Started Jun 10 05:53:38 PM PDT 24
Finished Jun 10 05:53:39 PM PDT 24
Peak memory 194852 kb
Host smart-a1e3474e-c3a3-40ec-ae5f-473cbafc2e14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456807206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.2456807206
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.4185713914
Short name T556
Test name
Test status
Simulation time 78961225 ps
CPU time 0.65 seconds
Started Jun 10 05:53:36 PM PDT 24
Finished Jun 10 05:53:37 PM PDT 24
Peak memory 194204 kb
Host smart-7a74a792-4d22-4a37-ac7f-9076d6578376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185713914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.4185713914
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.1810135709
Short name T634
Test name
Test status
Simulation time 783071266 ps
CPU time 5.91 seconds
Started Jun 10 05:53:37 PM PDT 24
Finished Jun 10 05:53:43 PM PDT 24
Peak memory 195592 kb
Host smart-0b7eff81-6615-4140-9ef4-33f666fe7b59
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810135709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.1810135709
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.4221179494
Short name T719
Test name
Test status
Simulation time 44272324 ps
CPU time 0.73 seconds
Started Jun 10 05:53:34 PM PDT 24
Finished Jun 10 05:53:35 PM PDT 24
Peak memory 194892 kb
Host smart-6815fdef-694e-4e25-8c97-456a4c00ef34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221179494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.4221179494
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.4095427564
Short name T592
Test name
Test status
Simulation time 50910656 ps
CPU time 1.31 seconds
Started Jun 10 05:53:35 PM PDT 24
Finished Jun 10 05:53:36 PM PDT 24
Peak memory 197032 kb
Host smart-f9dba17b-6c6f-4398-be1e-def643c7c2c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095427564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.4095427564
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.1129007651
Short name T711
Test name
Test status
Simulation time 64610980 ps
CPU time 2.52 seconds
Started Jun 10 05:53:35 PM PDT 24
Finished Jun 10 05:53:38 PM PDT 24
Peak memory 196492 kb
Host smart-66a2ca75-1d97-4b6b-9b7e-6e4af31640c6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129007651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.1129007651
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.2552641328
Short name T535
Test name
Test status
Simulation time 142896567 ps
CPU time 1.3 seconds
Started Jun 10 05:53:37 PM PDT 24
Finished Jun 10 05:53:39 PM PDT 24
Peak memory 196744 kb
Host smart-616a3872-d809-48c3-8d98-97e37996303e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552641328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
2552641328
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.644095564
Short name T659
Test name
Test status
Simulation time 161475098 ps
CPU time 0.96 seconds
Started Jun 10 05:53:40 PM PDT 24
Finished Jun 10 05:53:42 PM PDT 24
Peak memory 195892 kb
Host smart-852c3c4b-2587-4212-92fb-f0de838d361a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644095564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.644095564
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.3711831856
Short name T184
Test name
Test status
Simulation time 43312948 ps
CPU time 0.86 seconds
Started Jun 10 05:53:29 PM PDT 24
Finished Jun 10 05:53:30 PM PDT 24
Peak memory 197332 kb
Host smart-6bc6184f-0da0-444a-9b8e-7707704bc3dc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711831856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.3711831856
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.40518293
Short name T123
Test name
Test status
Simulation time 29051145 ps
CPU time 1.46 seconds
Started Jun 10 05:53:38 PM PDT 24
Finished Jun 10 05:53:40 PM PDT 24
Peak memory 198000 kb
Host smart-8948f778-8598-4a12-a6ba-95bcf9e68ed1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40518293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rando
m_long_reg_writes_reg_reads.40518293
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.1223729257
Short name T671
Test name
Test status
Simulation time 66613803 ps
CPU time 1.41 seconds
Started Jun 10 05:53:29 PM PDT 24
Finished Jun 10 05:53:31 PM PDT 24
Peak memory 197000 kb
Host smart-8b39bd2f-36de-476e-9cf9-1f223a35472e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223729257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.1223729257
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.33014893
Short name T120
Test name
Test status
Simulation time 121228670 ps
CPU time 1.03 seconds
Started Jun 10 05:53:30 PM PDT 24
Finished Jun 10 05:53:32 PM PDT 24
Peak memory 196460 kb
Host smart-6b682159-674b-4d92-b659-3f5f18dc5e78
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33014893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.33014893
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.2885041293
Short name T134
Test name
Test status
Simulation time 45462760928 ps
CPU time 163.31 seconds
Started Jun 10 05:53:38 PM PDT 24
Finished Jun 10 05:56:21 PM PDT 24
Peak memory 198244 kb
Host smart-db74a8b7-f53c-4a09-a7c3-5d410f936a35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885041293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.2885041293
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.2226798948
Short name T62
Test name
Test status
Simulation time 24713290 ps
CPU time 0.61 seconds
Started Jun 10 05:53:32 PM PDT 24
Finished Jun 10 05:53:33 PM PDT 24
Peak memory 193940 kb
Host smart-6d9a6887-15ec-447b-8a21-522b39644c63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226798948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.2226798948
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.2277575309
Short name T653
Test name
Test status
Simulation time 188614724 ps
CPU time 0.92 seconds
Started Jun 10 05:53:33 PM PDT 24
Finished Jun 10 05:53:35 PM PDT 24
Peak memory 196716 kb
Host smart-84523222-5850-4e09-80b4-aa1a8923633d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277575309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.2277575309
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.932039782
Short name T349
Test name
Test status
Simulation time 323407427 ps
CPU time 5.41 seconds
Started Jun 10 05:53:36 PM PDT 24
Finished Jun 10 05:53:42 PM PDT 24
Peak memory 197168 kb
Host smart-528691a7-fe79-480a-8caa-90711d610dc2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932039782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stress
.932039782
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.2226187470
Short name T686
Test name
Test status
Simulation time 87150993 ps
CPU time 0.98 seconds
Started Jun 10 05:53:33 PM PDT 24
Finished Jun 10 05:53:34 PM PDT 24
Peak memory 197084 kb
Host smart-d81d7cc5-7a59-4b43-9a3f-9ccf2c6689aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226187470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.2226187470
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.140771039
Short name T518
Test name
Test status
Simulation time 196298104 ps
CPU time 1.14 seconds
Started Jun 10 05:53:42 PM PDT 24
Finished Jun 10 05:53:44 PM PDT 24
Peak memory 196112 kb
Host smart-90919586-cbfa-4258-a966-ee295c1d50cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140771039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.140771039
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.3217196779
Short name T216
Test name
Test status
Simulation time 82228011 ps
CPU time 1.52 seconds
Started Jun 10 05:53:33 PM PDT 24
Finished Jun 10 05:53:35 PM PDT 24
Peak memory 196476 kb
Host smart-c807e6b1-7cd6-40da-ba6c-82826e44514c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217196779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.3217196779
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.4026720146
Short name T552
Test name
Test status
Simulation time 398028910 ps
CPU time 2.71 seconds
Started Jun 10 05:53:32 PM PDT 24
Finished Jun 10 05:53:35 PM PDT 24
Peak memory 197224 kb
Host smart-77b6d425-66e2-42f4-860b-e5aadcf87b16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026720146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
4026720146
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.4022107930
Short name T228
Test name
Test status
Simulation time 26860503 ps
CPU time 0.97 seconds
Started Jun 10 05:53:39 PM PDT 24
Finished Jun 10 05:53:41 PM PDT 24
Peak memory 196584 kb
Host smart-9fa750fc-2372-4c1b-aaec-10f9a3f9b4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022107930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.4022107930
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.3267520046
Short name T275
Test name
Test status
Simulation time 62984756 ps
CPU time 1.31 seconds
Started Jun 10 05:53:36 PM PDT 24
Finished Jun 10 05:53:38 PM PDT 24
Peak memory 196956 kb
Host smart-c436926b-cb40-4796-bc42-ef842aa68561
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267520046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.3267520046
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.2813610606
Short name T296
Test name
Test status
Simulation time 372855891 ps
CPU time 5.91 seconds
Started Jun 10 05:53:33 PM PDT 24
Finished Jun 10 05:53:39 PM PDT 24
Peak memory 198108 kb
Host smart-59b51624-15b1-482b-a33c-026ec5b18421
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813610606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.2813610606
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.2446556500
Short name T29
Test name
Test status
Simulation time 103959549 ps
CPU time 0.98 seconds
Started Jun 10 05:53:35 PM PDT 24
Finished Jun 10 05:53:36 PM PDT 24
Peak memory 213772 kb
Host smart-7fee9c3a-fb3f-45ba-8b68-8dcf07170d0d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446556500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.2446556500
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.2567561484
Short name T415
Test name
Test status
Simulation time 519827369 ps
CPU time 1.1 seconds
Started Jun 10 05:53:37 PM PDT 24
Finished Jun 10 05:53:38 PM PDT 24
Peak memory 196288 kb
Host smart-3b3391bd-4eca-4653-8bbf-861e442aa7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567561484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.2567561484
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.2592498149
Short name T649
Test name
Test status
Simulation time 43472285 ps
CPU time 1.43 seconds
Started Jun 10 05:53:40 PM PDT 24
Finished Jun 10 05:53:41 PM PDT 24
Peak memory 196872 kb
Host smart-ce412d89-1c90-4f45-9968-5fa97c0c27b5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592498149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.2592498149
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.3153868743
Short name T715
Test name
Test status
Simulation time 49994475429 ps
CPU time 71.25 seconds
Started Jun 10 05:53:36 PM PDT 24
Finished Jun 10 05:54:48 PM PDT 24
Peak memory 198228 kb
Host smart-3292ed6b-62ad-41f2-9974-618dac413896
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153868743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.3153868743
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.1703116769
Short name T678
Test name
Test status
Simulation time 43522174 ps
CPU time 0.57 seconds
Started Jun 10 05:54:07 PM PDT 24
Finished Jun 10 05:54:08 PM PDT 24
Peak memory 193888 kb
Host smart-bec74eb2-06dc-4e73-9679-db1f03bfb049
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703116769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.1703116769
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.2963515864
Short name T326
Test name
Test status
Simulation time 43977767 ps
CPU time 0.89 seconds
Started Jun 10 05:54:05 PM PDT 24
Finished Jun 10 05:54:07 PM PDT 24
Peak memory 197372 kb
Host smart-24fadce0-375e-4081-851f-4c0b6b6af57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963515864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.2963515864
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.3178321599
Short name T264
Test name
Test status
Simulation time 2236233544 ps
CPU time 17.51 seconds
Started Jun 10 05:54:05 PM PDT 24
Finished Jun 10 05:54:23 PM PDT 24
Peak memory 198132 kb
Host smart-2808e06c-6ec1-46e6-a4bc-812e68018c6d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178321599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.3178321599
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.3837273695
Short name T348
Test name
Test status
Simulation time 263123756 ps
CPU time 1 seconds
Started Jun 10 05:54:02 PM PDT 24
Finished Jun 10 05:54:03 PM PDT 24
Peak memory 196596 kb
Host smart-df0ce619-3b41-48fb-a9f1-52aae71205be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837273695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.3837273695
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.409661896
Short name T692
Test name
Test status
Simulation time 39764296 ps
CPU time 1.13 seconds
Started Jun 10 05:54:03 PM PDT 24
Finished Jun 10 05:54:04 PM PDT 24
Peak memory 196196 kb
Host smart-116a50e8-27c5-4d12-a54e-567859469227
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409661896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.409661896
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.278318511
Short name T269
Test name
Test status
Simulation time 601720254 ps
CPU time 2.36 seconds
Started Jun 10 05:54:06 PM PDT 24
Finished Jun 10 05:54:09 PM PDT 24
Peak memory 198156 kb
Host smart-fbace817-adc5-4459-b425-d230eae047e1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278318511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.gpio_intr_with_filter_rand_intr_event.278318511
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.239050785
Short name T716
Test name
Test status
Simulation time 66638605 ps
CPU time 1.61 seconds
Started Jun 10 05:54:07 PM PDT 24
Finished Jun 10 05:54:09 PM PDT 24
Peak memory 195912 kb
Host smart-b2130933-3a48-41f1-9710-114f9a73b92a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239050785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger.
239050785
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.2953545560
Short name T383
Test name
Test status
Simulation time 24973318 ps
CPU time 0.99 seconds
Started Jun 10 05:54:01 PM PDT 24
Finished Jun 10 05:54:03 PM PDT 24
Peak memory 195976 kb
Host smart-9573d684-89e4-48e3-9968-9daed3edfcd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953545560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.2953545560
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.761347585
Short name T261
Test name
Test status
Simulation time 32261440 ps
CPU time 0.93 seconds
Started Jun 10 05:54:05 PM PDT 24
Finished Jun 10 05:54:06 PM PDT 24
Peak memory 196720 kb
Host smart-afd5f102-1f3a-4562-9f9e-6855907dbb76
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761347585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullup
_pulldown.761347585
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.1470080693
Short name T549
Test name
Test status
Simulation time 74892605 ps
CPU time 3.35 seconds
Started Jun 10 05:54:04 PM PDT 24
Finished Jun 10 05:54:08 PM PDT 24
Peak memory 198056 kb
Host smart-8201b652-c594-4c4a-a1a9-334e609eb193
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470080693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.1470080693
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.1578499672
Short name T149
Test name
Test status
Simulation time 342367098 ps
CPU time 1.1 seconds
Started Jun 10 05:54:01 PM PDT 24
Finished Jun 10 05:54:08 PM PDT 24
Peak memory 195580 kb
Host smart-6ca5a96a-a6d0-442a-af9e-43f9e407580c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578499672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.1578499672
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.419424608
Short name T487
Test name
Test status
Simulation time 405143439 ps
CPU time 1.22 seconds
Started Jun 10 05:53:57 PM PDT 24
Finished Jun 10 05:53:59 PM PDT 24
Peak memory 195888 kb
Host smart-16ebdad1-8b6f-4bdf-bddd-5ca48225528a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419424608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.419424608
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.3968544348
Short name T164
Test name
Test status
Simulation time 49464624001 ps
CPU time 191.74 seconds
Started Jun 10 05:54:05 PM PDT 24
Finished Jun 10 05:57:17 PM PDT 24
Peak memory 198268 kb
Host smart-ff88d7cb-31c3-45fd-b1b9-7816bfb6019d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968544348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.3968544348
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.2657730968
Short name T52
Test name
Test status
Simulation time 194993921997 ps
CPU time 2037.4 seconds
Started Jun 10 05:54:06 PM PDT 24
Finished Jun 10 06:28:04 PM PDT 24
Peak memory 198328 kb
Host smart-3439f76e-e54c-435d-a582-322862c6bb55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2657730968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.2657730968
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.635711148
Short name T437
Test name
Test status
Simulation time 11924812 ps
CPU time 0.56 seconds
Started Jun 10 05:54:06 PM PDT 24
Finished Jun 10 05:54:07 PM PDT 24
Peak memory 194628 kb
Host smart-b1144de9-f72d-452f-ba6b-c040fb4a4db9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635711148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.635711148
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.1200302353
Short name T358
Test name
Test status
Simulation time 29221613 ps
CPU time 0.82 seconds
Started Jun 10 05:54:07 PM PDT 24
Finished Jun 10 05:54:08 PM PDT 24
Peak memory 196060 kb
Host smart-04a7e630-a7c9-4ff0-8df9-de8048f5d71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200302353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.1200302353
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.2491897132
Short name T305
Test name
Test status
Simulation time 546781273 ps
CPU time 28.69 seconds
Started Jun 10 05:54:01 PM PDT 24
Finished Jun 10 05:54:30 PM PDT 24
Peak memory 198056 kb
Host smart-eae5a837-267a-4e3a-89f9-1bb08721f953
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491897132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.2491897132
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.2317660899
Short name T45
Test name
Test status
Simulation time 100395132 ps
CPU time 0.65 seconds
Started Jun 10 05:54:04 PM PDT 24
Finished Jun 10 05:54:05 PM PDT 24
Peak memory 194704 kb
Host smart-bfc07ecc-be03-4bdd-8792-6ef2abdcdda7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317660899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.2317660899
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.339575544
Short name T441
Test name
Test status
Simulation time 114217984 ps
CPU time 0.82 seconds
Started Jun 10 05:54:06 PM PDT 24
Finished Jun 10 05:54:07 PM PDT 24
Peak memory 195620 kb
Host smart-5c7bb752-193f-48e6-93bf-a47a21828c6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339575544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.339575544
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.2431253287
Short name T13
Test name
Test status
Simulation time 211058239 ps
CPU time 2.32 seconds
Started Jun 10 05:54:04 PM PDT 24
Finished Jun 10 05:54:07 PM PDT 24
Peak memory 198140 kb
Host smart-0e8e4db3-8036-4435-829b-a5540e60d92e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431253287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.2431253287
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.1187682940
Short name T625
Test name
Test status
Simulation time 38341487 ps
CPU time 1.32 seconds
Started Jun 10 05:54:08 PM PDT 24
Finished Jun 10 05:54:10 PM PDT 24
Peak memory 196292 kb
Host smart-b8fd99ee-e641-44bc-abdd-5303dcb3a0b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187682940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.1187682940
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.2378983836
Short name T276
Test name
Test status
Simulation time 17933613 ps
CPU time 0.79 seconds
Started Jun 10 05:54:08 PM PDT 24
Finished Jun 10 05:54:09 PM PDT 24
Peak memory 196560 kb
Host smart-6f7def9e-3f82-4e85-b46d-67b3331cdbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378983836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.2378983836
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.3090319579
Short name T316
Test name
Test status
Simulation time 36123060 ps
CPU time 0.96 seconds
Started Jun 10 05:54:07 PM PDT 24
Finished Jun 10 05:54:08 PM PDT 24
Peak memory 196652 kb
Host smart-81c349c0-853a-437e-8c42-553732e16a97
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090319579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.3090319579
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.718780172
Short name T579
Test name
Test status
Simulation time 122717547 ps
CPU time 1.89 seconds
Started Jun 10 05:54:16 PM PDT 24
Finished Jun 10 05:54:23 PM PDT 24
Peak memory 198016 kb
Host smart-a13f852f-c2d5-47c4-bd97-f0401b91620d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718780172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ran
dom_long_reg_writes_reg_reads.718780172
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.3803908263
Short name T546
Test name
Test status
Simulation time 32198104 ps
CPU time 1.05 seconds
Started Jun 10 05:54:13 PM PDT 24
Finished Jun 10 05:54:14 PM PDT 24
Peak memory 195700 kb
Host smart-a83d5906-3fca-4fa8-beaa-32b6769ef11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803908263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.3803908263
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.1445459271
Short name T631
Test name
Test status
Simulation time 59764652 ps
CPU time 1.09 seconds
Started Jun 10 05:54:05 PM PDT 24
Finished Jun 10 05:54:06 PM PDT 24
Peak memory 195616 kb
Host smart-eb4c06d2-cac5-49b3-a52a-648d8f07edaa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445459271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.1445459271
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.3323959878
Short name T321
Test name
Test status
Simulation time 96387095584 ps
CPU time 206.7 seconds
Started Jun 10 05:54:08 PM PDT 24
Finished Jun 10 05:57:35 PM PDT 24
Peak memory 198232 kb
Host smart-ea71037e-b2a1-4f34-9d86-988f7c90c9cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323959878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.3323959878
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.999456148
Short name T21
Test name
Test status
Simulation time 437169418086 ps
CPU time 869.87 seconds
Started Jun 10 05:54:06 PM PDT 24
Finished Jun 10 06:08:36 PM PDT 24
Peak memory 198332 kb
Host smart-c1ec2ab4-0b6e-41cd-9872-471aff0f0846
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=999456148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.999456148
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.3696542129
Short name T221
Test name
Test status
Simulation time 98672148 ps
CPU time 0.56 seconds
Started Jun 10 05:54:05 PM PDT 24
Finished Jun 10 05:54:06 PM PDT 24
Peak memory 193944 kb
Host smart-50438895-542b-4624-9e42-e2cdc7f08c99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696542129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.3696542129
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.2312578691
Short name T515
Test name
Test status
Simulation time 15846859 ps
CPU time 0.68 seconds
Started Jun 10 05:54:08 PM PDT 24
Finished Jun 10 05:54:09 PM PDT 24
Peak memory 194944 kb
Host smart-795c4fe6-9948-4989-a45d-864e0dd99a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312578691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.2312578691
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.383040774
Short name T545
Test name
Test status
Simulation time 1844119008 ps
CPU time 24.28 seconds
Started Jun 10 05:54:07 PM PDT 24
Finished Jun 10 05:54:31 PM PDT 24
Peak memory 196932 kb
Host smart-07bbddf5-7903-43ec-8293-dabfbba7dfab
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383040774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stres
s.383040774
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.1279138366
Short name T234
Test name
Test status
Simulation time 308099184 ps
CPU time 1.09 seconds
Started Jun 10 05:54:06 PM PDT 24
Finished Jun 10 05:54:08 PM PDT 24
Peak memory 197784 kb
Host smart-9f4dc860-ef65-4f1a-b34d-5ec4f73ec923
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279138366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.1279138366
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.1989407381
Short name T590
Test name
Test status
Simulation time 131683755 ps
CPU time 0.85 seconds
Started Jun 10 05:54:04 PM PDT 24
Finished Jun 10 05:54:05 PM PDT 24
Peak memory 196376 kb
Host smart-e4326c44-94c1-4665-bbe0-53bd21743c0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989407381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.1989407381
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.3617165933
Short name T254
Test name
Test status
Simulation time 1397945159 ps
CPU time 3.52 seconds
Started Jun 10 05:54:07 PM PDT 24
Finished Jun 10 05:54:11 PM PDT 24
Peak memory 198112 kb
Host smart-ef4068bc-c349-49cd-9f18-654f34a155eb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617165933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.3617165933
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.3079367709
Short name T473
Test name
Test status
Simulation time 479185238 ps
CPU time 1.76 seconds
Started Jun 10 05:54:10 PM PDT 24
Finished Jun 10 05:54:12 PM PDT 24
Peak memory 196128 kb
Host smart-6cb70660-ad13-48b7-8008-925473e448fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079367709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.3079367709
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.1923887599
Short name T302
Test name
Test status
Simulation time 45554323 ps
CPU time 1.09 seconds
Started Jun 10 05:54:10 PM PDT 24
Finished Jun 10 05:54:17 PM PDT 24
Peak memory 196088 kb
Host smart-31878e08-ee06-466f-9310-198c033a9f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923887599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.1923887599
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.412563924
Short name T147
Test name
Test status
Simulation time 56763829 ps
CPU time 0.89 seconds
Started Jun 10 05:54:07 PM PDT 24
Finished Jun 10 05:54:08 PM PDT 24
Peak memory 197280 kb
Host smart-631c232d-ca1a-4f51-a2a7-35b0f0dc5e28
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412563924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullup
_pulldown.412563924
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.2764855040
Short name T377
Test name
Test status
Simulation time 490753219 ps
CPU time 2.21 seconds
Started Jun 10 05:54:06 PM PDT 24
Finished Jun 10 05:54:09 PM PDT 24
Peak memory 197976 kb
Host smart-f1acb63b-75f4-4f39-8005-461a5b515ff6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764855040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.2764855040
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.2535858250
Short name T400
Test name
Test status
Simulation time 246890256 ps
CPU time 0.78 seconds
Started Jun 10 05:54:07 PM PDT 24
Finished Jun 10 05:54:08 PM PDT 24
Peak memory 195240 kb
Host smart-d1e4141d-94e5-4d18-9cc4-4590a18f3275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535858250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.2535858250
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.1160086067
Short name T370
Test name
Test status
Simulation time 89296489 ps
CPU time 1.14 seconds
Started Jun 10 05:54:05 PM PDT 24
Finished Jun 10 05:54:07 PM PDT 24
Peak memory 196572 kb
Host smart-eb82b88e-8357-4cd3-81d6-06cf793ca712
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160086067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.1160086067
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.3101385654
Short name T335
Test name
Test status
Simulation time 68149135427 ps
CPU time 189.77 seconds
Started Jun 10 05:54:08 PM PDT 24
Finished Jun 10 05:57:18 PM PDT 24
Peak memory 198288 kb
Host smart-5489b26f-e08e-4427-a231-fbcff04564de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101385654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.3101385654
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.3447729469
Short name T438
Test name
Test status
Simulation time 71676149223 ps
CPU time 1503.76 seconds
Started Jun 10 05:54:06 PM PDT 24
Finished Jun 10 06:19:10 PM PDT 24
Peak memory 198264 kb
Host smart-80870c05-dd35-425d-8479-3c420ec7831f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3447729469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.3447729469
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.1554387999
Short name T246
Test name
Test status
Simulation time 44916254 ps
CPU time 0.92 seconds
Started Jun 10 05:54:11 PM PDT 24
Finished Jun 10 05:54:12 PM PDT 24
Peak memory 195280 kb
Host smart-9ef1eef0-6864-4d0f-9ddc-2184c94f1bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554387999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.1554387999
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.673339714
Short name T114
Test name
Test status
Simulation time 470624082 ps
CPU time 24.08 seconds
Started Jun 10 05:54:11 PM PDT 24
Finished Jun 10 05:54:35 PM PDT 24
Peak memory 198056 kb
Host smart-5d16d8e6-7583-4ca4-8e50-06f541300334
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673339714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stres
s.673339714
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.2975075916
Short name T200
Test name
Test status
Simulation time 285854605 ps
CPU time 0.9 seconds
Started Jun 10 05:54:10 PM PDT 24
Finished Jun 10 05:54:11 PM PDT 24
Peak memory 196424 kb
Host smart-0c3ff4dd-e00b-420e-b1b8-a670cd89a4ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975075916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.2975075916
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.2291336519
Short name T223
Test name
Test status
Simulation time 26723946 ps
CPU time 0.84 seconds
Started Jun 10 05:54:16 PM PDT 24
Finished Jun 10 05:54:18 PM PDT 24
Peak memory 196276 kb
Host smart-87d47a02-f782-4ae5-81cd-3b9fb48cd0a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291336519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.2291336519
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.3859988634
Short name T380
Test name
Test status
Simulation time 44967494 ps
CPU time 1.87 seconds
Started Jun 10 05:54:09 PM PDT 24
Finished Jun 10 05:54:11 PM PDT 24
Peak memory 197984 kb
Host smart-d7eb0554-aa30-4858-8091-5cf62717b527
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859988634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.3859988634
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.496756557
Short name T401
Test name
Test status
Simulation time 172475287 ps
CPU time 1.43 seconds
Started Jun 10 05:54:19 PM PDT 24
Finished Jun 10 05:54:21 PM PDT 24
Peak memory 195876 kb
Host smart-b1c9f082-dfaf-4a49-b4d1-0503179b8ba8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496756557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger.
496756557
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.2985720502
Short name T19
Test name
Test status
Simulation time 88706653 ps
CPU time 1.05 seconds
Started Jun 10 05:54:04 PM PDT 24
Finished Jun 10 05:54:05 PM PDT 24
Peak memory 196684 kb
Host smart-f0f6c3e8-9e2d-4a07-a03f-8ede11b7ba46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985720502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.2985720502
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.2343192562
Short name T474
Test name
Test status
Simulation time 53356130 ps
CPU time 0.66 seconds
Started Jun 10 05:54:04 PM PDT 24
Finished Jun 10 05:54:05 PM PDT 24
Peak memory 194404 kb
Host smart-f531ca24-e7a9-4b0d-8704-e1d9e32d3bd7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343192562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.2343192562
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.3090795591
Short name T588
Test name
Test status
Simulation time 283666866 ps
CPU time 1.57 seconds
Started Jun 10 05:54:15 PM PDT 24
Finished Jun 10 05:54:17 PM PDT 24
Peak memory 197904 kb
Host smart-3e614bcc-8445-4261-b4de-8802f56eb490
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090795591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.3090795591
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.1702321271
Short name T493
Test name
Test status
Simulation time 117352770 ps
CPU time 1.11 seconds
Started Jun 10 05:54:06 PM PDT 24
Finished Jun 10 05:54:07 PM PDT 24
Peak memory 196444 kb
Host smart-88b1a5c6-3a1a-4ef9-a2f9-d8d125ddb950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702321271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.1702321271
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.1135691814
Short name T486
Test name
Test status
Simulation time 40008101 ps
CPU time 0.84 seconds
Started Jun 10 05:54:03 PM PDT 24
Finished Jun 10 05:54:04 PM PDT 24
Peak memory 195496 kb
Host smart-c0db4421-d23c-439d-9082-3bc940ffb41c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135691814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.1135691814
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.3699977850
Short name T277
Test name
Test status
Simulation time 15558908586 ps
CPU time 114.13 seconds
Started Jun 10 05:54:10 PM PDT 24
Finished Jun 10 05:56:05 PM PDT 24
Peak memory 198240 kb
Host smart-d8028e69-dc98-4409-bfb6-66470185d561
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699977850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.3699977850
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.37457692
Short name T55
Test name
Test status
Simulation time 120879571208 ps
CPU time 974.32 seconds
Started Jun 10 05:54:11 PM PDT 24
Finished Jun 10 06:10:26 PM PDT 24
Peak memory 198340 kb
Host smart-aacbcae6-b3eb-4201-8a23-3f3359407539
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=37457692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.37457692
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.1640556383
Short name T595
Test name
Test status
Simulation time 11679856 ps
CPU time 0.56 seconds
Started Jun 10 05:54:11 PM PDT 24
Finished Jun 10 05:54:12 PM PDT 24
Peak memory 194684 kb
Host smart-120adb25-b2b5-44f1-9e3e-807df41028cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640556383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.1640556383
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.1971434687
Short name T117
Test name
Test status
Simulation time 59987993 ps
CPU time 0.82 seconds
Started Jun 10 05:54:06 PM PDT 24
Finished Jun 10 05:54:08 PM PDT 24
Peak memory 196388 kb
Host smart-2e31de74-d6a9-4573-b484-039e7f1bc5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971434687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.1971434687
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.2251164399
Short name T696
Test name
Test status
Simulation time 159289951 ps
CPU time 7.89 seconds
Started Jun 10 05:54:20 PM PDT 24
Finished Jun 10 05:54:29 PM PDT 24
Peak memory 196984 kb
Host smart-8305ace2-1661-48aa-afad-1231e6916b09
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251164399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.2251164399
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.3667314173
Short name T476
Test name
Test status
Simulation time 114283133 ps
CPU time 0.87 seconds
Started Jun 10 05:54:15 PM PDT 24
Finished Jun 10 05:54:16 PM PDT 24
Peak memory 196740 kb
Host smart-177f5ec4-17f9-44f6-828d-161b36c7541b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667314173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.3667314173
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.3329767561
Short name T341
Test name
Test status
Simulation time 109023524 ps
CPU time 1.4 seconds
Started Jun 10 05:54:13 PM PDT 24
Finished Jun 10 05:54:15 PM PDT 24
Peak memory 197300 kb
Host smart-ef84515a-38e6-4590-a074-8745bedff37c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329767561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.3329767561
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.454441456
Short name T183
Test name
Test status
Simulation time 94923120 ps
CPU time 1.25 seconds
Started Jun 10 05:54:09 PM PDT 24
Finished Jun 10 05:54:10 PM PDT 24
Peak memory 196852 kb
Host smart-e28f01a9-d16d-4b5a-bb79-127c0f86daae
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454441456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.gpio_intr_with_filter_rand_intr_event.454441456
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.396821426
Short name T502
Test name
Test status
Simulation time 512925393 ps
CPU time 2.96 seconds
Started Jun 10 05:54:11 PM PDT 24
Finished Jun 10 05:54:14 PM PDT 24
Peak memory 197428 kb
Host smart-68d7aace-f090-4399-a4e5-9bcfc9a49a4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396821426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger.
396821426
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.1897845058
Short name T477
Test name
Test status
Simulation time 30111476 ps
CPU time 0.79 seconds
Started Jun 10 05:54:17 PM PDT 24
Finished Jun 10 05:54:18 PM PDT 24
Peak memory 196200 kb
Host smart-638d7dbd-f209-46d9-8f33-757a747d2c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897845058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.1897845058
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.2674101011
Short name T304
Test name
Test status
Simulation time 48807352 ps
CPU time 0.97 seconds
Started Jun 10 05:54:10 PM PDT 24
Finished Jun 10 05:54:12 PM PDT 24
Peak memory 196040 kb
Host smart-dd7a038d-0a2f-4a66-afc9-b04a428967e7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674101011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.2674101011
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.356403398
Short name T20
Test name
Test status
Simulation time 667684215 ps
CPU time 5.46 seconds
Started Jun 10 05:54:17 PM PDT 24
Finished Jun 10 05:54:22 PM PDT 24
Peak memory 197952 kb
Host smart-f81ab7e4-dc82-47af-9f18-af1c0b5de12e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356403398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ran
dom_long_reg_writes_reg_reads.356403398
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.1222386433
Short name T232
Test name
Test status
Simulation time 240608641 ps
CPU time 1.24 seconds
Started Jun 10 05:54:19 PM PDT 24
Finished Jun 10 05:54:21 PM PDT 24
Peak memory 198016 kb
Host smart-0485555b-c11d-401c-a787-53a829909e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222386433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.1222386433
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.772121559
Short name T541
Test name
Test status
Simulation time 37152217 ps
CPU time 1.17 seconds
Started Jun 10 05:54:20 PM PDT 24
Finished Jun 10 05:54:21 PM PDT 24
Peak memory 196644 kb
Host smart-7bd48a51-9229-4393-a684-f0fb153b0056
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772121559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.772121559
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.2043341736
Short name T672
Test name
Test status
Simulation time 11081983393 ps
CPU time 156.63 seconds
Started Jun 10 05:54:09 PM PDT 24
Finished Jun 10 05:56:46 PM PDT 24
Peak memory 198304 kb
Host smart-d131ac40-a1df-4fcc-88c7-f2823a119889
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043341736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.2043341736
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.2953816987
Short name T58
Test name
Test status
Simulation time 104250590622 ps
CPU time 1573.72 seconds
Started Jun 10 05:54:08 PM PDT 24
Finished Jun 10 06:20:22 PM PDT 24
Peak memory 198292 kb
Host smart-3c7a22a8-076c-4bdf-b714-9cd397ddf3a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2953816987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.2953816987
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.1406229145
Short name T593
Test name
Test status
Simulation time 134826931 ps
CPU time 0.59 seconds
Started Jun 10 05:54:13 PM PDT 24
Finished Jun 10 05:54:14 PM PDT 24
Peak memory 193920 kb
Host smart-61c4a162-1a45-4f82-bbe1-47d8438d96d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406229145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.1406229145
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.496381439
Short name T434
Test name
Test status
Simulation time 50784452 ps
CPU time 0.71 seconds
Started Jun 10 05:54:15 PM PDT 24
Finished Jun 10 05:54:16 PM PDT 24
Peak memory 194256 kb
Host smart-1c3c5fae-9e59-4df2-9494-a269b9179bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496381439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.496381439
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.3307594702
Short name T458
Test name
Test status
Simulation time 132887273 ps
CPU time 4.38 seconds
Started Jun 10 05:54:10 PM PDT 24
Finished Jun 10 05:54:15 PM PDT 24
Peak memory 196064 kb
Host smart-5d148d9d-4075-4019-aacf-e0fa41b5c5d9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307594702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.3307594702
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.1979756878
Short name T66
Test name
Test status
Simulation time 59502569 ps
CPU time 0.89 seconds
Started Jun 10 05:54:13 PM PDT 24
Finished Jun 10 05:54:14 PM PDT 24
Peak memory 196220 kb
Host smart-cc4b457d-9e71-47d4-998e-97ef3212c6d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979756878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.1979756878
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.1783567574
Short name T685
Test name
Test status
Simulation time 31319238 ps
CPU time 1.04 seconds
Started Jun 10 05:54:11 PM PDT 24
Finished Jun 10 05:54:13 PM PDT 24
Peak memory 196704 kb
Host smart-1b706447-e94e-4255-853c-86f29a4a83b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783567574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.1783567574
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.142931380
Short name T561
Test name
Test status
Simulation time 41346944 ps
CPU time 1.65 seconds
Started Jun 10 05:54:11 PM PDT 24
Finished Jun 10 05:54:13 PM PDT 24
Peak memory 196816 kb
Host smart-fbaaf591-6842-4c76-b46c-69cd82cf990e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142931380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.gpio_intr_with_filter_rand_intr_event.142931380
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.3766332089
Short name T617
Test name
Test status
Simulation time 143509713 ps
CPU time 1.4 seconds
Started Jun 10 05:54:16 PM PDT 24
Finished Jun 10 05:54:18 PM PDT 24
Peak memory 195732 kb
Host smart-fc64a54e-5069-412e-927f-40d31dc35d11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766332089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.3766332089
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.1752073661
Short name T470
Test name
Test status
Simulation time 17569502 ps
CPU time 0.74 seconds
Started Jun 10 05:54:09 PM PDT 24
Finished Jun 10 05:54:10 PM PDT 24
Peak memory 195444 kb
Host smart-bda62e87-542a-4dd7-b2cc-856f4842f077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752073661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.1752073661
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3258661374
Short name T410
Test name
Test status
Simulation time 74426337 ps
CPU time 0.9 seconds
Started Jun 10 05:54:10 PM PDT 24
Finished Jun 10 05:54:11 PM PDT 24
Peak memory 196760 kb
Host smart-28ba10e7-97a8-47f0-8739-f284c9bc619f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258661374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3258661374
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.1267364406
Short name T603
Test name
Test status
Simulation time 553472479 ps
CPU time 2.41 seconds
Started Jun 10 05:54:13 PM PDT 24
Finished Jun 10 05:54:16 PM PDT 24
Peak memory 198024 kb
Host smart-3b1dbfd7-f8b1-4a5b-802a-9e8e1c1c1de2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267364406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.1267364406
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.3066267932
Short name T172
Test name
Test status
Simulation time 91228104 ps
CPU time 1.4 seconds
Started Jun 10 05:54:11 PM PDT 24
Finished Jun 10 05:54:13 PM PDT 24
Peak memory 196804 kb
Host smart-4d341c7c-22eb-4d65-ba45-60631b97acae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066267932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.3066267932
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.2608872107
Short name T417
Test name
Test status
Simulation time 148540609 ps
CPU time 1.28 seconds
Started Jun 10 05:54:06 PM PDT 24
Finished Jun 10 05:54:08 PM PDT 24
Peak memory 195660 kb
Host smart-3d4e577b-6045-41e9-9503-1ee08cdf1470
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608872107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.2608872107
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.721708570
Short name T665
Test name
Test status
Simulation time 17831253649 ps
CPU time 195.6 seconds
Started Jun 10 05:54:07 PM PDT 24
Finished Jun 10 05:57:23 PM PDT 24
Peak memory 198200 kb
Host smart-4fcf1c3c-2707-4860-8846-58b4aa6ad078
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721708570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.g
pio_stress_all.721708570
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.3259945422
Short name T319
Test name
Test status
Simulation time 41426996 ps
CPU time 0.55 seconds
Started Jun 10 05:54:22 PM PDT 24
Finished Jun 10 05:54:22 PM PDT 24
Peak memory 193964 kb
Host smart-8cc3aeeb-256c-4bc9-8fa7-d41a5869e95e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259945422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.3259945422
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.1688821186
Short name T166
Test name
Test status
Simulation time 58675719 ps
CPU time 0.72 seconds
Started Jun 10 05:54:33 PM PDT 24
Finished Jun 10 05:54:35 PM PDT 24
Peak memory 196096 kb
Host smart-60014e70-b85a-42ca-96d8-f010a2ce271f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688821186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.1688821186
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.902610536
Short name T679
Test name
Test status
Simulation time 1531114637 ps
CPU time 12.51 seconds
Started Jun 10 05:54:14 PM PDT 24
Finished Jun 10 05:54:27 PM PDT 24
Peak memory 196976 kb
Host smart-9cff0e6e-777a-429f-8979-9ca60c49f858
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902610536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stres
s.902610536
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.952326542
Short name T351
Test name
Test status
Simulation time 138716311 ps
CPU time 0.69 seconds
Started Jun 10 05:54:15 PM PDT 24
Finished Jun 10 05:54:17 PM PDT 24
Peak memory 194592 kb
Host smart-37f9feec-7a26-4dd3-a77b-8ad0b02c7c9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952326542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.952326542
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.1822320903
Short name T253
Test name
Test status
Simulation time 221533830 ps
CPU time 0.75 seconds
Started Jun 10 05:54:12 PM PDT 24
Finished Jun 10 05:54:13 PM PDT 24
Peak memory 196128 kb
Host smart-3d8c4e7d-fa44-4efe-ae72-414c48f970db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822320903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.1822320903
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.851316699
Short name T591
Test name
Test status
Simulation time 207018678 ps
CPU time 2.19 seconds
Started Jun 10 05:54:21 PM PDT 24
Finished Jun 10 05:54:23 PM PDT 24
Peak memory 198100 kb
Host smart-5e51acbf-64b3-4e28-a321-4697e04f1279
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851316699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.gpio_intr_with_filter_rand_intr_event.851316699
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.1852929138
Short name T597
Test name
Test status
Simulation time 351737747 ps
CPU time 2.05 seconds
Started Jun 10 05:54:16 PM PDT 24
Finished Jun 10 05:54:18 PM PDT 24
Peak memory 196192 kb
Host smart-d668a484-8d92-4d10-a928-331c0dd7322a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852929138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.1852929138
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.2353089179
Short name T616
Test name
Test status
Simulation time 46036648 ps
CPU time 0.87 seconds
Started Jun 10 05:54:22 PM PDT 24
Finished Jun 10 05:54:23 PM PDT 24
Peak memory 195736 kb
Host smart-e03034fd-5285-4498-b71d-7e24202a51a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353089179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.2353089179
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.2422432239
Short name T340
Test name
Test status
Simulation time 149499875 ps
CPU time 0.92 seconds
Started Jun 10 05:54:10 PM PDT 24
Finished Jun 10 05:54:11 PM PDT 24
Peak memory 196580 kb
Host smart-b64116e9-f137-4ef9-9e23-dbac1a77bcc5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422432239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.2422432239
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.296428719
Short name T371
Test name
Test status
Simulation time 2259125804 ps
CPU time 5.88 seconds
Started Jun 10 05:54:11 PM PDT 24
Finished Jun 10 05:54:17 PM PDT 24
Peak memory 198124 kb
Host smart-bd2e6d25-54f4-4eac-8c2a-534a4fcd0cf6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296428719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ran
dom_long_reg_writes_reg_reads.296428719
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.3477212189
Short name T420
Test name
Test status
Simulation time 43922777 ps
CPU time 1.31 seconds
Started Jun 10 05:54:13 PM PDT 24
Finished Jun 10 05:54:15 PM PDT 24
Peak memory 196644 kb
Host smart-37ff10ec-5a40-4528-aa08-1ac97b1db05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477212189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.3477212189
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.341138383
Short name T83
Test name
Test status
Simulation time 128113047 ps
CPU time 1.4 seconds
Started Jun 10 05:54:15 PM PDT 24
Finished Jun 10 05:54:16 PM PDT 24
Peak memory 196980 kb
Host smart-62762654-5ffd-4606-a459-e41e0f9c6f3c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341138383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.341138383
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.2665124235
Short name T640
Test name
Test status
Simulation time 1337593373 ps
CPU time 46.2 seconds
Started Jun 10 05:54:19 PM PDT 24
Finished Jun 10 05:55:06 PM PDT 24
Peak memory 198072 kb
Host smart-9df32257-d7a7-4e0d-980a-767983d4fbfe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665124235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.2665124235
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.2813561185
Short name T318
Test name
Test status
Simulation time 13545993 ps
CPU time 0.58 seconds
Started Jun 10 05:54:27 PM PDT 24
Finished Jun 10 05:54:33 PM PDT 24
Peak memory 195568 kb
Host smart-190b6754-b12b-4241-8bb4-7f3af425356d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813561185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.2813561185
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.233926710
Short name T243
Test name
Test status
Simulation time 66759325 ps
CPU time 0.65 seconds
Started Jun 10 05:54:11 PM PDT 24
Finished Jun 10 05:54:12 PM PDT 24
Peak memory 194064 kb
Host smart-5de887e6-071b-45bb-8fcc-ad8234ffc3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233926710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.233926710
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.1668190300
Short name T676
Test name
Test status
Simulation time 2059347686 ps
CPU time 18.47 seconds
Started Jun 10 05:54:17 PM PDT 24
Finished Jun 10 05:54:36 PM PDT 24
Peak memory 196888 kb
Host smart-51092cf5-ea3f-4fc8-931b-76041fc3f341
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668190300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.1668190300
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.1383819303
Short name T295
Test name
Test status
Simulation time 130709050 ps
CPU time 0.95 seconds
Started Jun 10 05:54:17 PM PDT 24
Finished Jun 10 05:54:18 PM PDT 24
Peak memory 196212 kb
Host smart-f9866715-0524-4aec-aa1e-494433b61d99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383819303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.1383819303
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.476621868
Short name T252
Test name
Test status
Simulation time 45786149 ps
CPU time 1.27 seconds
Started Jun 10 05:54:18 PM PDT 24
Finished Jun 10 05:54:19 PM PDT 24
Peak memory 196288 kb
Host smart-2c89e380-1b36-4fd3-b690-bdfd02972d22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476621868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.476621868
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.1079977151
Short name T684
Test name
Test status
Simulation time 747004440 ps
CPU time 3.77 seconds
Started Jun 10 05:54:16 PM PDT 24
Finished Jun 10 05:54:20 PM PDT 24
Peak memory 198164 kb
Host smart-6808de8a-72bb-4857-ace9-e5e379e0c560
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079977151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.1079977151
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.3990895124
Short name T670
Test name
Test status
Simulation time 157341688 ps
CPU time 2.47 seconds
Started Jun 10 05:54:27 PM PDT 24
Finished Jun 10 05:54:30 PM PDT 24
Peak memory 197332 kb
Host smart-4adecaa8-6d1b-4ea5-a490-970ddf03688e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990895124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.3990895124
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.3495112768
Short name T158
Test name
Test status
Simulation time 121892641 ps
CPU time 1.21 seconds
Started Jun 10 05:54:13 PM PDT 24
Finished Jun 10 05:54:15 PM PDT 24
Peak memory 197028 kb
Host smart-ca5d2075-689d-40cf-8c2c-826958a19658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495112768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.3495112768
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.947809548
Short name T393
Test name
Test status
Simulation time 55690656 ps
CPU time 1.23 seconds
Started Jun 10 05:54:18 PM PDT 24
Finished Jun 10 05:54:20 PM PDT 24
Peak memory 197368 kb
Host smart-0a615463-de94-4c6d-9701-2737ba4073dd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947809548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullup
_pulldown.947809548
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3178150157
Short name T508
Test name
Test status
Simulation time 41562862 ps
CPU time 1.86 seconds
Started Jun 10 05:54:18 PM PDT 24
Finished Jun 10 05:54:20 PM PDT 24
Peak memory 198064 kb
Host smart-440bedf2-8fc3-453f-8063-c2b2621557ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178150157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3178150157
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.2672760712
Short name T720
Test name
Test status
Simulation time 74308753 ps
CPU time 1.51 seconds
Started Jun 10 05:54:13 PM PDT 24
Finished Jun 10 05:54:14 PM PDT 24
Peak memory 195656 kb
Host smart-8cde8a52-556d-42e0-8146-3061d5de476e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672760712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.2672760712
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.3974036386
Short name T660
Test name
Test status
Simulation time 29189327 ps
CPU time 0.78 seconds
Started Jun 10 05:54:12 PM PDT 24
Finished Jun 10 05:54:13 PM PDT 24
Peak memory 195300 kb
Host smart-71ed2176-6016-4096-b7a1-e3fd24a5ba6e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974036386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.3974036386
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.1238766411
Short name T698
Test name
Test status
Simulation time 21566429895 ps
CPU time 206.32 seconds
Started Jun 10 05:54:18 PM PDT 24
Finished Jun 10 05:57:45 PM PDT 24
Peak memory 198184 kb
Host smart-1a59ed9f-05ab-43b4-9fb2-a16bba6cc894
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238766411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.1238766411
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.2229340303
Short name T426
Test name
Test status
Simulation time 240601822403 ps
CPU time 2507.63 seconds
Started Jun 10 05:54:20 PM PDT 24
Finished Jun 10 06:36:08 PM PDT 24
Peak memory 198296 kb
Host smart-f8f00f98-2a81-4493-a3ec-1361b93f35a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2229340303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.2229340303
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.2354169293
Short name T174
Test name
Test status
Simulation time 177654888 ps
CPU time 0.58 seconds
Started Jun 10 05:54:28 PM PDT 24
Finished Jun 10 05:54:29 PM PDT 24
Peak memory 194812 kb
Host smart-d94b5ab9-fb6b-4893-9ff9-943e74c2de77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354169293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.2354169293
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.2988840125
Short name T191
Test name
Test status
Simulation time 157577636 ps
CPU time 0.95 seconds
Started Jun 10 05:54:23 PM PDT 24
Finished Jun 10 05:54:25 PM PDT 24
Peak memory 196028 kb
Host smart-18694f4a-c628-43b0-a9de-c764334b9748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988840125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.2988840125
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.352514185
Short name T222
Test name
Test status
Simulation time 767397242 ps
CPU time 20.88 seconds
Started Jun 10 05:54:33 PM PDT 24
Finished Jun 10 05:54:54 PM PDT 24
Peak memory 196888 kb
Host smart-545e5271-c7be-44ef-b747-519906d87b86
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352514185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stres
s.352514185
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.2141148498
Short name T379
Test name
Test status
Simulation time 115909507 ps
CPU time 0.94 seconds
Started Jun 10 05:54:31 PM PDT 24
Finished Jun 10 05:54:37 PM PDT 24
Peak memory 197916 kb
Host smart-8d42c03d-0955-45a0-ad71-d7b27b935ca1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141148498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.2141148498
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.590144595
Short name T292
Test name
Test status
Simulation time 32345999 ps
CPU time 0.79 seconds
Started Jun 10 05:54:28 PM PDT 24
Finished Jun 10 05:54:29 PM PDT 24
Peak memory 196272 kb
Host smart-adf1e84f-9638-47e1-b1dd-d7191e05ac71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590144595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.590144595
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.2554115767
Short name T50
Test name
Test status
Simulation time 40987429 ps
CPU time 1.29 seconds
Started Jun 10 05:54:17 PM PDT 24
Finished Jun 10 05:54:19 PM PDT 24
Peak memory 196688 kb
Host smart-d61db1f8-65fb-4d3b-af19-8ae35787b538
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554115767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.2554115767
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.124402876
Short name T157
Test name
Test status
Simulation time 169669473 ps
CPU time 3.12 seconds
Started Jun 10 05:54:17 PM PDT 24
Finished Jun 10 05:54:21 PM PDT 24
Peak memory 197424 kb
Host smart-4b2f93dd-5592-4c32-b3f4-500feefce825
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124402876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger.
124402876
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.1047135635
Short name T395
Test name
Test status
Simulation time 203543487 ps
CPU time 1.35 seconds
Started Jun 10 05:54:16 PM PDT 24
Finished Jun 10 05:54:18 PM PDT 24
Peak memory 197068 kb
Host smart-2265acb6-f50a-48d5-b63e-1fb5e756be27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047135635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.1047135635
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.636410483
Short name T337
Test name
Test status
Simulation time 26653282 ps
CPU time 0.72 seconds
Started Jun 10 05:54:15 PM PDT 24
Finished Jun 10 05:54:17 PM PDT 24
Peak memory 195496 kb
Host smart-4e3977cc-56e6-4449-887a-02f1acad1d10
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636410483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullup
_pulldown.636410483
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.3307388812
Short name T577
Test name
Test status
Simulation time 113438067 ps
CPU time 4.83 seconds
Started Jun 10 05:54:18 PM PDT 24
Finished Jun 10 05:54:23 PM PDT 24
Peak memory 197740 kb
Host smart-0eec9989-7510-43b0-8c5b-649cf851764a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307388812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.3307388812
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.940430398
Short name T285
Test name
Test status
Simulation time 24150494 ps
CPU time 0.81 seconds
Started Jun 10 05:54:37 PM PDT 24
Finished Jun 10 05:54:38 PM PDT 24
Peak memory 195996 kb
Host smart-3435ec89-d7f3-4bc4-81e9-dfdc0809e247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940430398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.940430398
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.1042463425
Short name T193
Test name
Test status
Simulation time 99878279 ps
CPU time 0.86 seconds
Started Jun 10 05:54:16 PM PDT 24
Finished Jun 10 05:54:17 PM PDT 24
Peak memory 197280 kb
Host smart-abacfdf6-b9b2-4963-811e-140d44535b37
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042463425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.1042463425
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.3870038749
Short name T362
Test name
Test status
Simulation time 69408671050 ps
CPU time 185.68 seconds
Started Jun 10 05:54:17 PM PDT 24
Finished Jun 10 05:57:23 PM PDT 24
Peak memory 198296 kb
Host smart-b77c676f-7210-42ac-8057-ec177e6576a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870038749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.3870038749
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.3282592690
Short name T54
Test name
Test status
Simulation time 38403956186 ps
CPU time 1046.06 seconds
Started Jun 10 05:54:21 PM PDT 24
Finished Jun 10 06:11:47 PM PDT 24
Peak memory 198316 kb
Host smart-117cf917-8310-48dc-b7e2-bc6a09fb84de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3282592690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.3282592690
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.1285445917
Short name T186
Test name
Test status
Simulation time 22990282 ps
CPU time 0.57 seconds
Started Jun 10 05:54:22 PM PDT 24
Finished Jun 10 05:54:23 PM PDT 24
Peak memory 193944 kb
Host smart-78b26e58-ab42-4f5c-b3e1-48111bd0e9bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285445917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.1285445917
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.1081320513
Short name T495
Test name
Test status
Simulation time 47154337 ps
CPU time 0.65 seconds
Started Jun 10 05:54:26 PM PDT 24
Finished Jun 10 05:54:27 PM PDT 24
Peak memory 194172 kb
Host smart-6343cd7f-4bd9-46a1-aee3-e19ad2262439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081320513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.1081320513
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.2762626573
Short name T651
Test name
Test status
Simulation time 915163149 ps
CPU time 13.21 seconds
Started Jun 10 05:54:19 PM PDT 24
Finished Jun 10 05:54:33 PM PDT 24
Peak memory 196980 kb
Host smart-776432f0-05f2-4304-a223-bbf61460f37d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762626573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.2762626573
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.13052256
Short name T607
Test name
Test status
Simulation time 553248530 ps
CPU time 1.12 seconds
Started Jun 10 05:54:16 PM PDT 24
Finished Jun 10 05:54:18 PM PDT 24
Peak memory 196532 kb
Host smart-4d1a33d6-aeaf-4a2c-b2e6-68ded4d87ec0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13052256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.13052256
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.774404641
Short name T211
Test name
Test status
Simulation time 17690904 ps
CPU time 0.71 seconds
Started Jun 10 05:54:33 PM PDT 24
Finished Jun 10 05:54:35 PM PDT 24
Peak memory 195132 kb
Host smart-0538c196-14d4-4073-856f-1f2d671a27c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774404641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.774404641
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.2651635777
Short name T431
Test name
Test status
Simulation time 86153576 ps
CPU time 1.09 seconds
Started Jun 10 05:54:14 PM PDT 24
Finished Jun 10 05:54:15 PM PDT 24
Peak memory 196920 kb
Host smart-4e7946eb-0c35-4db7-a2ee-1d8e21d6dd20
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651635777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.2651635777
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.4139621986
Short name T584
Test name
Test status
Simulation time 881341132 ps
CPU time 3.14 seconds
Started Jun 10 05:54:38 PM PDT 24
Finished Jun 10 05:54:42 PM PDT 24
Peak memory 197044 kb
Host smart-89b89887-055a-40c5-95f5-c8c38155b944
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139621986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.4139621986
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.762239321
Short name T324
Test name
Test status
Simulation time 19649441 ps
CPU time 0.72 seconds
Started Jun 10 05:54:24 PM PDT 24
Finished Jun 10 05:54:25 PM PDT 24
Peak memory 194472 kb
Host smart-0ece8276-0a20-4d39-9189-f47447c4100f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762239321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.762239321
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.3178845207
Short name T175
Test name
Test status
Simulation time 19851090 ps
CPU time 0.83 seconds
Started Jun 10 05:54:20 PM PDT 24
Finished Jun 10 05:54:21 PM PDT 24
Peak memory 197348 kb
Host smart-e692eb98-1526-4c44-8418-4ab130ef4bb8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178845207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.3178845207
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.1068367114
Short name T317
Test name
Test status
Simulation time 2142749220 ps
CPU time 6.67 seconds
Started Jun 10 05:54:25 PM PDT 24
Finished Jun 10 05:54:32 PM PDT 24
Peak memory 197956 kb
Host smart-6b81a36d-4085-4b26-80a8-dd66b81f3837
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068367114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.1068367114
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.2035623515
Short name T560
Test name
Test status
Simulation time 86597179 ps
CPU time 1.35 seconds
Started Jun 10 05:54:14 PM PDT 24
Finished Jun 10 05:54:16 PM PDT 24
Peak memory 196760 kb
Host smart-ace0a5ac-b80c-4caa-8cd2-a68a22b93485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035623515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.2035623515
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.576418995
Short name T323
Test name
Test status
Simulation time 140537503 ps
CPU time 0.91 seconds
Started Jun 10 05:54:18 PM PDT 24
Finished Jun 10 05:54:19 PM PDT 24
Peak memory 196420 kb
Host smart-d6f0e422-1d1d-4978-980e-75615b902ef4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576418995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.576418995
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.4187517995
Short name T386
Test name
Test status
Simulation time 8454134712 ps
CPU time 234.53 seconds
Started Jun 10 05:54:22 PM PDT 24
Finished Jun 10 05:58:17 PM PDT 24
Peak memory 198248 kb
Host smart-61e2547d-e14a-41c9-9a4c-79ec33c8d080
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187517995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.4187517995
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.2878740158
Short name T578
Test name
Test status
Simulation time 99059077341 ps
CPU time 640.62 seconds
Started Jun 10 05:54:21 PM PDT 24
Finished Jun 10 06:05:07 PM PDT 24
Peak memory 198160 kb
Host smart-3bf99c1a-fc9d-4fe7-ad71-c38e58056d0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2878740158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.2878740158
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.3702676960
Short name T712
Test name
Test status
Simulation time 36598102 ps
CPU time 0.55 seconds
Started Jun 10 05:53:47 PM PDT 24
Finished Jun 10 05:53:48 PM PDT 24
Peak memory 193912 kb
Host smart-4f16a864-73d4-459a-8f26-920c961288cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702676960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.3702676960
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.1775635577
Short name T260
Test name
Test status
Simulation time 17987870 ps
CPU time 0.71 seconds
Started Jun 10 05:53:30 PM PDT 24
Finished Jun 10 05:53:31 PM PDT 24
Peak memory 194112 kb
Host smart-6120227e-fef6-4053-bd23-c7f4ba791a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775635577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.1775635577
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.2182410633
Short name T553
Test name
Test status
Simulation time 351803289 ps
CPU time 20.11 seconds
Started Jun 10 05:53:40 PM PDT 24
Finished Jun 10 05:54:00 PM PDT 24
Peak memory 197048 kb
Host smart-8b78055b-9154-427b-806c-982650376f23
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182410633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.2182410633
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.1339792793
Short name T510
Test name
Test status
Simulation time 72882141 ps
CPU time 0.77 seconds
Started Jun 10 05:53:38 PM PDT 24
Finished Jun 10 05:53:40 PM PDT 24
Peak memory 195916 kb
Host smart-2db58a42-1c85-45a6-95e9-63a53a656072
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339792793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.1339792793
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.4090899803
Short name T178
Test name
Test status
Simulation time 173435118 ps
CPU time 0.89 seconds
Started Jun 10 05:53:33 PM PDT 24
Finished Jun 10 05:53:34 PM PDT 24
Peak memory 196816 kb
Host smart-3bb82ed4-74cd-42de-a615-e4935a20370d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090899803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.4090899803
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.2935760505
Short name T490
Test name
Test status
Simulation time 132946491 ps
CPU time 1.47 seconds
Started Jun 10 05:53:35 PM PDT 24
Finished Jun 10 05:53:37 PM PDT 24
Peak memory 196344 kb
Host smart-fd32cb5f-16fa-435c-91da-cf9803c9b9ad
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935760505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.2935760505
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.3415895250
Short name T314
Test name
Test status
Simulation time 1354494442 ps
CPU time 2.83 seconds
Started Jun 10 05:53:32 PM PDT 24
Finished Jun 10 05:53:36 PM PDT 24
Peak memory 197400 kb
Host smart-c5843aec-392a-4f8c-aa0a-e8305cb1fb0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415895250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
3415895250
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.1617048563
Short name T503
Test name
Test status
Simulation time 77877732 ps
CPU time 0.92 seconds
Started Jun 10 05:53:33 PM PDT 24
Finished Jun 10 05:53:34 PM PDT 24
Peak memory 196004 kb
Host smart-6a3176b9-da1c-4f1c-9b92-c284262d4913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617048563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.1617048563
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.2157537934
Short name T367
Test name
Test status
Simulation time 38288605 ps
CPU time 0.96 seconds
Started Jun 10 05:53:37 PM PDT 24
Finished Jun 10 05:53:38 PM PDT 24
Peak memory 195988 kb
Host smart-7fc4f6d0-d720-42cc-a1c0-31cb713a7db1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157537934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.2157537934
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.3334525271
Short name T703
Test name
Test status
Simulation time 164845812 ps
CPU time 2.12 seconds
Started Jun 10 05:53:41 PM PDT 24
Finished Jun 10 05:53:44 PM PDT 24
Peak memory 198068 kb
Host smart-d7599e78-1176-4a88-9476-c5b1cf56ae2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334525271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.3334525271
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.2713736202
Short name T27
Test name
Test status
Simulation time 472935499 ps
CPU time 1.01 seconds
Started Jun 10 05:53:35 PM PDT 24
Finished Jun 10 05:53:36 PM PDT 24
Peak memory 215020 kb
Host smart-a8cd8d6b-461c-4805-8382-bb094d50016c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713736202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.2713736202
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.3620245526
Short name T201
Test name
Test status
Simulation time 509560289 ps
CPU time 1.23 seconds
Started Jun 10 05:53:37 PM PDT 24
Finished Jun 10 05:53:39 PM PDT 24
Peak memory 196912 kb
Host smart-8743d8d2-8e6d-4e37-b9bd-90d8ad1a149f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620245526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.3620245526
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.1110602035
Short name T196
Test name
Test status
Simulation time 66090718 ps
CPU time 1.18 seconds
Started Jun 10 05:53:37 PM PDT 24
Finished Jun 10 05:53:39 PM PDT 24
Peak memory 196428 kb
Host smart-fafd0a8e-b908-492f-b666-69405471fd8c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110602035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.1110602035
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.1904999059
Short name T445
Test name
Test status
Simulation time 11793595946 ps
CPU time 46.33 seconds
Started Jun 10 05:53:36 PM PDT 24
Finished Jun 10 05:54:23 PM PDT 24
Peak memory 198256 kb
Host smart-87b9ee12-63dc-4636-9aad-b2b66c53b8f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904999059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.1904999059
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.926834892
Short name T601
Test name
Test status
Simulation time 158730255540 ps
CPU time 817.56 seconds
Started Jun 10 05:53:33 PM PDT 24
Finished Jun 10 06:07:11 PM PDT 24
Peak memory 198260 kb
Host smart-a04f522d-4eeb-4909-be78-2d8c0fb4b025
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=926834892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.926834892
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.3873307189
Short name T596
Test name
Test status
Simulation time 99711825 ps
CPU time 0.6 seconds
Started Jun 10 05:54:18 PM PDT 24
Finished Jun 10 05:54:19 PM PDT 24
Peak memory 193992 kb
Host smart-ac14e0b4-e797-45ef-9329-dc2c4c23a279
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873307189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.3873307189
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.2166157743
Short name T207
Test name
Test status
Simulation time 24409455 ps
CPU time 0.86 seconds
Started Jun 10 05:54:23 PM PDT 24
Finished Jun 10 05:54:24 PM PDT 24
Peak memory 195312 kb
Host smart-91ef66d8-4076-411c-a8ce-f33ce438fa53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166157743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.2166157743
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.2378389148
Short name T688
Test name
Test status
Simulation time 534801765 ps
CPU time 12.05 seconds
Started Jun 10 05:54:41 PM PDT 24
Finished Jun 10 05:54:53 PM PDT 24
Peak memory 196984 kb
Host smart-2cbf3eb3-bba2-4383-8626-f19d64fe05b1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378389148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.2378389148
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.1148207246
Short name T176
Test name
Test status
Simulation time 100056928 ps
CPU time 0.67 seconds
Started Jun 10 05:54:32 PM PDT 24
Finished Jun 10 05:54:33 PM PDT 24
Peak memory 194804 kb
Host smart-80f0b945-76a9-419f-aaa4-efc7ca25439c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148207246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.1148207246
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.133887013
Short name T262
Test name
Test status
Simulation time 26254269 ps
CPU time 0.73 seconds
Started Jun 10 05:54:21 PM PDT 24
Finished Jun 10 05:54:22 PM PDT 24
Peak memory 194424 kb
Host smart-d7231f90-f8d0-4cbc-a640-a174c9df1a27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133887013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.133887013
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.4088433719
Short name T336
Test name
Test status
Simulation time 269616670 ps
CPU time 2.56 seconds
Started Jun 10 05:54:37 PM PDT 24
Finished Jun 10 05:54:40 PM PDT 24
Peak memory 196516 kb
Host smart-bdded337-d1aa-4c4e-9e05-be2f6714b617
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088433719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.4088433719
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.3795627471
Short name T398
Test name
Test status
Simulation time 553215067 ps
CPU time 2.95 seconds
Started Jun 10 05:54:15 PM PDT 24
Finished Jun 10 05:54:19 PM PDT 24
Peak memory 198128 kb
Host smart-f675fed4-d391-4683-a8f0-b96fa2f6d209
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795627471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.3795627471
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.3764962831
Short name T600
Test name
Test status
Simulation time 171960074 ps
CPU time 1.25 seconds
Started Jun 10 05:54:21 PM PDT 24
Finished Jun 10 05:54:23 PM PDT 24
Peak memory 195924 kb
Host smart-194bf984-71e6-47b2-babc-c8a40a9520dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764962831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.3764962831
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.1628345118
Short name T440
Test name
Test status
Simulation time 64604262 ps
CPU time 1.26 seconds
Started Jun 10 05:54:22 PM PDT 24
Finished Jun 10 05:54:23 PM PDT 24
Peak memory 198136 kb
Host smart-1babe65c-d267-4084-9fbe-6807d2f2c084
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628345118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.1628345118
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.1769190856
Short name T355
Test name
Test status
Simulation time 528455629 ps
CPU time 2.53 seconds
Started Jun 10 05:54:38 PM PDT 24
Finished Jun 10 05:54:41 PM PDT 24
Peak memory 198048 kb
Host smart-960614cd-9d54-4c59-ad44-c61244922e13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769190856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.1769190856
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.208591512
Short name T664
Test name
Test status
Simulation time 89247597 ps
CPU time 1.38 seconds
Started Jun 10 05:54:23 PM PDT 24
Finished Jun 10 05:54:25 PM PDT 24
Peak memory 195572 kb
Host smart-fe3b57fd-bb16-46ae-9798-47b2273064fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208591512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.208591512
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.4013589075
Short name T112
Test name
Test status
Simulation time 213110270 ps
CPU time 0.96 seconds
Started Jun 10 05:54:25 PM PDT 24
Finished Jun 10 05:54:26 PM PDT 24
Peak memory 196252 kb
Host smart-37a8be93-6986-4b75-adf8-a22e0ebc0773
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013589075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.4013589075
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.1895510106
Short name T402
Test name
Test status
Simulation time 9389132712 ps
CPU time 33.46 seconds
Started Jun 10 05:54:35 PM PDT 24
Finished Jun 10 05:55:09 PM PDT 24
Peak memory 198256 kb
Host smart-9e41b9e1-aece-437e-9294-90cedcdf0aa4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895510106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.1895510106
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.39804794
Short name T693
Test name
Test status
Simulation time 15533851 ps
CPU time 0.58 seconds
Started Jun 10 05:54:22 PM PDT 24
Finished Jun 10 05:54:23 PM PDT 24
Peak memory 194136 kb
Host smart-d18a5377-8bec-4c5f-bb13-319a1bd0a392
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39804794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.39804794
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.1211362050
Short name T449
Test name
Test status
Simulation time 70480405 ps
CPU time 0.82 seconds
Started Jun 10 05:54:22 PM PDT 24
Finished Jun 10 05:54:23 PM PDT 24
Peak memory 195044 kb
Host smart-83a7f2eb-d914-4558-8c4f-a0273194899c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211362050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.1211362050
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.4247197427
Short name T411
Test name
Test status
Simulation time 1430370052 ps
CPU time 23.22 seconds
Started Jun 10 05:54:20 PM PDT 24
Finished Jun 10 05:54:44 PM PDT 24
Peak memory 196900 kb
Host smart-b98bcc6b-d492-43d6-9de3-32c8a8748556
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247197427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.4247197427
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.3448768051
Short name T538
Test name
Test status
Simulation time 58853814 ps
CPU time 1.33 seconds
Started Jun 10 05:54:26 PM PDT 24
Finished Jun 10 05:54:28 PM PDT 24
Peak memory 196860 kb
Host smart-e3da19c5-09f1-4645-805f-f183cd5634c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448768051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.3448768051
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.1866500254
Short name T343
Test name
Test status
Simulation time 573635558 ps
CPU time 3.37 seconds
Started Jun 10 05:54:36 PM PDT 24
Finished Jun 10 05:54:40 PM PDT 24
Peak memory 197960 kb
Host smart-c26b96b8-d828-4a16-af87-86282d46f754
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866500254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.1866500254
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.3714522394
Short name T695
Test name
Test status
Simulation time 72494670 ps
CPU time 2.26 seconds
Started Jun 10 05:54:23 PM PDT 24
Finished Jun 10 05:54:26 PM PDT 24
Peak memory 197148 kb
Host smart-da880bb2-3578-47b3-be5f-dcba912bccb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714522394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.3714522394
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.1038938164
Short name T534
Test name
Test status
Simulation time 119990897 ps
CPU time 0.86 seconds
Started Jun 10 05:54:18 PM PDT 24
Finished Jun 10 05:54:20 PM PDT 24
Peak memory 195808 kb
Host smart-71e0d9b4-a42e-4be8-b31a-be861f2b5f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038938164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.1038938164
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.1885589701
Short name T614
Test name
Test status
Simulation time 38659999 ps
CPU time 1 seconds
Started Jun 10 05:54:29 PM PDT 24
Finished Jun 10 05:54:30 PM PDT 24
Peak memory 195788 kb
Host smart-d28698ef-e6a1-4fc7-9daf-2f12ee98cb49
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885589701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.1885589701
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.522322584
Short name T517
Test name
Test status
Simulation time 300729576 ps
CPU time 2.88 seconds
Started Jun 10 05:54:40 PM PDT 24
Finished Jun 10 05:54:43 PM PDT 24
Peak memory 198060 kb
Host smart-c20c5caa-85b4-437a-9a16-c25cca8f1cf3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522322584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ran
dom_long_reg_writes_reg_reads.522322584
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.919179745
Short name T457
Test name
Test status
Simulation time 30718195 ps
CPU time 0.94 seconds
Started Jun 10 05:54:20 PM PDT 24
Finished Jun 10 05:54:21 PM PDT 24
Peak memory 196364 kb
Host smart-d54c9620-788e-43f3-a88e-4350621a07a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919179745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.919179745
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.1161925148
Short name T219
Test name
Test status
Simulation time 28620025 ps
CPU time 0.94 seconds
Started Jun 10 05:54:40 PM PDT 24
Finished Jun 10 05:54:41 PM PDT 24
Peak memory 197276 kb
Host smart-98251710-2f3e-4bc1-90ff-37ab4185a0c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161925148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.1161925148
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.2795071530
Short name T498
Test name
Test status
Simulation time 2663997727 ps
CPU time 76.73 seconds
Started Jun 10 05:54:30 PM PDT 24
Finished Jun 10 05:55:47 PM PDT 24
Peak memory 198296 kb
Host smart-dca628a1-6bf1-4e8e-b625-f86570d44e99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795071530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.2795071530
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.3758626295
Short name T396
Test name
Test status
Simulation time 67650050051 ps
CPU time 504.69 seconds
Started Jun 10 05:54:17 PM PDT 24
Finished Jun 10 06:02:42 PM PDT 24
Peak memory 198248 kb
Host smart-0c235439-ee8c-4592-9dda-2234a2bbc2fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3758626295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.3758626295
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.2861132517
Short name T32
Test name
Test status
Simulation time 16537442 ps
CPU time 0.57 seconds
Started Jun 10 05:54:35 PM PDT 24
Finished Jun 10 05:54:36 PM PDT 24
Peak memory 193968 kb
Host smart-d824935e-0261-4535-b5b1-1780a7c01db2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861132517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.2861132517
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.4033314251
Short name T416
Test name
Test status
Simulation time 508956467 ps
CPU time 0.89 seconds
Started Jun 10 05:54:41 PM PDT 24
Finished Jun 10 05:54:42 PM PDT 24
Peak memory 196632 kb
Host smart-5c594c24-79a7-446b-acc4-f4652a605155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033314251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.4033314251
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.2546826370
Short name T170
Test name
Test status
Simulation time 832196784 ps
CPU time 10.16 seconds
Started Jun 10 05:54:25 PM PDT 24
Finished Jun 10 05:54:36 PM PDT 24
Peak memory 195668 kb
Host smart-22f836c5-5871-43ee-90fe-5cc2aaa3a74f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546826370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.2546826370
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.1586126506
Short name T668
Test name
Test status
Simulation time 198140868 ps
CPU time 0.86 seconds
Started Jun 10 05:54:39 PM PDT 24
Finished Jun 10 05:54:40 PM PDT 24
Peak memory 197200 kb
Host smart-495b3d54-2bfe-4377-8c33-4e90037cbddc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586126506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.1586126506
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.1094091481
Short name T622
Test name
Test status
Simulation time 207224492 ps
CPU time 1.47 seconds
Started Jun 10 05:54:24 PM PDT 24
Finished Jun 10 05:54:26 PM PDT 24
Peak memory 196588 kb
Host smart-860b172a-e8b6-4c57-838e-050e6223aa67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094091481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.1094091481
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.782708615
Short name T179
Test name
Test status
Simulation time 145119970 ps
CPU time 0.97 seconds
Started Jun 10 05:54:35 PM PDT 24
Finished Jun 10 05:54:37 PM PDT 24
Peak memory 196768 kb
Host smart-0b905822-ec68-49fd-bdc4-3d4bd4ec20c1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782708615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.gpio_intr_with_filter_rand_intr_event.782708615
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.1749596316
Short name T132
Test name
Test status
Simulation time 81393873 ps
CPU time 1.07 seconds
Started Jun 10 05:54:31 PM PDT 24
Finished Jun 10 05:54:33 PM PDT 24
Peak memory 195768 kb
Host smart-bdd6258e-94e3-41b0-ad02-5a7a18afbc05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749596316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.1749596316
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.1956138404
Short name T585
Test name
Test status
Simulation time 122466612 ps
CPU time 0.82 seconds
Started Jun 10 05:54:23 PM PDT 24
Finished Jun 10 05:54:24 PM PDT 24
Peak memory 195584 kb
Host smart-1c8582ae-2d75-483f-9506-c1dc8d40f6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956138404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.1956138404
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.2166396937
Short name T516
Test name
Test status
Simulation time 37802145 ps
CPU time 1.29 seconds
Started Jun 10 05:54:24 PM PDT 24
Finished Jun 10 05:54:25 PM PDT 24
Peak memory 197216 kb
Host smart-a0e3b6b8-4e1f-4d49-90ff-48cef54492ef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166396937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.2166396937
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.847120102
Short name T637
Test name
Test status
Simulation time 212711230 ps
CPU time 5.03 seconds
Started Jun 10 05:54:27 PM PDT 24
Finished Jun 10 05:54:32 PM PDT 24
Peak memory 197928 kb
Host smart-a2a66fa2-7290-4d8b-b71d-08e07a40b871
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847120102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ran
dom_long_reg_writes_reg_reads.847120102
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.1760518963
Short name T115
Test name
Test status
Simulation time 89697189 ps
CPU time 0.97 seconds
Started Jun 10 05:54:37 PM PDT 24
Finished Jun 10 05:54:39 PM PDT 24
Peak memory 197184 kb
Host smart-696b6417-5276-4b43-87d0-6bad08944758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760518963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.1760518963
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.1539610248
Short name T226
Test name
Test status
Simulation time 104943933 ps
CPU time 0.93 seconds
Started Jun 10 05:54:23 PM PDT 24
Finished Jun 10 05:54:24 PM PDT 24
Peak memory 195768 kb
Host smart-40d88123-ecea-4c20-a793-4cc8736ffc03
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539610248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.1539610248
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.753424282
Short name T667
Test name
Test status
Simulation time 24698186401 ps
CPU time 182.37 seconds
Started Jun 10 05:54:26 PM PDT 24
Finished Jun 10 05:57:28 PM PDT 24
Peak memory 198156 kb
Host smart-ce591572-89c2-43c8-a12a-4bdb61618e03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753424282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.g
pio_stress_all.753424282
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.802943244
Short name T505
Test name
Test status
Simulation time 100176128009 ps
CPU time 936.77 seconds
Started Jun 10 05:54:26 PM PDT 24
Finished Jun 10 06:10:03 PM PDT 24
Peak memory 198312 kb
Host smart-aa9b23dd-0cc8-4c22-a396-693b91026a15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=802943244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.802943244
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.1776600345
Short name T708
Test name
Test status
Simulation time 78530982 ps
CPU time 0.59 seconds
Started Jun 10 05:54:32 PM PDT 24
Finished Jun 10 05:54:33 PM PDT 24
Peak memory 193944 kb
Host smart-938273a9-7de3-45c6-9c3c-716acf44598b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776600345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.1776600345
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.2556621345
Short name T64
Test name
Test status
Simulation time 18227692 ps
CPU time 0.67 seconds
Started Jun 10 05:54:30 PM PDT 24
Finished Jun 10 05:54:31 PM PDT 24
Peak memory 194224 kb
Host smart-355b6826-61f5-4272-88bd-3647500b2bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556621345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.2556621345
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.957741288
Short name T334
Test name
Test status
Simulation time 1601256157 ps
CPU time 23.38 seconds
Started Jun 10 05:54:32 PM PDT 24
Finished Jun 10 05:54:56 PM PDT 24
Peak memory 196888 kb
Host smart-d1c9fc77-d3d0-470c-8aee-f6521d23b9e6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957741288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stres
s.957741288
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.2472610416
Short name T702
Test name
Test status
Simulation time 99524479 ps
CPU time 0.86 seconds
Started Jun 10 05:54:33 PM PDT 24
Finished Jun 10 05:54:34 PM PDT 24
Peak memory 196012 kb
Host smart-d54a4dfb-b37f-4874-bb8b-762558fb5cb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472610416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.2472610416
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.3985663637
Short name T271
Test name
Test status
Simulation time 53032296 ps
CPU time 1.35 seconds
Started Jun 10 05:54:25 PM PDT 24
Finished Jun 10 05:54:27 PM PDT 24
Peak memory 196952 kb
Host smart-3d97e360-daf5-4e48-bd26-d6d0419f179d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985663637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.3985663637
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.1750651741
Short name T263
Test name
Test status
Simulation time 76467843 ps
CPU time 1.6 seconds
Started Jun 10 05:54:42 PM PDT 24
Finished Jun 10 05:54:44 PM PDT 24
Peak memory 196636 kb
Host smart-2c8f889f-a152-46ec-81c9-c6ee3291bea4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750651741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.1750651741
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.3830777040
Short name T44
Test name
Test status
Simulation time 330568793 ps
CPU time 2.51 seconds
Started Jun 10 05:54:38 PM PDT 24
Finished Jun 10 05:54:41 PM PDT 24
Peak memory 195840 kb
Host smart-c510a390-658b-4b89-b81b-edd5b1259e56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830777040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.3830777040
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.3587173478
Short name T180
Test name
Test status
Simulation time 303133449 ps
CPU time 0.86 seconds
Started Jun 10 05:54:49 PM PDT 24
Finished Jun 10 05:54:50 PM PDT 24
Peak memory 196508 kb
Host smart-62679f9e-b6fe-47c5-94cc-2e1289108268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587173478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.3587173478
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.2400121254
Short name T484
Test name
Test status
Simulation time 40896315 ps
CPU time 0.94 seconds
Started Jun 10 05:54:24 PM PDT 24
Finished Jun 10 05:54:26 PM PDT 24
Peak memory 196012 kb
Host smart-ddb04bb4-0e21-449b-b67c-e518fa10df7a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400121254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.2400121254
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.98484233
Short name T5
Test name
Test status
Simulation time 1804098638 ps
CPU time 5.29 seconds
Started Jun 10 05:54:27 PM PDT 24
Finished Jun 10 05:54:32 PM PDT 24
Peak memory 198092 kb
Host smart-e6237166-5485-45c6-b479-f6cf5a32f45a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98484233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand
om_long_reg_writes_reg_reads.98484233
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.1892892418
Short name T236
Test name
Test status
Simulation time 88098128 ps
CPU time 0.84 seconds
Started Jun 10 05:54:41 PM PDT 24
Finished Jun 10 05:54:42 PM PDT 24
Peak memory 196512 kb
Host smart-d3d8a442-041c-43c0-87a0-7abf6afa9c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892892418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.1892892418
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.1489936906
Short name T143
Test name
Test status
Simulation time 57895757 ps
CPU time 0.97 seconds
Started Jun 10 05:54:29 PM PDT 24
Finished Jun 10 05:54:30 PM PDT 24
Peak memory 197296 kb
Host smart-ea5c8187-19c4-4e12-97d7-865a91a8e82a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489936906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.1489936906
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.4184002216
Short name T424
Test name
Test status
Simulation time 8514096500 ps
CPU time 116.02 seconds
Started Jun 10 05:54:45 PM PDT 24
Finished Jun 10 05:56:42 PM PDT 24
Peak memory 198120 kb
Host smart-14fed03e-c070-4ce4-8e35-d350898a82a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184002216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.4184002216
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.1288031734
Short name T602
Test name
Test status
Simulation time 27563491611 ps
CPU time 772.24 seconds
Started Jun 10 05:54:31 PM PDT 24
Finished Jun 10 06:07:24 PM PDT 24
Peak memory 198284 kb
Host smart-76845d30-7605-4270-b9a2-6583845290cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1288031734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.1288031734
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.2497248493
Short name T643
Test name
Test status
Simulation time 48203029 ps
CPU time 0.56 seconds
Started Jun 10 05:54:45 PM PDT 24
Finished Jun 10 05:54:46 PM PDT 24
Peak memory 193976 kb
Host smart-ae0f0c62-8198-4663-92e5-447395ac4454
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497248493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.2497248493
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.2286151710
Short name T586
Test name
Test status
Simulation time 28574748 ps
CPU time 0.75 seconds
Started Jun 10 05:54:26 PM PDT 24
Finished Jun 10 05:54:27 PM PDT 24
Peak memory 195000 kb
Host smart-12b8a25b-f0e7-4514-9be1-6786e48b920e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286151710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.2286151710
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.49272116
Short name T80
Test name
Test status
Simulation time 153521725 ps
CPU time 7.09 seconds
Started Jun 10 05:54:50 PM PDT 24
Finished Jun 10 05:54:58 PM PDT 24
Peak memory 198040 kb
Host smart-c7d634a0-fc59-489c-a172-c3c3f4898c41
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49272116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stress
.49272116
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.521633113
Short name T283
Test name
Test status
Simulation time 203869824 ps
CPU time 0.78 seconds
Started Jun 10 05:54:38 PM PDT 24
Finished Jun 10 05:54:39 PM PDT 24
Peak memory 196076 kb
Host smart-5aa25827-c7a5-4e02-a152-39c207478352
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521633113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.521633113
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.1948886279
Short name T215
Test name
Test status
Simulation time 68979370 ps
CPU time 0.88 seconds
Started Jun 10 05:54:33 PM PDT 24
Finished Jun 10 05:54:35 PM PDT 24
Peak memory 195472 kb
Host smart-2294e4b1-50d3-4210-a0a0-cb44109e2333
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948886279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.1948886279
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.2163361712
Short name T310
Test name
Test status
Simulation time 1181752254 ps
CPU time 3.37 seconds
Started Jun 10 05:54:50 PM PDT 24
Finished Jun 10 05:54:54 PM PDT 24
Peak memory 198136 kb
Host smart-9517a29c-b3c6-4d36-a8ad-e215a6fe7bea
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163361712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.2163361712
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.1096555222
Short name T156
Test name
Test status
Simulation time 464552980 ps
CPU time 2.27 seconds
Started Jun 10 05:54:44 PM PDT 24
Finished Jun 10 05:54:47 PM PDT 24
Peak memory 195824 kb
Host smart-50f68b75-1edb-4081-bca3-a89185aa97b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096555222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.1096555222
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.2132160631
Short name T129
Test name
Test status
Simulation time 170557979 ps
CPU time 1.24 seconds
Started Jun 10 05:54:29 PM PDT 24
Finished Jun 10 05:54:30 PM PDT 24
Peak memory 196608 kb
Host smart-4b5dfcf5-549e-4336-a858-5e1feb93a9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132160631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.2132160631
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.2816957519
Short name T427
Test name
Test status
Simulation time 58441022 ps
CPU time 0.71 seconds
Started Jun 10 05:54:48 PM PDT 24
Finished Jun 10 05:54:49 PM PDT 24
Peak memory 195524 kb
Host smart-215ffb03-b274-4dfc-a463-483ed1e44985
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816957519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.2816957519
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.3698502662
Short name T8
Test name
Test status
Simulation time 578848373 ps
CPU time 6.93 seconds
Started Jun 10 05:54:30 PM PDT 24
Finished Jun 10 05:54:37 PM PDT 24
Peak memory 198056 kb
Host smart-0ff79065-4450-44ac-86ca-2f34f5f833e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698502662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.3698502662
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.3960220737
Short name T717
Test name
Test status
Simulation time 67825704 ps
CPU time 1.17 seconds
Started Jun 10 05:54:31 PM PDT 24
Finished Jun 10 05:54:33 PM PDT 24
Peak memory 195752 kb
Host smart-d37779fd-1d61-4e89-ad81-69e43dfbb746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960220737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.3960220737
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.2641503086
Short name T350
Test name
Test status
Simulation time 358403561 ps
CPU time 1.52 seconds
Started Jun 10 05:54:31 PM PDT 24
Finished Jun 10 05:54:33 PM PDT 24
Peak memory 198000 kb
Host smart-410079c5-a5e1-483b-8598-a4b5ea2d024f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641503086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.2641503086
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.2742882436
Short name T390
Test name
Test status
Simulation time 80354140007 ps
CPU time 132.01 seconds
Started Jun 10 05:54:28 PM PDT 24
Finished Jun 10 05:56:40 PM PDT 24
Peak memory 198204 kb
Host smart-95e25b94-42ab-4fe4-bca4-c21eea8570db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742882436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.2742882436
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.728036299
Short name T53
Test name
Test status
Simulation time 65576196786 ps
CPU time 884.41 seconds
Started Jun 10 05:54:28 PM PDT 24
Finished Jun 10 06:09:13 PM PDT 24
Peak memory 198420 kb
Host smart-3d3c9679-5677-4f6f-88c6-dd49794539ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=728036299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.728036299
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.3820719932
Short name T47
Test name
Test status
Simulation time 32827839 ps
CPU time 0.56 seconds
Started Jun 10 05:54:45 PM PDT 24
Finished Jun 10 05:54:47 PM PDT 24
Peak memory 194944 kb
Host smart-14926958-2cd8-4fcf-882a-58adcf000b1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820719932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.3820719932
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.4254094044
Short name T554
Test name
Test status
Simulation time 18415292 ps
CPU time 0.68 seconds
Started Jun 10 05:54:31 PM PDT 24
Finished Jun 10 05:54:32 PM PDT 24
Peak memory 194936 kb
Host smart-12256ae5-aca7-4c58-871b-f39ba528696a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254094044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.4254094044
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.3921576603
Short name T714
Test name
Test status
Simulation time 384191666 ps
CPU time 13.74 seconds
Started Jun 10 05:54:31 PM PDT 24
Finished Jun 10 05:54:45 PM PDT 24
Peak memory 197016 kb
Host smart-1b73e6ec-ea83-4d61-811f-6b697b9567d7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921576603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.3921576603
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.916266862
Short name T197
Test name
Test status
Simulation time 107397936 ps
CPU time 1.06 seconds
Started Jun 10 05:54:46 PM PDT 24
Finished Jun 10 05:54:47 PM PDT 24
Peak memory 197928 kb
Host smart-e7cb617e-d33b-4f62-8e85-16b0869558f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916266862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.916266862
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.2181909989
Short name T266
Test name
Test status
Simulation time 63122978 ps
CPU time 1.17 seconds
Started Jun 10 05:54:30 PM PDT 24
Finished Jun 10 05:54:32 PM PDT 24
Peak memory 196796 kb
Host smart-6ceccab0-51f6-4b54-9d5c-e36270c8d01e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181909989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.2181909989
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.3275730903
Short name T360
Test name
Test status
Simulation time 69143397 ps
CPU time 2.74 seconds
Started Jun 10 05:54:28 PM PDT 24
Finished Jun 10 05:54:31 PM PDT 24
Peak memory 198104 kb
Host smart-7eb97bff-b73b-4e3a-b050-c8d1589062cf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275730903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.3275730903
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.491033684
Short name T138
Test name
Test status
Simulation time 115350376 ps
CPU time 2.28 seconds
Started Jun 10 05:54:31 PM PDT 24
Finished Jun 10 05:54:34 PM PDT 24
Peak memory 195848 kb
Host smart-56065b00-e5ae-4cc8-8cb3-6366122cc277
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491033684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger.
491033684
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.1821496879
Short name T559
Test name
Test status
Simulation time 21168423 ps
CPU time 0.78 seconds
Started Jun 10 05:54:49 PM PDT 24
Finished Jun 10 05:54:50 PM PDT 24
Peak memory 196704 kb
Host smart-b969735e-dda0-43c5-b322-0dc7ff080b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821496879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.1821496879
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.1908291496
Short name T249
Test name
Test status
Simulation time 26572236 ps
CPU time 0.94 seconds
Started Jun 10 05:54:40 PM PDT 24
Finished Jun 10 05:54:42 PM PDT 24
Peak memory 196808 kb
Host smart-e8a887f0-ed04-4aec-9252-e7d795502dd6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908291496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.1908291496
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.2917322029
Short name T428
Test name
Test status
Simulation time 27595472 ps
CPU time 1.15 seconds
Started Jun 10 05:54:30 PM PDT 24
Finished Jun 10 05:54:32 PM PDT 24
Peak memory 198080 kb
Host smart-d5249b05-be63-45d6-ace1-555d10f7085d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917322029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.2917322029
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.2019792195
Short name T248
Test name
Test status
Simulation time 303928209 ps
CPU time 1.29 seconds
Started Jun 10 05:54:29 PM PDT 24
Finished Jun 10 05:54:31 PM PDT 24
Peak memory 196272 kb
Host smart-2b4c6885-b8fb-4307-a68b-34841cf2be79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019792195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.2019792195
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.3973370076
Short name T185
Test name
Test status
Simulation time 53917442 ps
CPU time 1.1 seconds
Started Jun 10 05:54:33 PM PDT 24
Finished Jun 10 05:54:34 PM PDT 24
Peak memory 195776 kb
Host smart-6d19e6c2-ce4d-4457-8797-d17a0ff666a6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973370076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.3973370076
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.1355667844
Short name T293
Test name
Test status
Simulation time 6020632782 ps
CPU time 64.06 seconds
Started Jun 10 05:54:34 PM PDT 24
Finished Jun 10 05:55:38 PM PDT 24
Peak memory 198160 kb
Host smart-c5a86799-d5ec-48ff-a00f-0794be918aaf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355667844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.1355667844
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.1691684760
Short name T376
Test name
Test status
Simulation time 14548660 ps
CPU time 0.58 seconds
Started Jun 10 05:54:37 PM PDT 24
Finished Jun 10 05:54:38 PM PDT 24
Peak memory 194672 kb
Host smart-90c7f3f1-9689-4382-be7c-84c30d1c35e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691684760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.1691684760
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.266149635
Short name T173
Test name
Test status
Simulation time 33609547 ps
CPU time 0.74 seconds
Started Jun 10 05:54:47 PM PDT 24
Finished Jun 10 05:54:48 PM PDT 24
Peak memory 195440 kb
Host smart-b398ba25-70b5-419b-86f7-f426e92fa457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266149635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.266149635
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.893005634
Short name T527
Test name
Test status
Simulation time 117577912 ps
CPU time 6.28 seconds
Started Jun 10 05:54:33 PM PDT 24
Finished Jun 10 05:54:40 PM PDT 24
Peak memory 196988 kb
Host smart-3342e493-415a-408c-83d9-0d934a3dc5af
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893005634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stres
s.893005634
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.3420189681
Short name T491
Test name
Test status
Simulation time 183233727 ps
CPU time 0.76 seconds
Started Jun 10 05:54:32 PM PDT 24
Finished Jun 10 05:54:33 PM PDT 24
Peak memory 196612 kb
Host smart-33978333-ce25-471e-8afa-edec15e63dbe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420189681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.3420189681
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.34818536
Short name T488
Test name
Test status
Simulation time 93566816 ps
CPU time 0.88 seconds
Started Jun 10 05:54:48 PM PDT 24
Finished Jun 10 05:54:50 PM PDT 24
Peak memory 196956 kb
Host smart-dcb3bd3b-99b5-4f59-b56d-359d5d64a179
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34818536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.34818536
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.1052299890
Short name T267
Test name
Test status
Simulation time 139502633 ps
CPU time 2.86 seconds
Started Jun 10 05:54:42 PM PDT 24
Finished Jun 10 05:54:46 PM PDT 24
Peak memory 198112 kb
Host smart-d8af1c02-3b4a-4149-b7c1-ccb67849ce63
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052299890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.1052299890
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.63251804
Short name T82
Test name
Test status
Simulation time 83360735 ps
CPU time 2.45 seconds
Started Jun 10 05:54:39 PM PDT 24
Finished Jun 10 05:54:42 PM PDT 24
Peak memory 196932 kb
Host smart-98b2f1e2-6abe-4bb1-80bb-c47806ad4643
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63251804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger.63251804
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.273908471
Short name T315
Test name
Test status
Simulation time 42406479 ps
CPU time 0.98 seconds
Started Jun 10 05:54:32 PM PDT 24
Finished Jun 10 05:54:33 PM PDT 24
Peak memory 196456 kb
Host smart-d173e4f2-c4f3-490e-9f81-fa0b90202475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273908471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.273908471
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.921006709
Short name T363
Test name
Test status
Simulation time 38936772 ps
CPU time 0.95 seconds
Started Jun 10 05:54:49 PM PDT 24
Finished Jun 10 05:54:51 PM PDT 24
Peak memory 196828 kb
Host smart-ad074893-fa63-4373-98dc-5ea8ec1e5a88
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921006709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullup
_pulldown.921006709
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.1725573736
Short name T567
Test name
Test status
Simulation time 2547288101 ps
CPU time 7.15 seconds
Started Jun 10 05:54:42 PM PDT 24
Finished Jun 10 05:54:50 PM PDT 24
Peak memory 198056 kb
Host smart-9c30954a-67b6-459c-89f3-608eb5d1e73b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725573736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.1725573736
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.2914358242
Short name T189
Test name
Test status
Simulation time 182793184 ps
CPU time 1.22 seconds
Started Jun 10 05:54:31 PM PDT 24
Finished Jun 10 05:54:32 PM PDT 24
Peak memory 196560 kb
Host smart-566d7516-ad2b-4299-acfc-ff80f19e3bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914358242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.2914358242
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.4010627151
Short name T192
Test name
Test status
Simulation time 52453018 ps
CPU time 1.14 seconds
Started Jun 10 05:54:36 PM PDT 24
Finished Jun 10 05:54:37 PM PDT 24
Peak memory 195804 kb
Host smart-ed71d83e-e358-4103-894d-e1d223c52325
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010627151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.4010627151
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.3514478276
Short name T338
Test name
Test status
Simulation time 31725786678 ps
CPU time 207.44 seconds
Started Jun 10 05:54:44 PM PDT 24
Finished Jun 10 05:58:12 PM PDT 24
Peak memory 198192 kb
Host smart-83c04178-2701-478e-9f52-7b3a9050dca1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514478276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.3514478276
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.568587859
Short name T635
Test name
Test status
Simulation time 17354770 ps
CPU time 0.59 seconds
Started Jun 10 05:54:49 PM PDT 24
Finished Jun 10 05:54:50 PM PDT 24
Peak memory 194560 kb
Host smart-dff31f70-96d4-478b-b430-69740a62c57c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568587859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.568587859
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.4037414604
Short name T547
Test name
Test status
Simulation time 32525193 ps
CPU time 0.81 seconds
Started Jun 10 05:54:37 PM PDT 24
Finished Jun 10 05:54:38 PM PDT 24
Peak memory 195384 kb
Host smart-f5a93c49-aae9-45c7-8ea9-819ba5089600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037414604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.4037414604
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.1007998259
Short name T369
Test name
Test status
Simulation time 671702646 ps
CPU time 16.64 seconds
Started Jun 10 05:54:44 PM PDT 24
Finished Jun 10 05:55:01 PM PDT 24
Peak memory 196748 kb
Host smart-751e0cef-ff05-4ea1-b2d8-bed4bbad365f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007998259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.1007998259
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.3409486511
Short name T113
Test name
Test status
Simulation time 135840843 ps
CPU time 0.94 seconds
Started Jun 10 05:54:39 PM PDT 24
Finished Jun 10 05:54:40 PM PDT 24
Peak memory 197284 kb
Host smart-ffdc630e-5466-4e89-90a6-f2d58b71b847
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409486511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.3409486511
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.297386177
Short name T564
Test name
Test status
Simulation time 256859014 ps
CPU time 1.4 seconds
Started Jun 10 05:54:53 PM PDT 24
Finished Jun 10 05:54:56 PM PDT 24
Peak memory 197024 kb
Host smart-c70a24ff-0d38-4319-981a-bb0338c58f5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297386177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.297386177
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.1494807070
Short name T621
Test name
Test status
Simulation time 373489288 ps
CPU time 3.68 seconds
Started Jun 10 05:54:50 PM PDT 24
Finished Jun 10 05:54:54 PM PDT 24
Peak memory 198088 kb
Host smart-d000bb8f-7f8c-4505-8b3b-1b4f1ac45190
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494807070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.1494807070
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.1963328450
Short name T533
Test name
Test status
Simulation time 379876770 ps
CPU time 2.82 seconds
Started Jun 10 05:54:50 PM PDT 24
Finished Jun 10 05:54:54 PM PDT 24
Peak memory 197012 kb
Host smart-d5fcfabd-5b9a-417e-b2d5-8a89d9c89092
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963328450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.1963328450
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.2172447848
Short name T375
Test name
Test status
Simulation time 100169405 ps
CPU time 1.31 seconds
Started Jun 10 05:54:46 PM PDT 24
Finished Jun 10 05:54:48 PM PDT 24
Peak memory 197092 kb
Host smart-db9b37f3-9681-42dc-a7d9-835f615a6a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172447848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.2172447848
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.3482880162
Short name T691
Test name
Test status
Simulation time 457278286 ps
CPU time 1.28 seconds
Started Jun 10 05:54:52 PM PDT 24
Finished Jun 10 05:54:54 PM PDT 24
Peak memory 197004 kb
Host smart-91b3b5b7-87ba-4c13-88e6-c4e49c738908
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482880162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.3482880162
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.130307144
Short name T111
Test name
Test status
Simulation time 44105556 ps
CPU time 1.58 seconds
Started Jun 10 05:54:48 PM PDT 24
Finished Jun 10 05:54:50 PM PDT 24
Peak memory 197892 kb
Host smart-f51af0d8-bbb3-4eeb-8a22-1f1eb0c33221
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130307144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ran
dom_long_reg_writes_reg_reads.130307144
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.2854515388
Short name T425
Test name
Test status
Simulation time 37121240 ps
CPU time 0.79 seconds
Started Jun 10 05:54:44 PM PDT 24
Finished Jun 10 05:54:45 PM PDT 24
Peak memory 195344 kb
Host smart-b3e8b21d-dab9-40f7-935d-aebdd690488e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854515388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.2854515388
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.2576240102
Short name T251
Test name
Test status
Simulation time 218623175 ps
CPU time 1.15 seconds
Started Jun 10 05:54:39 PM PDT 24
Finished Jun 10 05:54:40 PM PDT 24
Peak memory 195752 kb
Host smart-c948c615-ea27-468c-9251-d8a26c7d937e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576240102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.2576240102
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.678174750
Short name T569
Test name
Test status
Simulation time 133317230467 ps
CPU time 169.96 seconds
Started Jun 10 05:54:34 PM PDT 24
Finished Jun 10 05:57:25 PM PDT 24
Peak memory 198240 kb
Host smart-3874457f-b2c9-4558-a8cb-ae37cb9c953f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678174750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.g
pio_stress_all.678174750
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.2274243399
Short name T281
Test name
Test status
Simulation time 40985519 ps
CPU time 0.61 seconds
Started Jun 10 05:54:52 PM PDT 24
Finished Jun 10 05:54:53 PM PDT 24
Peak memory 192848 kb
Host smart-d6a3432d-5ad7-4fb8-9b20-74c5074c0d1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274243399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.2274243399
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.2601926634
Short name T636
Test name
Test status
Simulation time 17561622 ps
CPU time 0.63 seconds
Started Jun 10 05:54:45 PM PDT 24
Finished Jun 10 05:54:46 PM PDT 24
Peak memory 194140 kb
Host smart-acbf76ad-873a-48fe-8659-fcb7c13c5434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601926634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.2601926634
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.693933355
Short name T133
Test name
Test status
Simulation time 3987779048 ps
CPU time 24.71 seconds
Started Jun 10 05:54:38 PM PDT 24
Finished Jun 10 05:55:04 PM PDT 24
Peak memory 196740 kb
Host smart-40c422ad-3db5-4eef-a9bc-84cca4ab8a02
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693933355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stres
s.693933355
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.3669324519
Short name T17
Test name
Test status
Simulation time 180725332 ps
CPU time 0.76 seconds
Started Jun 10 05:54:37 PM PDT 24
Finished Jun 10 05:54:39 PM PDT 24
Peak memory 196028 kb
Host smart-d9a647ea-6620-414f-9211-dc0bfa1dd651
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669324519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.3669324519
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.3698377414
Short name T79
Test name
Test status
Simulation time 249791369 ps
CPU time 1.11 seconds
Started Jun 10 05:54:39 PM PDT 24
Finished Jun 10 05:54:40 PM PDT 24
Peak memory 196164 kb
Host smart-294865ca-3447-475f-bfa1-d2bf5f7cd5ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698377414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.3698377414
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.3158491362
Short name T694
Test name
Test status
Simulation time 44041903 ps
CPU time 1.9 seconds
Started Jun 10 05:54:42 PM PDT 24
Finished Jun 10 05:54:44 PM PDT 24
Peak memory 198032 kb
Host smart-d2a9a522-6719-4c5b-9abe-fb82b00eb9f7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158491362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.3158491362
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.2733766047
Short name T385
Test name
Test status
Simulation time 278666556 ps
CPU time 2.88 seconds
Started Jun 10 05:54:50 PM PDT 24
Finished Jun 10 05:54:54 PM PDT 24
Peak memory 197484 kb
Host smart-470f04f1-8dc1-44d9-969c-4b05a7bb5cbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733766047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.2733766047
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.736111638
Short name T582
Test name
Test status
Simulation time 107468920 ps
CPU time 1 seconds
Started Jun 10 05:54:51 PM PDT 24
Finished Jun 10 05:54:53 PM PDT 24
Peak memory 196832 kb
Host smart-c4131b34-05ad-49f4-aabf-0c423e2a161c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736111638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.736111638
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.2655569908
Short name T282
Test name
Test status
Simulation time 106941732 ps
CPU time 1.33 seconds
Started Jun 10 05:54:49 PM PDT 24
Finished Jun 10 05:54:51 PM PDT 24
Peak memory 195872 kb
Host smart-4dbd908f-dc6d-425a-b609-98a083054e8b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655569908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.2655569908
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.511014640
Short name T504
Test name
Test status
Simulation time 551316177 ps
CPU time 1.96 seconds
Started Jun 10 05:54:41 PM PDT 24
Finished Jun 10 05:54:43 PM PDT 24
Peak memory 198060 kb
Host smart-f4c3b147-881e-4781-b6b1-421e550d3dec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511014640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ran
dom_long_reg_writes_reg_reads.511014640
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.3094514904
Short name T181
Test name
Test status
Simulation time 32113344 ps
CPU time 1.06 seconds
Started Jun 10 05:54:50 PM PDT 24
Finished Jun 10 05:54:52 PM PDT 24
Peak memory 195672 kb
Host smart-1510eede-8801-436c-ae8c-5a4ef3ca8501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094514904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.3094514904
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.3405890624
Short name T675
Test name
Test status
Simulation time 108504715 ps
CPU time 1.33 seconds
Started Jun 10 05:54:45 PM PDT 24
Finished Jun 10 05:54:46 PM PDT 24
Peak memory 196728 kb
Host smart-bd47614c-26aa-4bf5-9144-ee12dd4e626a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405890624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.3405890624
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.3210798847
Short name T483
Test name
Test status
Simulation time 61071871776 ps
CPU time 168.1 seconds
Started Jun 10 05:54:38 PM PDT 24
Finished Jun 10 05:57:27 PM PDT 24
Peak memory 198208 kb
Host smart-a979969f-c2bb-4fbf-b8cf-f1bd62d6fa38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210798847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.3210798847
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.2223162304
Short name T342
Test name
Test status
Simulation time 24943685 ps
CPU time 0.57 seconds
Started Jun 10 05:54:53 PM PDT 24
Finished Jun 10 05:54:54 PM PDT 24
Peak memory 193972 kb
Host smart-d812ded2-5a65-4697-9e77-eb741eb225b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223162304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.2223162304
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.2104584497
Short name T288
Test name
Test status
Simulation time 95394490 ps
CPU time 0.61 seconds
Started Jun 10 05:54:53 PM PDT 24
Finished Jun 10 05:54:55 PM PDT 24
Peak memory 194152 kb
Host smart-d4a40a7e-6556-40a2-8367-3f4b38f8393d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104584497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.2104584497
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.2984418571
Short name T403
Test name
Test status
Simulation time 674102599 ps
CPU time 22.68 seconds
Started Jun 10 05:54:49 PM PDT 24
Finished Jun 10 05:55:13 PM PDT 24
Peak memory 195676 kb
Host smart-411d47c9-c212-4edf-a34f-5a3a6ff39384
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984418571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.2984418571
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.3942910582
Short name T642
Test name
Test status
Simulation time 189184808 ps
CPU time 0.85 seconds
Started Jun 10 05:54:47 PM PDT 24
Finished Jun 10 05:54:49 PM PDT 24
Peak memory 197808 kb
Host smart-c2d4fd5d-270f-42b8-b0a6-f21d04fe7ab4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942910582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.3942910582
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.1476607485
Short name T620
Test name
Test status
Simulation time 358621008 ps
CPU time 1.62 seconds
Started Jun 10 05:54:51 PM PDT 24
Finished Jun 10 05:54:54 PM PDT 24
Peak memory 197264 kb
Host smart-b80b0899-84af-4355-9eec-df08280fafa8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476607485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.1476607485
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.1865366714
Short name T137
Test name
Test status
Simulation time 84847724 ps
CPU time 3.36 seconds
Started Jun 10 05:54:41 PM PDT 24
Finished Jun 10 05:54:45 PM PDT 24
Peak memory 198104 kb
Host smart-4c49f4a3-05ef-4674-9211-18343f907e30
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865366714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.1865366714
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.2625047541
Short name T680
Test name
Test status
Simulation time 231961837 ps
CPU time 1.5 seconds
Started Jun 10 05:54:52 PM PDT 24
Finished Jun 10 05:54:54 PM PDT 24
Peak memory 196184 kb
Host smart-64776696-7882-4b9c-b5ec-e814e16453d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625047541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.2625047541
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.914995716
Short name T418
Test name
Test status
Simulation time 87945310 ps
CPU time 0.69 seconds
Started Jun 10 05:54:39 PM PDT 24
Finished Jun 10 05:54:40 PM PDT 24
Peak memory 195504 kb
Host smart-e0dc718f-86b8-4d3f-87d8-3b72dce9c069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914995716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.914995716
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.2199589755
Short name T81
Test name
Test status
Simulation time 58481705 ps
CPU time 1.41 seconds
Started Jun 10 05:54:51 PM PDT 24
Finished Jun 10 05:54:54 PM PDT 24
Peak memory 195908 kb
Host smart-5c6a7a7a-0e3a-406f-8382-064e8f207cb1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199589755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.2199589755
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.2902703190
Short name T543
Test name
Test status
Simulation time 466273009 ps
CPU time 1.99 seconds
Started Jun 10 05:54:38 PM PDT 24
Finished Jun 10 05:54:40 PM PDT 24
Peak memory 198036 kb
Host smart-8f3d54ae-9499-40d2-a40a-ef80ce2987db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902703190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.2902703190
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.707829901
Short name T67
Test name
Test status
Simulation time 264714646 ps
CPU time 1.41 seconds
Started Jun 10 05:54:50 PM PDT 24
Finished Jun 10 05:54:53 PM PDT 24
Peak memory 196748 kb
Host smart-6db18509-1ad2-4e6e-b61d-80428e466a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707829901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.707829901
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.1803264692
Short name T359
Test name
Test status
Simulation time 365580792 ps
CPU time 1.12 seconds
Started Jun 10 05:54:41 PM PDT 24
Finished Jun 10 05:54:43 PM PDT 24
Peak memory 196476 kb
Host smart-e5054e9a-507c-4da7-b719-c6dbf4953034
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803264692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.1803264692
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.1117042905
Short name T627
Test name
Test status
Simulation time 14698970561 ps
CPU time 214.6 seconds
Started Jun 10 05:54:48 PM PDT 24
Finished Jun 10 05:58:23 PM PDT 24
Peak memory 198160 kb
Host smart-263c7041-ecbf-4bac-bac3-28f3e2ef7693
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117042905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.1117042905
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.3757605880
Short name T423
Test name
Test status
Simulation time 25386489 ps
CPU time 0.58 seconds
Started Jun 10 05:53:40 PM PDT 24
Finished Jun 10 05:53:41 PM PDT 24
Peak memory 194852 kb
Host smart-1a250e97-a800-4cff-9f6c-5972e60dca62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757605880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.3757605880
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.2641282351
Short name T247
Test name
Test status
Simulation time 25572516 ps
CPU time 0.67 seconds
Started Jun 10 05:53:34 PM PDT 24
Finished Jun 10 05:53:35 PM PDT 24
Peak memory 194248 kb
Host smart-30db5c7a-37ec-4c96-80be-680162404fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641282351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.2641282351
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.3439187307
Short name T436
Test name
Test status
Simulation time 4530313561 ps
CPU time 18.57 seconds
Started Jun 10 05:53:43 PM PDT 24
Finished Jun 10 05:54:02 PM PDT 24
Peak memory 196848 kb
Host smart-9bdd436f-f824-4249-a0b1-983b2c0f8838
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439187307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.3439187307
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.2854260662
Short name T496
Test name
Test status
Simulation time 284928291 ps
CPU time 0.96 seconds
Started Jun 10 05:53:41 PM PDT 24
Finished Jun 10 05:53:43 PM PDT 24
Peak memory 196676 kb
Host smart-3ebff622-2322-406c-89cc-88f11126e1dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854260662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.2854260662
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.517829130
Short name T722
Test name
Test status
Simulation time 128888696 ps
CPU time 1.02 seconds
Started Jun 10 05:53:38 PM PDT 24
Finished Jun 10 05:53:40 PM PDT 24
Peak memory 196104 kb
Host smart-25e64692-4887-453d-82f4-3ba2d0f73d86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517829130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.517829130
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.3393373808
Short name T299
Test name
Test status
Simulation time 41973572 ps
CPU time 1.11 seconds
Started Jun 10 05:53:39 PM PDT 24
Finished Jun 10 05:53:40 PM PDT 24
Peak memory 197496 kb
Host smart-e88bc547-fef2-4ea9-a1bb-fe5faf6f7106
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393373808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.3393373808
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.4076023192
Short name T509
Test name
Test status
Simulation time 211457265 ps
CPU time 3.03 seconds
Started Jun 10 05:53:43 PM PDT 24
Finished Jun 10 05:53:47 PM PDT 24
Peak memory 196804 kb
Host smart-507d8745-9d64-4a62-b4ee-8a4bd4fa3e2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076023192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
4076023192
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.4054928381
Short name T291
Test name
Test status
Simulation time 41434455 ps
CPU time 0.84 seconds
Started Jun 10 05:53:39 PM PDT 24
Finished Jun 10 05:53:40 PM PDT 24
Peak memory 196636 kb
Host smart-8a5206d7-699d-4547-a332-22e0ee6ad9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054928381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.4054928381
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.83096662
Short name T209
Test name
Test status
Simulation time 22821510 ps
CPU time 0.93 seconds
Started Jun 10 05:53:37 PM PDT 24
Finished Jun 10 05:53:39 PM PDT 24
Peak memory 196148 kb
Host smart-966ab9e3-c986-4a34-a992-e56ae7413c95
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83096662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup_p
ulldown.83096662
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.4081736804
Short name T548
Test name
Test status
Simulation time 613832612 ps
CPU time 4.94 seconds
Started Jun 10 05:53:40 PM PDT 24
Finished Jun 10 05:53:45 PM PDT 24
Peak memory 198040 kb
Host smart-d469d23e-83aa-4653-a738-ca6580e2d1bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081736804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.4081736804
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.852112074
Short name T42
Test name
Test status
Simulation time 679300886 ps
CPU time 1.04 seconds
Started Jun 10 05:53:42 PM PDT 24
Finished Jun 10 05:53:43 PM PDT 24
Peak memory 215132 kb
Host smart-59afffc4-267e-4e2a-8e3b-3cefd93ba28e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852112074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.852112074
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.3874404234
Short name T557
Test name
Test status
Simulation time 212737691 ps
CPU time 1 seconds
Started Jun 10 05:53:36 PM PDT 24
Finished Jun 10 05:53:38 PM PDT 24
Peak memory 195608 kb
Host smart-ae7defd7-10ce-4d45-8c83-f7d65a1b53ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874404234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.3874404234
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.297358245
Short name T523
Test name
Test status
Simulation time 198657910 ps
CPU time 1.1 seconds
Started Jun 10 05:53:42 PM PDT 24
Finished Jun 10 05:53:43 PM PDT 24
Peak memory 196568 kb
Host smart-96beea8a-5eb2-4ba5-b766-d33050dfa7a7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297358245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.297358245
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.3270352519
Short name T413
Test name
Test status
Simulation time 5400827516 ps
CPU time 142.16 seconds
Started Jun 10 05:54:01 PM PDT 24
Finished Jun 10 05:56:23 PM PDT 24
Peak memory 198176 kb
Host smart-ad463187-a60b-461a-9ac5-c2ba4e2fbe10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270352519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.3270352519
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.2175700524
Short name T69
Test name
Test status
Simulation time 90919583138 ps
CPU time 1898.91 seconds
Started Jun 10 05:53:37 PM PDT 24
Finished Jun 10 06:25:17 PM PDT 24
Peak memory 198252 kb
Host smart-d9efa3c0-1551-4495-a05e-4592c2db6cba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2175700524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.2175700524
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.3716715683
Short name T397
Test name
Test status
Simulation time 13510025 ps
CPU time 0.57 seconds
Started Jun 10 05:54:50 PM PDT 24
Finished Jun 10 05:54:52 PM PDT 24
Peak memory 192832 kb
Host smart-aaefcb97-65fb-4754-a6d2-40498e25e948
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716715683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.3716715683
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.172608310
Short name T139
Test name
Test status
Simulation time 22896310 ps
CPU time 0.79 seconds
Started Jun 10 05:54:42 PM PDT 24
Finished Jun 10 05:54:44 PM PDT 24
Peak memory 195388 kb
Host smart-0c0adc05-b184-49e8-ae29-3b3ce7394d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172608310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.172608310
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.3384861462
Short name T333
Test name
Test status
Simulation time 429090223 ps
CPU time 22.06 seconds
Started Jun 10 05:54:51 PM PDT 24
Finished Jun 10 05:55:14 PM PDT 24
Peak memory 196944 kb
Host smart-0b501280-d48f-4e03-8675-b1153c908baf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384861462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.3384861462
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.708015308
Short name T494
Test name
Test status
Simulation time 56207703 ps
CPU time 0.79 seconds
Started Jun 10 05:54:44 PM PDT 24
Finished Jun 10 05:54:45 PM PDT 24
Peak memory 196668 kb
Host smart-d2d935c1-ad89-4f8f-be83-c034ca7f3d85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708015308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.708015308
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.4244823665
Short name T128
Test name
Test status
Simulation time 311222005 ps
CPU time 1.32 seconds
Started Jun 10 05:54:45 PM PDT 24
Finished Jun 10 05:54:46 PM PDT 24
Peak memory 195796 kb
Host smart-517c2f60-d783-4f50-a35d-9ce61a94d515
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244823665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.4244823665
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.1346461517
Short name T604
Test name
Test status
Simulation time 120041868 ps
CPU time 3.7 seconds
Started Jun 10 05:54:47 PM PDT 24
Finished Jun 10 05:54:51 PM PDT 24
Peak memory 198020 kb
Host smart-e0331787-e4f2-47b4-8e8c-ad2b8052ca2f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346461517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.1346461517
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.2925067777
Short name T278
Test name
Test status
Simulation time 460731655 ps
CPU time 1.26 seconds
Started Jun 10 05:54:53 PM PDT 24
Finished Jun 10 05:54:55 PM PDT 24
Peak memory 196960 kb
Host smart-50671b15-5bde-4f3b-bd48-fcec82abde31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925067777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.2925067777
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.3484866332
Short name T481
Test name
Test status
Simulation time 81626871 ps
CPU time 1.3 seconds
Started Jun 10 05:54:43 PM PDT 24
Finished Jun 10 05:54:44 PM PDT 24
Peak memory 195864 kb
Host smart-2b25d075-bac3-42d9-b2b7-ad02d16e8216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484866332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.3484866332
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.3267001556
Short name T284
Test name
Test status
Simulation time 120006351 ps
CPU time 1.33 seconds
Started Jun 10 05:54:52 PM PDT 24
Finished Jun 10 05:54:54 PM PDT 24
Peak memory 198068 kb
Host smart-04f0c177-5808-4faf-8295-f2fef608b784
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267001556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.3267001556
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.2781883112
Short name T10
Test name
Test status
Simulation time 293616079 ps
CPU time 3.09 seconds
Started Jun 10 05:54:51 PM PDT 24
Finished Jun 10 05:54:55 PM PDT 24
Peak memory 197948 kb
Host smart-f5d337b3-1d48-46b1-a32c-c5ea46387fda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781883112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.2781883112
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.3024229075
Short name T265
Test name
Test status
Simulation time 170867737 ps
CPU time 1.32 seconds
Started Jun 10 05:54:51 PM PDT 24
Finished Jun 10 05:54:53 PM PDT 24
Peak memory 196864 kb
Host smart-269af5d1-446f-426a-820e-7a9979f52485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024229075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.3024229075
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.437066512
Short name T194
Test name
Test status
Simulation time 117128760 ps
CPU time 1.24 seconds
Started Jun 10 05:54:49 PM PDT 24
Finished Jun 10 05:54:50 PM PDT 24
Peak memory 196816 kb
Host smart-bfb58e35-5236-4319-9978-55b46418084e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437066512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.437066512
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.1375714449
Short name T647
Test name
Test status
Simulation time 12579915374 ps
CPU time 161.35 seconds
Started Jun 10 05:54:50 PM PDT 24
Finished Jun 10 05:57:33 PM PDT 24
Peak memory 198248 kb
Host smart-f94f5284-02f9-4246-8cb6-ac725ada4094
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375714449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.1375714449
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.5524037
Short name T565
Test name
Test status
Simulation time 51654102 ps
CPU time 0.55 seconds
Started Jun 10 05:54:52 PM PDT 24
Finished Jun 10 05:54:53 PM PDT 24
Peak memory 194604 kb
Host smart-391f5549-a9bb-4322-831c-aa880a1d36d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5524037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.5524037
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.3124685003
Short name T482
Test name
Test status
Simulation time 187697034 ps
CPU time 0.87 seconds
Started Jun 10 05:54:47 PM PDT 24
Finished Jun 10 05:54:48 PM PDT 24
Peak memory 196520 kb
Host smart-f289c8ba-95ab-4e04-88bc-541c50859a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124685003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.3124685003
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.702123860
Short name T177
Test name
Test status
Simulation time 2516051718 ps
CPU time 24.51 seconds
Started Jun 10 05:54:50 PM PDT 24
Finished Jun 10 05:55:15 PM PDT 24
Peak memory 197068 kb
Host smart-f24b76c3-ad96-4649-a6c6-3f104485c5cd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702123860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stres
s.702123860
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.1676156595
Short name T704
Test name
Test status
Simulation time 87575197 ps
CPU time 0.98 seconds
Started Jun 10 05:54:57 PM PDT 24
Finished Jun 10 05:54:58 PM PDT 24
Peak memory 197036 kb
Host smart-209d1c25-d7ad-4666-a880-68efd5ba7d05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676156595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.1676156595
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.969782511
Short name T609
Test name
Test status
Simulation time 315400895 ps
CPU time 1.34 seconds
Started Jun 10 05:54:49 PM PDT 24
Finished Jun 10 05:54:51 PM PDT 24
Peak memory 195888 kb
Host smart-3e7c06ac-7957-442b-bb20-0e1333d9a449
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969782511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.969782511
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.1929285189
Short name T256
Test name
Test status
Simulation time 91392578 ps
CPU time 2 seconds
Started Jun 10 05:54:45 PM PDT 24
Finished Jun 10 05:54:47 PM PDT 24
Peak memory 198164 kb
Host smart-9ba1a8c3-cf93-4ed1-87f1-fa3ffd3f33ac
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929285189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.1929285189
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.2500534089
Short name T255
Test name
Test status
Simulation time 194405300 ps
CPU time 1.58 seconds
Started Jun 10 05:54:49 PM PDT 24
Finished Jun 10 05:54:51 PM PDT 24
Peak memory 196164 kb
Host smart-a71c513b-cd4e-48de-a408-70ee0992d6cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500534089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.2500534089
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.3224474657
Short name T373
Test name
Test status
Simulation time 29437231 ps
CPU time 1.13 seconds
Started Jun 10 05:54:44 PM PDT 24
Finished Jun 10 05:54:45 PM PDT 24
Peak memory 196140 kb
Host smart-5a29ac6f-ee6f-4254-a71a-4de4e2e71f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224474657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.3224474657
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.2803017183
Short name T237
Test name
Test status
Simulation time 23097826 ps
CPU time 0.83 seconds
Started Jun 10 05:54:45 PM PDT 24
Finished Jun 10 05:54:46 PM PDT 24
Peak memory 197404 kb
Host smart-115728d9-c9f3-451f-8674-03a4dd503979
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803017183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.2803017183
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.1466996800
Short name T619
Test name
Test status
Simulation time 31818685 ps
CPU time 1.34 seconds
Started Jun 10 05:54:52 PM PDT 24
Finished Jun 10 05:54:54 PM PDT 24
Peak memory 198032 kb
Host smart-a411bcc1-7bca-4fef-bf97-c9b488d8404d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466996800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.1466996800
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.2987416933
Short name T199
Test name
Test status
Simulation time 64501170 ps
CPU time 1.23 seconds
Started Jun 10 05:54:51 PM PDT 24
Finished Jun 10 05:54:53 PM PDT 24
Peak memory 195592 kb
Host smart-95346ea9-5d55-46cb-a195-e7d5d08c8f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987416933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.2987416933
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.555778456
Short name T467
Test name
Test status
Simulation time 185579067 ps
CPU time 0.93 seconds
Started Jun 10 05:54:47 PM PDT 24
Finished Jun 10 05:54:48 PM PDT 24
Peak memory 195736 kb
Host smart-0580674f-1547-40d2-9204-b94dd03f237e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555778456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.555778456
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.1949613849
Short name T661
Test name
Test status
Simulation time 16593299914 ps
CPU time 101.67 seconds
Started Jun 10 05:54:48 PM PDT 24
Finished Jun 10 05:56:30 PM PDT 24
Peak memory 198208 kb
Host smart-941aa394-1df8-4564-a420-3234ff0564eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949613849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.1949613849
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.3632494490
Short name T150
Test name
Test status
Simulation time 14445615 ps
CPU time 0.58 seconds
Started Jun 10 05:54:47 PM PDT 24
Finished Jun 10 05:54:48 PM PDT 24
Peak memory 194596 kb
Host smart-82a56af4-81a4-47f8-8114-d2ffbbcb7e8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632494490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.3632494490
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.1651143533
Short name T452
Test name
Test status
Simulation time 104604901 ps
CPU time 0.79 seconds
Started Jun 10 05:54:45 PM PDT 24
Finished Jun 10 05:54:46 PM PDT 24
Peak memory 196016 kb
Host smart-09ab8c5a-d328-4083-8aea-f1181766cf6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651143533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.1651143533
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.1459294864
Short name T606
Test name
Test status
Simulation time 341324176 ps
CPU time 16.95 seconds
Started Jun 10 05:54:49 PM PDT 24
Finished Jun 10 05:55:07 PM PDT 24
Peak memory 196480 kb
Host smart-113eb4a3-ffb1-48e1-907c-667e3c869c82
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459294864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.1459294864
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.1450159117
Short name T663
Test name
Test status
Simulation time 59841831 ps
CPU time 0.87 seconds
Started Jun 10 05:54:47 PM PDT 24
Finished Jun 10 05:54:49 PM PDT 24
Peak memory 196700 kb
Host smart-0baf341b-7867-44fd-aa01-1e82c2a423be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450159117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.1450159117
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.1664534308
Short name T300
Test name
Test status
Simulation time 63853153 ps
CPU time 1.11 seconds
Started Jun 10 05:54:45 PM PDT 24
Finished Jun 10 05:54:47 PM PDT 24
Peak memory 195904 kb
Host smart-8e5928f2-43cb-49bf-b802-0392a42648e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664534308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.1664534308
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.4061176783
Short name T432
Test name
Test status
Simulation time 28533921 ps
CPU time 1.13 seconds
Started Jun 10 05:54:45 PM PDT 24
Finished Jun 10 05:54:47 PM PDT 24
Peak memory 197124 kb
Host smart-7554200b-436d-4f59-8e63-adc8c3e1e8e0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061176783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.4061176783
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.2421392301
Short name T652
Test name
Test status
Simulation time 489979951 ps
CPU time 2.95 seconds
Started Jun 10 05:54:52 PM PDT 24
Finished Jun 10 05:54:55 PM PDT 24
Peak memory 197172 kb
Host smart-a1f58ded-d7e7-4c56-86f7-541e3d5104d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421392301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.2421392301
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.3218408596
Short name T683
Test name
Test status
Simulation time 75393212 ps
CPU time 0.76 seconds
Started Jun 10 05:54:45 PM PDT 24
Finished Jun 10 05:54:46 PM PDT 24
Peak memory 195528 kb
Host smart-e9bdf0f0-f504-411f-bc3a-34b5736b7ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218408596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.3218408596
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.1858741043
Short name T154
Test name
Test status
Simulation time 27358615 ps
CPU time 0.98 seconds
Started Jun 10 05:54:47 PM PDT 24
Finished Jun 10 05:54:48 PM PDT 24
Peak memory 195856 kb
Host smart-9c9f9229-c7aa-42f9-af7a-1c8691e3deda
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858741043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.1858741043
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.2197736889
Short name T542
Test name
Test status
Simulation time 244934805 ps
CPU time 3.24 seconds
Started Jun 10 05:54:46 PM PDT 24
Finished Jun 10 05:54:50 PM PDT 24
Peak memory 197956 kb
Host smart-6710bdea-38fd-4b0d-b54f-bf9e9a42d951
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197736889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.2197736889
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.253614284
Short name T48
Test name
Test status
Simulation time 101120177 ps
CPU time 1.5 seconds
Started Jun 10 05:54:42 PM PDT 24
Finished Jun 10 05:54:44 PM PDT 24
Peak memory 195600 kb
Host smart-48f3220e-e595-4b2f-bd1e-e11e57c1caa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253614284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.253614284
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.2777945510
Short name T227
Test name
Test status
Simulation time 80192023 ps
CPU time 1.15 seconds
Started Jun 10 05:54:52 PM PDT 24
Finished Jun 10 05:54:54 PM PDT 24
Peak memory 196772 kb
Host smart-faef9f4c-b40c-4468-ba2b-f340115b3b78
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777945510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.2777945510
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.2413936175
Short name T7
Test name
Test status
Simulation time 31607623688 ps
CPU time 200.43 seconds
Started Jun 10 05:54:46 PM PDT 24
Finished Jun 10 05:58:07 PM PDT 24
Peak memory 198136 kb
Host smart-2f23645a-2038-4d91-8bf4-b1f35931e013
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413936175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.2413936175
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.1747446966
Short name T241
Test name
Test status
Simulation time 53898126 ps
CPU time 0.59 seconds
Started Jun 10 05:54:50 PM PDT 24
Finished Jun 10 05:54:52 PM PDT 24
Peak memory 192928 kb
Host smart-4449e3db-f2ac-43a0-8f33-8a2610344ecb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747446966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.1747446966
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.2310404740
Short name T433
Test name
Test status
Simulation time 173831908 ps
CPU time 0.86 seconds
Started Jun 10 05:55:04 PM PDT 24
Finished Jun 10 05:55:05 PM PDT 24
Peak memory 195592 kb
Host smart-7f528723-0810-4093-876c-2746ee4b5f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310404740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.2310404740
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.3938444291
Short name T204
Test name
Test status
Simulation time 423286366 ps
CPU time 20.01 seconds
Started Jun 10 05:54:49 PM PDT 24
Finished Jun 10 05:55:09 PM PDT 24
Peak memory 196996 kb
Host smart-bc4e8452-e5eb-46e9-976a-18fb48e1cd37
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938444291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.3938444291
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.1260933759
Short name T240
Test name
Test status
Simulation time 241377169 ps
CPU time 1.05 seconds
Started Jun 10 05:54:50 PM PDT 24
Finished Jun 10 05:54:52 PM PDT 24
Peak memory 196688 kb
Host smart-e721a459-9c44-4a97-bccf-e41267a51249
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260933759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.1260933759
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.1814764244
Short name T287
Test name
Test status
Simulation time 38469276 ps
CPU time 1.07 seconds
Started Jun 10 05:55:13 PM PDT 24
Finished Jun 10 05:55:15 PM PDT 24
Peak memory 196440 kb
Host smart-89dea1f0-d84e-4b77-aea2-b0026d900658
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814764244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.1814764244
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.1442291770
Short name T466
Test name
Test status
Simulation time 193606194 ps
CPU time 2.19 seconds
Started Jun 10 05:54:51 PM PDT 24
Finished Jun 10 05:54:54 PM PDT 24
Peak memory 198076 kb
Host smart-d096694c-47b5-4b38-a0d8-c401e1c1338b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442291770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.1442291770
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.1604492244
Short name T65
Test name
Test status
Simulation time 563706984 ps
CPU time 2.49 seconds
Started Jun 10 05:54:50 PM PDT 24
Finished Jun 10 05:54:53 PM PDT 24
Peak memory 198140 kb
Host smart-99d9d2c2-548b-49df-9c37-41132f6da17f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604492244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.1604492244
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.1291215336
Short name T231
Test name
Test status
Simulation time 32655068 ps
CPU time 0.89 seconds
Started Jun 10 05:54:51 PM PDT 24
Finished Jun 10 05:54:53 PM PDT 24
Peak memory 196700 kb
Host smart-2bd11f74-5ac0-4cc3-9dd0-faf859b2407a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291215336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.1291215336
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.4273015898
Short name T448
Test name
Test status
Simulation time 89793673 ps
CPU time 1.19 seconds
Started Jun 10 05:54:56 PM PDT 24
Finished Jun 10 05:54:57 PM PDT 24
Peak memory 195956 kb
Host smart-efdce201-417e-46b8-962d-9e900ed9952d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273015898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.4273015898
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.1426490416
Short name T2
Test name
Test status
Simulation time 295177541 ps
CPU time 3.49 seconds
Started Jun 10 05:54:47 PM PDT 24
Finished Jun 10 05:54:51 PM PDT 24
Peak memory 198092 kb
Host smart-d3d5c616-868d-4bae-8ea4-89b6e27ba635
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426490416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.1426490416
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.4171052149
Short name T366
Test name
Test status
Simulation time 46859861 ps
CPU time 0.99 seconds
Started Jun 10 05:54:58 PM PDT 24
Finished Jun 10 05:54:59 PM PDT 24
Peak memory 195768 kb
Host smart-47992b41-fdd0-4abe-96cf-4b953b59ea51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171052149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.4171052149
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.3463332820
Short name T405
Test name
Test status
Simulation time 149136141 ps
CPU time 0.85 seconds
Started Jun 10 05:54:55 PM PDT 24
Finished Jun 10 05:54:56 PM PDT 24
Peak memory 196368 kb
Host smart-48776575-7724-4ddf-815d-bb59202f7c51
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463332820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.3463332820
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.3805822011
Short name T701
Test name
Test status
Simulation time 50336936278 ps
CPU time 209.91 seconds
Started Jun 10 05:54:50 PM PDT 24
Finished Jun 10 05:58:21 PM PDT 24
Peak memory 198216 kb
Host smart-46676219-aa58-47b1-8aee-55420dcd8a74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805822011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.3805822011
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.1602355553
Short name T57
Test name
Test status
Simulation time 99889413005 ps
CPU time 595.27 seconds
Started Jun 10 05:54:48 PM PDT 24
Finished Jun 10 06:04:43 PM PDT 24
Peak memory 198272 kb
Host smart-0f2f0ff7-a6c2-4a8c-a08c-3c46c5ee3a8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1602355553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.1602355553
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.1496075884
Short name T169
Test name
Test status
Simulation time 35126201 ps
CPU time 0.55 seconds
Started Jun 10 05:54:50 PM PDT 24
Finished Jun 10 05:54:52 PM PDT 24
Peak memory 193912 kb
Host smart-fbba9cb4-3318-43c7-84cd-6cec50839b45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496075884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.1496075884
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.1345120996
Short name T566
Test name
Test status
Simulation time 108313956 ps
CPU time 0.97 seconds
Started Jun 10 05:54:51 PM PDT 24
Finished Jun 10 05:54:53 PM PDT 24
Peak memory 195776 kb
Host smart-22bb6e4f-c03f-4359-a9cb-3d597ff34110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345120996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.1345120996
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.342825595
Short name T628
Test name
Test status
Simulation time 440419506 ps
CPU time 23 seconds
Started Jun 10 05:54:50 PM PDT 24
Finished Jun 10 05:55:14 PM PDT 24
Peak memory 195528 kb
Host smart-a2a82385-5db8-4e7a-b3f5-a6faee27b191
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342825595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stres
s.342825595
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.2316353669
Short name T392
Test name
Test status
Simulation time 68899756 ps
CPU time 1.02 seconds
Started Jun 10 05:54:53 PM PDT 24
Finished Jun 10 05:54:55 PM PDT 24
Peak memory 196612 kb
Host smart-359efaaf-a8f0-4263-b150-0ee2fc9a0ec1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316353669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.2316353669
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.3998755863
Short name T551
Test name
Test status
Simulation time 81834460 ps
CPU time 1.16 seconds
Started Jun 10 05:54:55 PM PDT 24
Finished Jun 10 05:54:57 PM PDT 24
Peak memory 196188 kb
Host smart-ced1500c-cc89-4923-ad63-77e2746715ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998755863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.3998755863
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.3278836415
Short name T250
Test name
Test status
Simulation time 29320593 ps
CPU time 1.25 seconds
Started Jun 10 05:54:50 PM PDT 24
Finished Jun 10 05:54:52 PM PDT 24
Peak memory 198024 kb
Host smart-08d722b4-930f-4475-bb9d-13c55018a8e4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278836415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.3278836415
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.2146039127
Short name T453
Test name
Test status
Simulation time 382254508 ps
CPU time 2.82 seconds
Started Jun 10 05:54:52 PM PDT 24
Finished Jun 10 05:54:56 PM PDT 24
Peak memory 195908 kb
Host smart-2b1806d9-b417-43ec-92b1-ca3255cf5e32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146039127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.2146039127
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.874764413
Short name T581
Test name
Test status
Simulation time 66181756 ps
CPU time 0.66 seconds
Started Jun 10 05:55:04 PM PDT 24
Finished Jun 10 05:55:05 PM PDT 24
Peak memory 194392 kb
Host smart-3b6b3a44-bc2e-4dea-b7a7-740e7543c7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874764413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.874764413
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.323325947
Short name T230
Test name
Test status
Simulation time 24463418 ps
CPU time 0.77 seconds
Started Jun 10 05:54:50 PM PDT 24
Finished Jun 10 05:54:52 PM PDT 24
Peak memory 196280 kb
Host smart-c8e0efed-169c-4257-b929-5c39d9906066
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323325947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullup
_pulldown.323325947
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.3156640874
Short name T531
Test name
Test status
Simulation time 447739743 ps
CPU time 3.71 seconds
Started Jun 10 05:54:53 PM PDT 24
Finished Jun 10 05:54:58 PM PDT 24
Peak memory 198016 kb
Host smart-58b34e5d-5932-48c8-9714-172434363b1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156640874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.3156640874
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.2816069562
Short name T357
Test name
Test status
Simulation time 101678575 ps
CPU time 1.5 seconds
Started Jun 10 05:54:52 PM PDT 24
Finished Jun 10 05:54:55 PM PDT 24
Peak memory 195548 kb
Host smart-ebec20d3-70b9-416f-866e-06ea5ced61b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816069562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.2816069562
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.3895661716
Short name T329
Test name
Test status
Simulation time 178050169 ps
CPU time 0.96 seconds
Started Jun 10 05:54:52 PM PDT 24
Finished Jun 10 05:54:54 PM PDT 24
Peak memory 195552 kb
Host smart-07d83161-cc4a-4b91-95fe-efb6b339cafe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895661716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.3895661716
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.1340477008
Short name T455
Test name
Test status
Simulation time 5344876926 ps
CPU time 77.18 seconds
Started Jun 10 05:54:55 PM PDT 24
Finished Jun 10 05:56:13 PM PDT 24
Peak memory 198240 kb
Host smart-0f3c06c7-c701-447a-803c-a66e08bc2078
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340477008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.1340477008
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.922362359
Short name T59
Test name
Test status
Simulation time 100365044785 ps
CPU time 437.2 seconds
Started Jun 10 05:54:52 PM PDT 24
Finished Jun 10 06:02:09 PM PDT 24
Peak memory 206492 kb
Host smart-4f034b72-5a11-48db-bb94-8268c703ec52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=922362359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.922362359
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.1004790910
Short name T512
Test name
Test status
Simulation time 33908316 ps
CPU time 0.58 seconds
Started Jun 10 05:54:58 PM PDT 24
Finished Jun 10 05:54:59 PM PDT 24
Peak memory 193856 kb
Host smart-87be8cb7-cce5-4eee-aa53-e431899c9340
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004790910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.1004790910
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.3487491351
Short name T311
Test name
Test status
Simulation time 92958346 ps
CPU time 0.78 seconds
Started Jun 10 05:54:53 PM PDT 24
Finished Jun 10 05:54:55 PM PDT 24
Peak memory 195336 kb
Host smart-d67c5b71-1537-4a5b-8b4e-81ecff2a7a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487491351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.3487491351
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.3141176537
Short name T573
Test name
Test status
Simulation time 1450442209 ps
CPU time 19.62 seconds
Started Jun 10 05:54:54 PM PDT 24
Finished Jun 10 05:55:14 PM PDT 24
Peak memory 196944 kb
Host smart-caacc2e8-0af6-4d33-8c50-556b53063dfe
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141176537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.3141176537
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.4172273026
Short name T713
Test name
Test status
Simulation time 65980003 ps
CPU time 0.77 seconds
Started Jun 10 05:54:50 PM PDT 24
Finished Jun 10 05:54:51 PM PDT 24
Peak memory 195976 kb
Host smart-55015690-94a6-4e94-9c7b-271a2874f0d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172273026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.4172273026
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.1151963132
Short name T155
Test name
Test status
Simulation time 54247991 ps
CPU time 0.98 seconds
Started Jun 10 05:55:12 PM PDT 24
Finished Jun 10 05:55:14 PM PDT 24
Peak memory 196652 kb
Host smart-131385bb-d565-40b8-97c8-57ca92bafba4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151963132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.1151963132
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.337305789
Short name T122
Test name
Test status
Simulation time 252145435 ps
CPU time 2.63 seconds
Started Jun 10 05:54:58 PM PDT 24
Finished Jun 10 05:55:01 PM PDT 24
Peak memory 197960 kb
Host smart-977e6e2e-5f43-49ea-b244-43c29ae6e12e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337305789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.gpio_intr_with_filter_rand_intr_event.337305789
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.980300634
Short name T540
Test name
Test status
Simulation time 122761286 ps
CPU time 2.02 seconds
Started Jun 10 05:54:56 PM PDT 24
Finished Jun 10 05:54:58 PM PDT 24
Peak memory 197232 kb
Host smart-924fd25f-5966-4320-8995-ea81169a11fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980300634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger.
980300634
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.282372480
Short name T352
Test name
Test status
Simulation time 35025715 ps
CPU time 1.11 seconds
Started Jun 10 05:54:57 PM PDT 24
Finished Jun 10 05:54:58 PM PDT 24
Peak memory 197192 kb
Host smart-5fd0b6a1-69a1-4417-8a59-5de20811eada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282372480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.282372480
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.1174107824
Short name T365
Test name
Test status
Simulation time 163888032 ps
CPU time 1.4 seconds
Started Jun 10 05:54:55 PM PDT 24
Finished Jun 10 05:54:57 PM PDT 24
Peak memory 197060 kb
Host smart-d7eaa4ec-214f-42c6-b8f8-9d18955e23a2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174107824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.1174107824
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.1449538094
Short name T568
Test name
Test status
Simulation time 462463876 ps
CPU time 6.42 seconds
Started Jun 10 05:54:54 PM PDT 24
Finished Jun 10 05:55:01 PM PDT 24
Peak memory 198016 kb
Host smart-d0925886-c788-4f09-bf56-5c4e3a2e3789
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449538094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.1449538094
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.3136829665
Short name T598
Test name
Test status
Simulation time 137980637 ps
CPU time 1.03 seconds
Started Jun 10 05:55:13 PM PDT 24
Finished Jun 10 05:55:14 PM PDT 24
Peak memory 195800 kb
Host smart-e205c1b2-9ecf-4fd3-9b42-18263b6a1672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136829665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.3136829665
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.3646748496
Short name T165
Test name
Test status
Simulation time 248171334 ps
CPU time 1.13 seconds
Started Jun 10 05:54:55 PM PDT 24
Finished Jun 10 05:54:56 PM PDT 24
Peak memory 195892 kb
Host smart-8db3c8d6-8ecf-44a0-8cbc-0f19af6179c2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646748496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.3646748496
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.3426719637
Short name T9
Test name
Test status
Simulation time 13228634931 ps
CPU time 29.85 seconds
Started Jun 10 05:54:57 PM PDT 24
Finished Jun 10 05:55:27 PM PDT 24
Peak memory 198192 kb
Host smart-8b3238af-1c86-4714-90b4-28623b0af56c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426719637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.3426719637
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.2354042596
Short name T447
Test name
Test status
Simulation time 113623223233 ps
CPU time 1348.32 seconds
Started Jun 10 05:54:56 PM PDT 24
Finished Jun 10 06:17:24 PM PDT 24
Peak memory 198312 kb
Host smart-6a3a8876-72dd-43f8-8a56-5e23c3512263
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2354042596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.2354042596
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.1719794026
Short name T615
Test name
Test status
Simulation time 14350338 ps
CPU time 0.59 seconds
Started Jun 10 05:54:58 PM PDT 24
Finished Jun 10 05:54:59 PM PDT 24
Peak memory 193872 kb
Host smart-98f55259-1404-4e0d-85c1-5cedba24e49a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719794026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.1719794026
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.990638856
Short name T563
Test name
Test status
Simulation time 110320093 ps
CPU time 0.94 seconds
Started Jun 10 05:54:54 PM PDT 24
Finished Jun 10 05:54:56 PM PDT 24
Peak memory 195992 kb
Host smart-360e06f5-a177-4398-8054-d38142b68364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990638856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.990638856
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.1836062418
Short name T257
Test name
Test status
Simulation time 192047176 ps
CPU time 4.14 seconds
Started Jun 10 05:55:09 PM PDT 24
Finished Jun 10 05:55:14 PM PDT 24
Peak memory 195980 kb
Host smart-84d1faf1-5636-48a0-bb0f-97520335c851
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836062418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.1836062418
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.3621715962
Short name T18
Test name
Test status
Simulation time 74133254 ps
CPU time 0.63 seconds
Started Jun 10 05:54:53 PM PDT 24
Finished Jun 10 05:54:55 PM PDT 24
Peak memory 194528 kb
Host smart-7234998d-e9e6-4bc9-ba53-862d8dcbbd5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621715962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.3621715962
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.4107093861
Short name T51
Test name
Test status
Simulation time 174701516 ps
CPU time 0.67 seconds
Started Jun 10 05:55:09 PM PDT 24
Finished Jun 10 05:55:10 PM PDT 24
Peak memory 194452 kb
Host smart-571c63a0-f93f-4a45-bbf2-8e7a5d396cfc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107093861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.4107093861
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.3092748744
Short name T611
Test name
Test status
Simulation time 167129267 ps
CPU time 3.11 seconds
Started Jun 10 05:54:54 PM PDT 24
Finished Jun 10 05:54:58 PM PDT 24
Peak memory 198112 kb
Host smart-e6a26ec3-79fc-4845-9b36-ef8e827632a0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092748744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.3092748744
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.2617360318
Short name T580
Test name
Test status
Simulation time 119558927 ps
CPU time 2.54 seconds
Started Jun 10 05:55:12 PM PDT 24
Finished Jun 10 05:55:15 PM PDT 24
Peak memory 197020 kb
Host smart-a02fd74b-20f3-4f7c-bb76-ef6086c25ea8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617360318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.2617360318
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.2271116289
Short name T414
Test name
Test status
Simulation time 83076337 ps
CPU time 1.39 seconds
Started Jun 10 05:54:53 PM PDT 24
Finished Jun 10 05:54:55 PM PDT 24
Peak memory 197240 kb
Host smart-d181cbc3-1104-4506-8f44-083bcae920de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271116289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.2271116289
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.1250152310
Short name T160
Test name
Test status
Simulation time 139662520 ps
CPU time 1.16 seconds
Started Jun 10 05:54:53 PM PDT 24
Finished Jun 10 05:54:55 PM PDT 24
Peak memory 196944 kb
Host smart-3199255c-f02e-4de0-8099-588209c7c749
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250152310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.1250152310
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.4170077725
Short name T130
Test name
Test status
Simulation time 106711769 ps
CPU time 2.49 seconds
Started Jun 10 05:54:56 PM PDT 24
Finished Jun 10 05:54:59 PM PDT 24
Peak memory 197920 kb
Host smart-ef4dfe47-0d25-4aaf-893b-7c948d820836
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170077725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.4170077725
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.299814025
Short name T391
Test name
Test status
Simulation time 254907104 ps
CPU time 1.15 seconds
Started Jun 10 05:54:52 PM PDT 24
Finished Jun 10 05:54:54 PM PDT 24
Peak memory 195532 kb
Host smart-a6df2756-fd3a-4d53-8439-3c29c204b647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299814025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.299814025
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.1069209518
Short name T205
Test name
Test status
Simulation time 88865977 ps
CPU time 1 seconds
Started Jun 10 05:54:56 PM PDT 24
Finished Jun 10 05:54:57 PM PDT 24
Peak memory 195816 kb
Host smart-91e4a69b-a48e-436f-8478-cb99fdabe044
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069209518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.1069209518
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.1476275614
Short name T274
Test name
Test status
Simulation time 2441417654 ps
CPU time 60.07 seconds
Started Jun 10 05:55:17 PM PDT 24
Finished Jun 10 05:56:17 PM PDT 24
Peak memory 198200 kb
Host smart-044a0ae4-55d1-41bb-8e06-c6031acd56a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476275614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.1476275614
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.513640525
Short name T697
Test name
Test status
Simulation time 14089983 ps
CPU time 0.56 seconds
Started Jun 10 05:54:55 PM PDT 24
Finished Jun 10 05:54:56 PM PDT 24
Peak memory 194180 kb
Host smart-80818608-a6f6-40f2-8a52-3344120275be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513640525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.513640525
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.1734112046
Short name T681
Test name
Test status
Simulation time 25401437 ps
CPU time 0.62 seconds
Started Jun 10 05:55:05 PM PDT 24
Finished Jun 10 05:55:06 PM PDT 24
Peak memory 194120 kb
Host smart-41ae4cfc-4ab9-4e19-8ab4-c7b14b18e9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734112046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.1734112046
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.379619352
Short name T368
Test name
Test status
Simulation time 9155678644 ps
CPU time 24.4 seconds
Started Jun 10 05:55:07 PM PDT 24
Finished Jun 10 05:55:32 PM PDT 24
Peak memory 197728 kb
Host smart-922f6e81-2d4d-4ac1-b734-d4690de3312b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379619352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stres
s.379619352
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.3595278941
Short name T313
Test name
Test status
Simulation time 137514211 ps
CPU time 0.74 seconds
Started Jun 10 05:54:55 PM PDT 24
Finished Jun 10 05:54:57 PM PDT 24
Peak memory 196488 kb
Host smart-b973b272-005d-4e7d-8753-a06613971599
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595278941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.3595278941
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.454332877
Short name T151
Test name
Test status
Simulation time 589401365 ps
CPU time 0.86 seconds
Started Jun 10 05:55:12 PM PDT 24
Finished Jun 10 05:55:13 PM PDT 24
Peak memory 195560 kb
Host smart-ecaeebfc-f525-4b69-81aa-e1edd531098f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454332877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.454332877
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.577376525
Short name T229
Test name
Test status
Simulation time 505045079 ps
CPU time 3.13 seconds
Started Jun 10 05:55:01 PM PDT 24
Finished Jun 10 05:55:05 PM PDT 24
Peak memory 198164 kb
Host smart-8511b52c-2717-4994-90cf-a9824c66e96e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577376525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.gpio_intr_with_filter_rand_intr_event.577376525
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.3446816677
Short name T198
Test name
Test status
Simulation time 301933866 ps
CPU time 2.52 seconds
Started Jun 10 05:55:18 PM PDT 24
Finished Jun 10 05:55:21 PM PDT 24
Peak memory 195896 kb
Host smart-9f02ac69-3a10-434b-9833-b8d6b62d41d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446816677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.3446816677
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.3777463307
Short name T233
Test name
Test status
Simulation time 76715526 ps
CPU time 1.03 seconds
Started Jun 10 05:54:58 PM PDT 24
Finished Jun 10 05:55:00 PM PDT 24
Peak memory 196092 kb
Host smart-fb1f8c52-53e9-4294-b02a-9711fad83392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777463307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.3777463307
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.54551879
Short name T388
Test name
Test status
Simulation time 27279709 ps
CPU time 0.96 seconds
Started Jun 10 05:54:58 PM PDT 24
Finished Jun 10 05:54:59 PM PDT 24
Peak memory 195948 kb
Host smart-f7cbf7ba-4b59-4359-9869-cb307ea0353a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54551879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullup_
pulldown.54551879
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.3520268156
Short name T273
Test name
Test status
Simulation time 85113812 ps
CPU time 3.56 seconds
Started Jun 10 05:55:00 PM PDT 24
Finished Jun 10 05:55:04 PM PDT 24
Peak memory 197932 kb
Host smart-3bfe8543-4303-4945-a741-3e71963552c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520268156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.3520268156
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.637160931
Short name T537
Test name
Test status
Simulation time 105728501 ps
CPU time 0.8 seconds
Started Jun 10 05:54:56 PM PDT 24
Finished Jun 10 05:54:57 PM PDT 24
Peak memory 195300 kb
Host smart-b949d98b-c8a4-4182-9d20-ddf7257194d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637160931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.637160931
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.2804490919
Short name T148
Test name
Test status
Simulation time 37185555 ps
CPU time 1 seconds
Started Jun 10 05:55:06 PM PDT 24
Finished Jun 10 05:55:07 PM PDT 24
Peak memory 195904 kb
Host smart-2b5837b7-a58e-4e4d-8a9d-c9a71f6b234a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804490919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.2804490919
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.1119836578
Short name T384
Test name
Test status
Simulation time 31470253984 ps
CPU time 220.99 seconds
Started Jun 10 05:55:00 PM PDT 24
Finished Jun 10 05:58:41 PM PDT 24
Peak memory 198240 kb
Host smart-63058df6-3490-4c10-92d6-2e6064d43542
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119836578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.1119836578
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.2217298876
Short name T450
Test name
Test status
Simulation time 41315067305 ps
CPU time 454.57 seconds
Started Jun 10 05:54:59 PM PDT 24
Finished Jun 10 06:02:34 PM PDT 24
Peak memory 206512 kb
Host smart-cfb32bdd-99e0-4005-9ba0-0dc5460236d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2217298876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.2217298876
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.40441028
Short name T49
Test name
Test status
Simulation time 13674677 ps
CPU time 0.6 seconds
Started Jun 10 05:55:13 PM PDT 24
Finished Jun 10 05:55:14 PM PDT 24
Peak memory 193900 kb
Host smart-90d4722b-449f-4894-95d9-fce1cacc3be9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40441028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.40441028
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.3991564705
Short name T610
Test name
Test status
Simulation time 16585398 ps
CPU time 0.6 seconds
Started Jun 10 05:54:57 PM PDT 24
Finished Jun 10 05:54:58 PM PDT 24
Peak memory 193964 kb
Host smart-3c25e6a0-d463-4355-97e9-94d3d06c5bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991564705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.3991564705
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.3089650138
Short name T171
Test name
Test status
Simulation time 1793933798 ps
CPU time 27.03 seconds
Started Jun 10 05:55:13 PM PDT 24
Finished Jun 10 05:55:41 PM PDT 24
Peak memory 197000 kb
Host smart-4e6c2028-0998-4997-9f4c-6d9fabaf671d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089650138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.3089650138
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.1128574031
Short name T605
Test name
Test status
Simulation time 325802339 ps
CPU time 0.88 seconds
Started Jun 10 05:55:03 PM PDT 24
Finished Jun 10 05:55:04 PM PDT 24
Peak memory 196816 kb
Host smart-bdbff14c-a971-4767-a54d-34de6173b26c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128574031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.1128574031
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.3988430769
Short name T550
Test name
Test status
Simulation time 106452050 ps
CPU time 1.39 seconds
Started Jun 10 05:54:59 PM PDT 24
Finished Jun 10 05:55:00 PM PDT 24
Peak memory 197128 kb
Host smart-9f082891-ffc0-4657-b531-8852bbd235a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988430769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.3988430769
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.3054124449
Short name T119
Test name
Test status
Simulation time 53487918 ps
CPU time 2.11 seconds
Started Jun 10 05:55:23 PM PDT 24
Finished Jun 10 05:55:25 PM PDT 24
Peak memory 198092 kb
Host smart-81fb2249-4cd4-4a8d-9058-ce79aeed962d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054124449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.3054124449
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.3634764071
Short name T707
Test name
Test status
Simulation time 75227222 ps
CPU time 2.02 seconds
Started Jun 10 05:54:58 PM PDT 24
Finished Jun 10 05:55:00 PM PDT 24
Peak memory 197216 kb
Host smart-17bd129d-bffa-4b03-afc0-5dff670ee33b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634764071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.3634764071
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.2382410120
Short name T84
Test name
Test status
Simulation time 87510128 ps
CPU time 1 seconds
Started Jun 10 05:55:10 PM PDT 24
Finished Jun 10 05:55:12 PM PDT 24
Peak memory 195972 kb
Host smart-0c364dd9-e827-4d98-946c-3e5b1b5259f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382410120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.2382410120
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.1931920971
Short name T407
Test name
Test status
Simulation time 79527129 ps
CPU time 0.88 seconds
Started Jun 10 05:55:00 PM PDT 24
Finished Jun 10 05:55:01 PM PDT 24
Peak memory 196540 kb
Host smart-ef96b521-5e7a-491f-91ae-d212da9901de
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931920971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.1931920971
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.3992165388
Short name T330
Test name
Test status
Simulation time 1320263759 ps
CPU time 5.32 seconds
Started Jun 10 05:55:11 PM PDT 24
Finished Jun 10 05:55:17 PM PDT 24
Peak memory 198124 kb
Host smart-ef94d229-47c9-4ee7-83ee-b6ec74d0fa01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992165388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.3992165388
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.3218564309
Short name T146
Test name
Test status
Simulation time 59466356 ps
CPU time 1.15 seconds
Started Jun 10 05:55:00 PM PDT 24
Finished Jun 10 05:55:01 PM PDT 24
Peak memory 196500 kb
Host smart-7a47f701-196e-4430-83ab-90bf150d6eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218564309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.3218564309
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.146239020
Short name T709
Test name
Test status
Simulation time 69620575 ps
CPU time 0.96 seconds
Started Jun 10 05:55:01 PM PDT 24
Finished Jun 10 05:55:03 PM PDT 24
Peak memory 197176 kb
Host smart-76c9f90a-0e52-44d1-866c-c417901d7902
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146239020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.146239020
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.1699808137
Short name T589
Test name
Test status
Simulation time 5016398253 ps
CPU time 63.31 seconds
Started Jun 10 05:55:16 PM PDT 24
Finished Jun 10 05:56:19 PM PDT 24
Peak memory 198160 kb
Host smart-368df608-b484-4079-934e-8a7b8e0bf80e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699808137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.1699808137
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.895857521
Short name T645
Test name
Test status
Simulation time 39711467 ps
CPU time 0.57 seconds
Started Jun 10 05:55:04 PM PDT 24
Finished Jun 10 05:55:05 PM PDT 24
Peak memory 194648 kb
Host smart-18e9a94b-c5ea-4296-88a4-557138b109ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895857521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.895857521
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.2331251821
Short name T644
Test name
Test status
Simulation time 56790694 ps
CPU time 0.91 seconds
Started Jun 10 05:55:12 PM PDT 24
Finished Jun 10 05:55:14 PM PDT 24
Peak memory 196784 kb
Host smart-c366627c-4060-4eaa-88a0-043aaf003c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331251821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.2331251821
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.1092127058
Short name T446
Test name
Test status
Simulation time 729189488 ps
CPU time 25.01 seconds
Started Jun 10 05:55:02 PM PDT 24
Finished Jun 10 05:55:27 PM PDT 24
Peak memory 196996 kb
Host smart-05acf41c-3588-4f0c-a9e6-3ec0a3c76ec9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092127058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.1092127058
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.2009536333
Short name T309
Test name
Test status
Simulation time 127241139 ps
CPU time 0.71 seconds
Started Jun 10 05:55:03 PM PDT 24
Finished Jun 10 05:55:04 PM PDT 24
Peak memory 194712 kb
Host smart-576c69b8-a7e0-4b9f-be0a-57e7200b32f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009536333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.2009536333
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.2306867905
Short name T14
Test name
Test status
Simulation time 100391662 ps
CPU time 1.4 seconds
Started Jun 10 05:55:04 PM PDT 24
Finished Jun 10 05:55:06 PM PDT 24
Peak memory 195868 kb
Host smart-324f0093-701f-407e-8e3d-c7be1950dd96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306867905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.2306867905
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.3306869020
Short name T439
Test name
Test status
Simulation time 141749063 ps
CPU time 1.8 seconds
Started Jun 10 05:55:13 PM PDT 24
Finished Jun 10 05:55:15 PM PDT 24
Peak memory 198068 kb
Host smart-144a7e07-dbfc-43bf-b18e-ba3091422bf8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306869020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.3306869020
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.875293807
Short name T669
Test name
Test status
Simulation time 122188218 ps
CPU time 2.72 seconds
Started Jun 10 05:55:03 PM PDT 24
Finished Jun 10 05:55:06 PM PDT 24
Peak memory 197456 kb
Host smart-b886c0be-878b-46a1-86db-e8d26fe9ed55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875293807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger.
875293807
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.567785934
Short name T168
Test name
Test status
Simulation time 268311075 ps
CPU time 1.21 seconds
Started Jun 10 05:55:11 PM PDT 24
Finished Jun 10 05:55:12 PM PDT 24
Peak memory 197012 kb
Host smart-6ef33440-ba5a-4b28-8a69-e02be28107d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567785934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.567785934
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.2581158212
Short name T666
Test name
Test status
Simulation time 105612613 ps
CPU time 1.27 seconds
Started Jun 10 05:55:12 PM PDT 24
Finished Jun 10 05:55:14 PM PDT 24
Peak memory 197092 kb
Host smart-7e958d48-d05b-454e-a6d0-28a6ae2eae3a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581158212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.2581158212
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.1384592043
Short name T6
Test name
Test status
Simulation time 2725607179 ps
CPU time 6.21 seconds
Started Jun 10 05:55:02 PM PDT 24
Finished Jun 10 05:55:09 PM PDT 24
Peak memory 198236 kb
Host smart-d6a94b3a-b87b-4620-89e2-20481b50adde
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384592043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.1384592043
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.3759790110
Short name T297
Test name
Test status
Simulation time 61127340 ps
CPU time 1.22 seconds
Started Jun 10 05:55:00 PM PDT 24
Finished Jun 10 05:55:01 PM PDT 24
Peak memory 196244 kb
Host smart-c0a247a1-b665-44c1-978a-97e3d881201f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759790110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.3759790110
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.2329767054
Short name T412
Test name
Test status
Simulation time 47290049 ps
CPU time 1.09 seconds
Started Jun 10 05:55:07 PM PDT 24
Finished Jun 10 05:55:08 PM PDT 24
Peak memory 195560 kb
Host smart-4bd610e1-ec99-4cc4-8ea2-f1fb1aa47b35
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329767054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.2329767054
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.994713367
Short name T422
Test name
Test status
Simulation time 9341489232 ps
CPU time 132.36 seconds
Started Jun 10 05:55:14 PM PDT 24
Finished Jun 10 05:57:27 PM PDT 24
Peak memory 198256 kb
Host smart-5a0d73f6-9c97-4aff-8c26-ccf912ed9673
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994713367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.g
pio_stress_all.994713367
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.1703459220
Short name T245
Test name
Test status
Simulation time 13686498 ps
CPU time 0.58 seconds
Started Jun 10 05:53:43 PM PDT 24
Finished Jun 10 05:53:44 PM PDT 24
Peak memory 194652 kb
Host smart-d5ea013e-2539-4288-9b70-5dc11cfb7c85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703459220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.1703459220
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.423599291
Short name T347
Test name
Test status
Simulation time 22288424 ps
CPU time 0.81 seconds
Started Jun 10 05:53:41 PM PDT 24
Finished Jun 10 05:53:42 PM PDT 24
Peak memory 196100 kb
Host smart-70b1e475-6499-4cd9-90a6-1f3b2a128393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423599291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.423599291
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.4118858089
Short name T294
Test name
Test status
Simulation time 1150636273 ps
CPU time 25.33 seconds
Started Jun 10 05:54:00 PM PDT 24
Finished Jun 10 05:54:25 PM PDT 24
Peak memory 198020 kb
Host smart-1009ce9b-62fa-484f-b5c3-c7b4d43ace2e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118858089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.4118858089
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.2661491142
Short name T479
Test name
Test status
Simulation time 117614100 ps
CPU time 1.02 seconds
Started Jun 10 05:53:41 PM PDT 24
Finished Jun 10 05:53:42 PM PDT 24
Peak memory 197940 kb
Host smart-03cda0a4-517b-4658-8212-22b4fd76cf3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661491142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.2661491142
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.2497251999
Short name T506
Test name
Test status
Simulation time 40753061 ps
CPU time 0.88 seconds
Started Jun 10 05:53:41 PM PDT 24
Finished Jun 10 05:53:43 PM PDT 24
Peak memory 195708 kb
Host smart-ed109b7b-8f97-40bb-a197-3f3fb74eec09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497251999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.2497251999
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.443822542
Short name T461
Test name
Test status
Simulation time 121585202 ps
CPU time 3.68 seconds
Started Jun 10 05:53:43 PM PDT 24
Finished Jun 10 05:53:47 PM PDT 24
Peak memory 197988 kb
Host smart-13b3aecb-8a0d-4593-a580-d09c27db5210
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443822542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.gpio_intr_with_filter_rand_intr_event.443822542
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.2598728408
Short name T572
Test name
Test status
Simulation time 48480356 ps
CPU time 0.91 seconds
Started Jun 10 05:53:41 PM PDT 24
Finished Jun 10 05:53:43 PM PDT 24
Peak memory 194552 kb
Host smart-b76fafa0-6130-49db-b7b7-7a3483a12211
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598728408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
2598728408
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.3849602500
Short name T387
Test name
Test status
Simulation time 76074123 ps
CPU time 0.84 seconds
Started Jun 10 05:53:42 PM PDT 24
Finished Jun 10 05:53:43 PM PDT 24
Peak memory 196764 kb
Host smart-db2c9831-b1b8-4f48-a056-df452ae318cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849602500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.3849602500
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.3350229142
Short name T655
Test name
Test status
Simulation time 37568993 ps
CPU time 0.92 seconds
Started Jun 10 05:53:42 PM PDT 24
Finished Jun 10 05:53:44 PM PDT 24
Peak memory 195612 kb
Host smart-722ab853-ae48-4af4-ae14-7d3800be41ec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350229142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.3350229142
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.2086631507
Short name T406
Test name
Test status
Simulation time 338170940 ps
CPU time 4.81 seconds
Started Jun 10 05:53:42 PM PDT 24
Finished Jun 10 05:53:47 PM PDT 24
Peak memory 198012 kb
Host smart-50c755c0-93e1-4d9c-8e15-5ff9c8d59b91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086631507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.2086631507
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.3932705436
Short name T28
Test name
Test status
Simulation time 771607513 ps
CPU time 0.98 seconds
Started Jun 10 05:53:48 PM PDT 24
Finished Jun 10 05:53:50 PM PDT 24
Peak memory 215032 kb
Host smart-4836ee4d-440e-49b8-b14c-4f7a0704a679
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932705436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.3932705436
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.83181206
Short name T125
Test name
Test status
Simulation time 426346726 ps
CPU time 1.02 seconds
Started Jun 10 05:53:44 PM PDT 24
Finished Jun 10 05:53:45 PM PDT 24
Peak memory 196572 kb
Host smart-89a19e6c-1feb-4b95-a732-6e542ebb8b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83181206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.83181206
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.1488385431
Short name T648
Test name
Test status
Simulation time 52364227 ps
CPU time 1.02 seconds
Started Jun 10 05:54:00 PM PDT 24
Finished Jun 10 05:54:02 PM PDT 24
Peak memory 195624 kb
Host smart-e17c44ef-5a6e-4197-ba64-1280e11375d9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488385431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.1488385431
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.157628262
Short name T699
Test name
Test status
Simulation time 2007487721 ps
CPU time 25.76 seconds
Started Jun 10 05:53:44 PM PDT 24
Finished Jun 10 05:54:10 PM PDT 24
Peak memory 198008 kb
Host smart-65b3f233-9f40-47e1-92ef-016be64dfc55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157628262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gp
io_stress_all.157628262
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.3422878443
Short name T718
Test name
Test status
Simulation time 27043008 ps
CPU time 0.59 seconds
Started Jun 10 05:55:31 PM PDT 24
Finished Jun 10 05:55:33 PM PDT 24
Peak memory 194176 kb
Host smart-2609278a-d75f-4a67-91fc-467ebbcb8313
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422878443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.3422878443
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.2037470280
Short name T167
Test name
Test status
Simulation time 126993999 ps
CPU time 0.89 seconds
Started Jun 10 05:55:08 PM PDT 24
Finished Jun 10 05:55:09 PM PDT 24
Peak memory 196096 kb
Host smart-595954c1-58f2-467c-9eb8-c0aed3c093ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037470280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.2037470280
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.2025103440
Short name T242
Test name
Test status
Simulation time 2451172080 ps
CPU time 20.9 seconds
Started Jun 10 05:55:15 PM PDT 24
Finished Jun 10 05:55:36 PM PDT 24
Peak memory 197060 kb
Host smart-ec2e46c9-0843-478a-aea1-df2a5a8d874f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025103440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.2025103440
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.435200494
Short name T656
Test name
Test status
Simulation time 77379332 ps
CPU time 0.84 seconds
Started Jun 10 05:55:09 PM PDT 24
Finished Jun 10 05:55:10 PM PDT 24
Peak memory 195976 kb
Host smart-85264a9c-061d-4b68-8d91-5b8347a6379a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435200494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.435200494
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.689299631
Short name T478
Test name
Test status
Simulation time 105848295 ps
CPU time 1 seconds
Started Jun 10 05:55:11 PM PDT 24
Finished Jun 10 05:55:12 PM PDT 24
Peak memory 196608 kb
Host smart-b4176121-9876-457f-9e3c-64d0e4373878
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689299631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.689299631
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.1726901651
Short name T142
Test name
Test status
Simulation time 289368559 ps
CPU time 1.46 seconds
Started Jun 10 05:55:12 PM PDT 24
Finished Jun 10 05:55:14 PM PDT 24
Peak memory 196608 kb
Host smart-8dba3d33-c78e-4e39-832d-cc6e53e2b217
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726901651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.1726901651
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.2791071147
Short name T116
Test name
Test status
Simulation time 200908839 ps
CPU time 3.25 seconds
Started Jun 10 05:55:14 PM PDT 24
Finished Jun 10 05:55:17 PM PDT 24
Peak memory 195908 kb
Host smart-53c2edba-876c-4866-ac7e-3fd0bb476ec3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791071147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.2791071147
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.2201812604
Short name T354
Test name
Test status
Simulation time 50618257 ps
CPU time 0.72 seconds
Started Jun 10 05:55:30 PM PDT 24
Finished Jun 10 05:55:31 PM PDT 24
Peak memory 195440 kb
Host smart-39982f01-c55c-4265-84fa-b9bca2ebf446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201812604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.2201812604
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.3672976567
Short name T522
Test name
Test status
Simulation time 73467999 ps
CPU time 0.8 seconds
Started Jun 10 05:55:09 PM PDT 24
Finished Jun 10 05:55:10 PM PDT 24
Peak memory 196240 kb
Host smart-9e2df068-a052-4aaa-b714-ce5e9eeeeba1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672976567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.3672976567
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.1026700233
Short name T161
Test name
Test status
Simulation time 529851557 ps
CPU time 4.6 seconds
Started Jun 10 05:55:10 PM PDT 24
Finished Jun 10 05:55:15 PM PDT 24
Peak memory 198108 kb
Host smart-28c481a3-6a85-4635-93a3-197b54e32fd6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026700233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.1026700233
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.1123440148
Short name T118
Test name
Test status
Simulation time 32178489 ps
CPU time 1.04 seconds
Started Jun 10 05:55:01 PM PDT 24
Finished Jun 10 05:55:02 PM PDT 24
Peak memory 196676 kb
Host smart-3a329a17-4b3a-4e11-b1e7-9a134e133b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123440148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.1123440148
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.3343010886
Short name T469
Test name
Test status
Simulation time 118440950 ps
CPU time 1.16 seconds
Started Jun 10 05:55:01 PM PDT 24
Finished Jun 10 05:55:02 PM PDT 24
Peak memory 196572 kb
Host smart-36c78860-9bf7-4628-92e1-70fddc95ff16
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343010886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.3343010886
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.3219813834
Short name T290
Test name
Test status
Simulation time 12135242139 ps
CPU time 175.51 seconds
Started Jun 10 05:55:10 PM PDT 24
Finished Jun 10 05:58:06 PM PDT 24
Peak memory 198196 kb
Host smart-95884b3d-e4ec-4016-9a19-acf4e0ce283d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219813834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.3219813834
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.4191194018
Short name T23
Test name
Test status
Simulation time 310136751540 ps
CPU time 838.96 seconds
Started Jun 10 05:55:05 PM PDT 24
Finished Jun 10 06:09:04 PM PDT 24
Peak memory 198300 kb
Host smart-117332ba-48d3-408c-805a-f468d5a7b828
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4191194018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.4191194018
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.35600968
Short name T31
Test name
Test status
Simulation time 10733717 ps
CPU time 0.58 seconds
Started Jun 10 05:55:13 PM PDT 24
Finished Jun 10 05:55:14 PM PDT 24
Peak memory 194604 kb
Host smart-429394fa-a7a8-4c98-9057-fa8891a17789
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35600968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.35600968
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.3079758362
Short name T307
Test name
Test status
Simulation time 71629375 ps
CPU time 0.65 seconds
Started Jun 10 05:55:17 PM PDT 24
Finished Jun 10 05:55:18 PM PDT 24
Peak memory 194800 kb
Host smart-b1ce9565-f1d2-4e94-a68b-96b93562bb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079758362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.3079758362
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.3163089756
Short name T419
Test name
Test status
Simulation time 1791962097 ps
CPU time 20.06 seconds
Started Jun 10 05:55:16 PM PDT 24
Finished Jun 10 05:55:37 PM PDT 24
Peak memory 196280 kb
Host smart-03207fb3-8c75-4d44-ac74-d436c5a5b849
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163089756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.3163089756
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.1832554385
Short name T520
Test name
Test status
Simulation time 384789839 ps
CPU time 1.09 seconds
Started Jun 10 05:55:07 PM PDT 24
Finished Jun 10 05:55:09 PM PDT 24
Peak memory 196684 kb
Host smart-07dcdd59-feb8-4386-bd41-41db721e61e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832554385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.1832554385
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.3777187368
Short name T492
Test name
Test status
Simulation time 57017041 ps
CPU time 0.9 seconds
Started Jun 10 05:55:02 PM PDT 24
Finished Jun 10 05:55:03 PM PDT 24
Peak memory 195960 kb
Host smart-5d0ad479-ba72-41ce-ae93-f7591b377161
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777187368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.3777187368
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.3269796486
Short name T623
Test name
Test status
Simulation time 170749787 ps
CPU time 1.79 seconds
Started Jun 10 05:55:22 PM PDT 24
Finished Jun 10 05:55:24 PM PDT 24
Peak memory 198172 kb
Host smart-aaf51bd2-631b-48a8-bcee-e6aabaafe8bc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269796486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.3269796486
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.2017493982
Short name T394
Test name
Test status
Simulation time 555105307 ps
CPU time 2.9 seconds
Started Jun 10 05:55:21 PM PDT 24
Finished Jun 10 05:55:24 PM PDT 24
Peak memory 196940 kb
Host smart-b578efa5-2801-4cac-814a-e7763a7aa0fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017493982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.2017493982
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.4083642599
Short name T705
Test name
Test status
Simulation time 200531846 ps
CPU time 1.04 seconds
Started Jun 10 05:55:11 PM PDT 24
Finished Jun 10 05:55:12 PM PDT 24
Peak memory 196636 kb
Host smart-72424255-a4a6-48af-b720-47abbd61ef60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083642599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.4083642599
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.3930893058
Short name T258
Test name
Test status
Simulation time 42218480 ps
CPU time 1.08 seconds
Started Jun 10 05:55:10 PM PDT 24
Finished Jun 10 05:55:12 PM PDT 24
Peak memory 195916 kb
Host smart-fa6d51c8-56f3-47b6-867a-69f9cb11f58e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930893058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.3930893058
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.563310869
Short name T301
Test name
Test status
Simulation time 611518179 ps
CPU time 4.42 seconds
Started Jun 10 05:55:02 PM PDT 24
Finished Jun 10 05:55:07 PM PDT 24
Peak memory 198004 kb
Host smart-632b61e5-b520-4917-ac01-09646dd1d5af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563310869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ran
dom_long_reg_writes_reg_reads.563310869
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.1973602498
Short name T15
Test name
Test status
Simulation time 1157111810 ps
CPU time 1.29 seconds
Started Jun 10 05:55:08 PM PDT 24
Finished Jun 10 05:55:10 PM PDT 24
Peak memory 196616 kb
Host smart-3b8c6c58-c41a-487b-808f-70c36047222e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973602498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.1973602498
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.3112232687
Short name T507
Test name
Test status
Simulation time 76503266 ps
CPU time 1.53 seconds
Started Jun 10 05:55:09 PM PDT 24
Finished Jun 10 05:55:11 PM PDT 24
Peak memory 198016 kb
Host smart-0d53cd32-552f-4079-8e65-ce5f715d8115
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112232687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.3112232687
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.4056624050
Short name T325
Test name
Test status
Simulation time 1536245193 ps
CPU time 16.52 seconds
Started Jun 10 05:55:10 PM PDT 24
Finished Jun 10 05:55:27 PM PDT 24
Peak memory 198120 kb
Host smart-3720521d-535d-42c6-a5ff-6e5ce7c353e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056624050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.4056624050
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.3795130840
Short name T163
Test name
Test status
Simulation time 23376978 ps
CPU time 0.6 seconds
Started Jun 10 05:55:17 PM PDT 24
Finished Jun 10 05:55:18 PM PDT 24
Peak memory 194656 kb
Host smart-65e4814f-edc0-4bbd-b58a-c777612d2cfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795130840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.3795130840
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.154064432
Short name T454
Test name
Test status
Simulation time 22158986 ps
CPU time 0.81 seconds
Started Jun 10 05:55:16 PM PDT 24
Finished Jun 10 05:55:18 PM PDT 24
Peak memory 195356 kb
Host smart-b70917ce-ff59-4ac7-b451-cf1485b087e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154064432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.154064432
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.3442662988
Short name T624
Test name
Test status
Simulation time 9046706179 ps
CPU time 15.9 seconds
Started Jun 10 05:55:17 PM PDT 24
Finished Jun 10 05:55:33 PM PDT 24
Peak memory 196812 kb
Host smart-238a6f76-1767-4273-82ec-e14735c1a8d7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442662988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.3442662988
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.406734731
Short name T524
Test name
Test status
Simulation time 265332539 ps
CPU time 1.08 seconds
Started Jun 10 05:55:16 PM PDT 24
Finished Jun 10 05:55:18 PM PDT 24
Peak memory 197832 kb
Host smart-38e2f158-6f65-424a-a69b-526f96a834fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406734731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.406734731
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.1343426455
Short name T630
Test name
Test status
Simulation time 786007646 ps
CPU time 1.5 seconds
Started Jun 10 05:55:39 PM PDT 24
Finished Jun 10 05:55:41 PM PDT 24
Peak memory 197244 kb
Host smart-5bc23400-1af1-45c2-91ca-7541e7c97161
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343426455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.1343426455
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.813208861
Short name T459
Test name
Test status
Simulation time 127467599 ps
CPU time 3.69 seconds
Started Jun 10 05:55:18 PM PDT 24
Finished Jun 10 05:55:22 PM PDT 24
Peak memory 196536 kb
Host smart-c98675ba-a212-4697-8c14-25c6dcabbebf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813208861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger.
813208861
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.940783285
Short name T499
Test name
Test status
Simulation time 31202713 ps
CPU time 1.2 seconds
Started Jun 10 05:55:11 PM PDT 24
Finished Jun 10 05:55:13 PM PDT 24
Peak memory 198160 kb
Host smart-b81fcb2d-b4e5-40a8-8a29-cae3eb797101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940783285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.940783285
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.3417652470
Short name T312
Test name
Test status
Simulation time 19612923 ps
CPU time 0.68 seconds
Started Jun 10 05:55:19 PM PDT 24
Finished Jun 10 05:55:20 PM PDT 24
Peak memory 194436 kb
Host smart-caa27566-3f41-45ca-8f46-018bd7884eb3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417652470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.3417652470
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.1084705469
Short name T238
Test name
Test status
Simulation time 434908307 ps
CPU time 5.27 seconds
Started Jun 10 05:55:11 PM PDT 24
Finished Jun 10 05:55:17 PM PDT 24
Peak memory 198032 kb
Host smart-573acc9b-feb5-46cf-a308-3f151f760703
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084705469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.1084705469
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.908185759
Short name T235
Test name
Test status
Simulation time 56028158 ps
CPU time 1.21 seconds
Started Jun 10 05:55:18 PM PDT 24
Finished Jun 10 05:55:20 PM PDT 24
Peak memory 195764 kb
Host smart-1dbdf57d-fce6-422b-a7d6-11d9cf795269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908185759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.908185759
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.2751943245
Short name T332
Test name
Test status
Simulation time 33978697 ps
CPU time 1.1 seconds
Started Jun 10 05:55:07 PM PDT 24
Finished Jun 10 05:55:09 PM PDT 24
Peak memory 195792 kb
Host smart-06dd040c-f49a-49fc-a2cc-ef8c32f8c0c4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751943245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.2751943245
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.327467793
Short name T145
Test name
Test status
Simulation time 11702626969 ps
CPU time 37.67 seconds
Started Jun 10 05:55:15 PM PDT 24
Finished Jun 10 05:55:53 PM PDT 24
Peak memory 198168 kb
Host smart-860b0f08-544f-4995-9526-cf2e6f1120bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327467793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.g
pio_stress_all.327467793
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.1710887123
Short name T30
Test name
Test status
Simulation time 87719264 ps
CPU time 0.58 seconds
Started Jun 10 05:55:31 PM PDT 24
Finished Jun 10 05:55:32 PM PDT 24
Peak memory 194668 kb
Host smart-792b613c-ffc5-4660-b8db-92f3d4fa6a75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710887123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.1710887123
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.943061428
Short name T86
Test name
Test status
Simulation time 82934013 ps
CPU time 0.86 seconds
Started Jun 10 05:55:37 PM PDT 24
Finished Jun 10 05:55:39 PM PDT 24
Peak memory 195420 kb
Host smart-b71a2e19-72af-4758-a68e-b94bc072cca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943061428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.943061428
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.3730857053
Short name T11
Test name
Test status
Simulation time 3934793261 ps
CPU time 28.1 seconds
Started Jun 10 05:55:24 PM PDT 24
Finished Jun 10 05:55:53 PM PDT 24
Peak memory 197072 kb
Host smart-b2858bd4-8b0d-446a-be6b-6068e4b61bc4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730857053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.3730857053
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.3828551842
Short name T430
Test name
Test status
Simulation time 29004043 ps
CPU time 0.7 seconds
Started Jun 10 05:55:27 PM PDT 24
Finished Jun 10 05:55:28 PM PDT 24
Peak memory 195576 kb
Host smart-0d18c63f-41e2-4836-9f66-513831cffc27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828551842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.3828551842
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.2571954657
Short name T612
Test name
Test status
Simulation time 242355884 ps
CPU time 1.22 seconds
Started Jun 10 05:55:11 PM PDT 24
Finished Jun 10 05:55:13 PM PDT 24
Peak memory 196516 kb
Host smart-8b80298f-3a51-49df-b25c-48563d1d2b51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571954657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.2571954657
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.1123652922
Short name T213
Test name
Test status
Simulation time 32031397 ps
CPU time 1.44 seconds
Started Jun 10 05:55:16 PM PDT 24
Finished Jun 10 05:55:18 PM PDT 24
Peak memory 197752 kb
Host smart-b0dad6b8-5a31-408b-87ff-d090fe76690c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123652922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.1123652922
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.2157146050
Short name T12
Test name
Test status
Simulation time 42258037 ps
CPU time 0.92 seconds
Started Jun 10 05:55:16 PM PDT 24
Finished Jun 10 05:55:17 PM PDT 24
Peak memory 195500 kb
Host smart-fbcba4bb-b5f5-4f38-b9ed-3587db60d29c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157146050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.2157146050
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.2696352599
Short name T570
Test name
Test status
Simulation time 100142137 ps
CPU time 1.13 seconds
Started Jun 10 05:55:18 PM PDT 24
Finished Jun 10 05:55:19 PM PDT 24
Peak memory 196100 kb
Host smart-175cf414-b314-464f-a455-81e960a45f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696352599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.2696352599
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.2550756569
Short name T629
Test name
Test status
Simulation time 45241868 ps
CPU time 1.1 seconds
Started Jun 10 05:55:11 PM PDT 24
Finished Jun 10 05:55:12 PM PDT 24
Peak memory 196704 kb
Host smart-6cc5e844-41cf-4056-950d-d144684bdc45
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550756569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.2550756569
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.3697544894
Short name T272
Test name
Test status
Simulation time 536994117 ps
CPU time 3.69 seconds
Started Jun 10 05:55:16 PM PDT 24
Finished Jun 10 05:55:20 PM PDT 24
Peak memory 197972 kb
Host smart-0af3bef0-69e6-42e2-bf71-d9ac0dd57afc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697544894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.3697544894
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.2387773393
Short name T528
Test name
Test status
Simulation time 180995477 ps
CPU time 1.08 seconds
Started Jun 10 05:55:28 PM PDT 24
Finished Jun 10 05:55:35 PM PDT 24
Peak memory 195692 kb
Host smart-f42601b2-6e70-4952-b680-51e0152e4b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387773393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.2387773393
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.1497012912
Short name T217
Test name
Test status
Simulation time 158763703 ps
CPU time 1.31 seconds
Started Jun 10 05:55:36 PM PDT 24
Finished Jun 10 05:55:38 PM PDT 24
Peak memory 195460 kb
Host smart-2397de25-37b1-427e-8883-b2b84077bed6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497012912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.1497012912
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.1200052143
Short name T135
Test name
Test status
Simulation time 122688295173 ps
CPU time 215.08 seconds
Started Jun 10 05:55:11 PM PDT 24
Finished Jun 10 05:58:47 PM PDT 24
Peak memory 198128 kb
Host smart-d623bff8-90c2-4cf7-9a31-c744a9e1acde
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200052143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.1200052143
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.2427631222
Short name T526
Test name
Test status
Simulation time 62807859440 ps
CPU time 1047.57 seconds
Started Jun 10 05:55:42 PM PDT 24
Finished Jun 10 06:13:10 PM PDT 24
Peak memory 198288 kb
Host smart-aa5a63e4-1565-4210-b521-1742ad3912df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2427631222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.2427631222
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.2230182325
Short name T408
Test name
Test status
Simulation time 173381174 ps
CPU time 0.59 seconds
Started Jun 10 05:55:31 PM PDT 24
Finished Jun 10 05:55:32 PM PDT 24
Peak memory 193964 kb
Host smart-423ccca7-2ce4-4dd4-b843-4c28f7a4608b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230182325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.2230182325
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.817935225
Short name T456
Test name
Test status
Simulation time 33515685 ps
CPU time 0.7 seconds
Started Jun 10 05:55:23 PM PDT 24
Finished Jun 10 05:55:24 PM PDT 24
Peak memory 195240 kb
Host smart-87fe4e4b-0994-4ee1-9172-0266a9c1d583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817935225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.817935225
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.1414018349
Short name T144
Test name
Test status
Simulation time 4852704131 ps
CPU time 10.42 seconds
Started Jun 10 05:55:14 PM PDT 24
Finished Jun 10 05:55:25 PM PDT 24
Peak memory 197076 kb
Host smart-a66ae679-b239-47d9-b4f3-7b8f0092f244
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414018349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.1414018349
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.4158998852
Short name T68
Test name
Test status
Simulation time 66293646 ps
CPU time 0.91 seconds
Started Jun 10 05:55:26 PM PDT 24
Finished Jun 10 05:55:27 PM PDT 24
Peak memory 197324 kb
Host smart-331b90d7-9469-4a22-b599-bd9a474bb0e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158998852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.4158998852
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.944296151
Short name T511
Test name
Test status
Simulation time 58174928 ps
CPU time 1 seconds
Started Jun 10 05:55:25 PM PDT 24
Finished Jun 10 05:55:26 PM PDT 24
Peak memory 196100 kb
Host smart-1ae01166-1383-4e69-8651-096cbc3a5235
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944296151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.944296151
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.2133685877
Short name T286
Test name
Test status
Simulation time 277854917 ps
CPU time 3.11 seconds
Started Jun 10 05:55:16 PM PDT 24
Finished Jun 10 05:55:19 PM PDT 24
Peak memory 198164 kb
Host smart-7d8d510a-762c-400f-84d3-918cfcb70c62
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133685877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.2133685877
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.3973285815
Short name T289
Test name
Test status
Simulation time 83270178 ps
CPU time 1.83 seconds
Started Jun 10 05:55:18 PM PDT 24
Finished Jun 10 05:55:20 PM PDT 24
Peak memory 196584 kb
Host smart-8c320b53-d236-4f08-9fd1-f3c1a7b116d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973285815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.3973285815
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.2861656118
Short name T320
Test name
Test status
Simulation time 133874042 ps
CPU time 1.04 seconds
Started Jun 10 05:55:17 PM PDT 24
Finished Jun 10 05:55:19 PM PDT 24
Peak memory 195864 kb
Host smart-6853fb98-fa75-4b35-b866-370585c6c936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861656118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.2861656118
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.3668981723
Short name T131
Test name
Test status
Simulation time 29003643 ps
CPU time 1.13 seconds
Started Jun 10 05:55:34 PM PDT 24
Finished Jun 10 05:55:35 PM PDT 24
Peak memory 196160 kb
Host smart-c2766e88-e258-4814-bc94-dd213384e220
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668981723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.3668981723
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.86453841
Short name T489
Test name
Test status
Simulation time 743325517 ps
CPU time 5.55 seconds
Started Jun 10 05:55:17 PM PDT 24
Finished Jun 10 05:55:23 PM PDT 24
Peak memory 198020 kb
Host smart-bdb18e2c-9a08-4c39-8d16-370b15a30a8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86453841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand
om_long_reg_writes_reg_reads.86453841
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.3857639148
Short name T364
Test name
Test status
Simulation time 52539490 ps
CPU time 0.94 seconds
Started Jun 10 05:55:27 PM PDT 24
Finished Jun 10 05:55:28 PM PDT 24
Peak memory 195444 kb
Host smart-2f448fd0-1453-409b-823d-6518cf160062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857639148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.3857639148
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.3172598034
Short name T613
Test name
Test status
Simulation time 660423722 ps
CPU time 1.2 seconds
Started Jun 10 05:55:34 PM PDT 24
Finished Jun 10 05:55:36 PM PDT 24
Peak memory 195596 kb
Host smart-e4c7724a-d9e7-470d-a895-ef8377ebbb2e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172598034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.3172598034
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.1116304315
Short name T4
Test name
Test status
Simulation time 16903655823 ps
CPU time 189.46 seconds
Started Jun 10 05:55:19 PM PDT 24
Finished Jun 10 05:58:29 PM PDT 24
Peak memory 198180 kb
Host smart-0ff13f81-a1c9-42ae-9475-b994eb3956f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116304315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.1116304315
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.3581341397
Short name T618
Test name
Test status
Simulation time 18096399 ps
CPU time 0.56 seconds
Started Jun 10 05:55:19 PM PDT 24
Finished Jun 10 05:55:20 PM PDT 24
Peak memory 193900 kb
Host smart-77c0f20b-6712-4b90-b0f1-7d52d4f3ceb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581341397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.3581341397
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.2211183428
Short name T187
Test name
Test status
Simulation time 84860350 ps
CPU time 0.74 seconds
Started Jun 10 05:55:36 PM PDT 24
Finished Jun 10 05:55:37 PM PDT 24
Peak memory 195260 kb
Host smart-3463aff0-1e59-4cd7-a4e3-a218f89cd4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211183428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.2211183428
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.2263879874
Short name T587
Test name
Test status
Simulation time 3257103860 ps
CPU time 22.14 seconds
Started Jun 10 05:55:14 PM PDT 24
Finished Jun 10 05:55:37 PM PDT 24
Peak memory 197580 kb
Host smart-b7bd7056-cc8e-4ab9-ba6f-d85fbf102516
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263879874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.2263879874
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.2734005453
Short name T444
Test name
Test status
Simulation time 33010736 ps
CPU time 0.72 seconds
Started Jun 10 05:55:29 PM PDT 24
Finished Jun 10 05:55:30 PM PDT 24
Peak memory 194760 kb
Host smart-10b644e6-f9d9-45b2-823d-8fec10abac7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734005453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.2734005453
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.4078619014
Short name T435
Test name
Test status
Simulation time 56303975 ps
CPU time 1.04 seconds
Started Jun 10 05:55:28 PM PDT 24
Finished Jun 10 05:55:29 PM PDT 24
Peak memory 196092 kb
Host smart-fe2b4d2c-2f74-45b8-9405-7d7d97d64cbd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078619014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.4078619014
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.763539568
Short name T212
Test name
Test status
Simulation time 56814364 ps
CPU time 2.16 seconds
Started Jun 10 05:55:33 PM PDT 24
Finished Jun 10 05:55:35 PM PDT 24
Peak memory 198168 kb
Host smart-4f3633b7-5300-48f9-bc86-ff86604e753b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763539568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.gpio_intr_with_filter_rand_intr_event.763539568
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.153366074
Short name T501
Test name
Test status
Simulation time 338595640 ps
CPU time 3.04 seconds
Started Jun 10 05:55:15 PM PDT 24
Finished Jun 10 05:55:18 PM PDT 24
Peak memory 197220 kb
Host smart-919446e2-cb59-4093-81de-b3568b5da005
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153366074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger.
153366074
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.2891165423
Short name T361
Test name
Test status
Simulation time 36402733 ps
CPU time 0.95 seconds
Started Jun 10 05:55:15 PM PDT 24
Finished Jun 10 05:55:16 PM PDT 24
Peak memory 195876 kb
Host smart-5fefed80-4698-4125-9aac-57dd0eab3f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891165423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.2891165423
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.4148818343
Short name T530
Test name
Test status
Simulation time 190459501 ps
CPU time 1.08 seconds
Started Jun 10 05:55:16 PM PDT 24
Finished Jun 10 05:55:18 PM PDT 24
Peak memory 195840 kb
Host smart-83fbebe3-b0e2-4ffb-8f37-476f88247f6b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148818343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.4148818343
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.2062074068
Short name T575
Test name
Test status
Simulation time 196952124 ps
CPU time 2.63 seconds
Started Jun 10 05:55:19 PM PDT 24
Finished Jun 10 05:55:22 PM PDT 24
Peak memory 197960 kb
Host smart-9e3a691a-c324-4d36-90d2-00260f9ff9d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062074068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.2062074068
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.2451986239
Short name T690
Test name
Test status
Simulation time 802897361 ps
CPU time 0.97 seconds
Started Jun 10 05:55:17 PM PDT 24
Finished Jun 10 05:55:18 PM PDT 24
Peak memory 195604 kb
Host smart-7b9b2f2b-8116-4f8e-acc0-a06d4a66752f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451986239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.2451986239
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.2938981085
Short name T638
Test name
Test status
Simulation time 57718079 ps
CPU time 1.49 seconds
Started Jun 10 05:55:34 PM PDT 24
Finished Jun 10 05:55:36 PM PDT 24
Peak memory 195484 kb
Host smart-701d35af-1ee8-4dae-93ec-1484ff98a3dd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938981085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.2938981085
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.325267027
Short name T303
Test name
Test status
Simulation time 32981039647 ps
CPU time 80.47 seconds
Started Jun 10 05:55:43 PM PDT 24
Finished Jun 10 05:57:04 PM PDT 24
Peak memory 198216 kb
Host smart-e8d27c88-969c-44d3-870d-ef220704d338
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325267027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.g
pio_stress_all.325267027
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.3134549816
Short name T465
Test name
Test status
Simulation time 117623762045 ps
CPU time 869.92 seconds
Started Jun 10 05:55:42 PM PDT 24
Finished Jun 10 06:10:14 PM PDT 24
Peak memory 198292 kb
Host smart-ee521864-18f4-4d62-8010-47a7115d589f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3134549816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.3134549816
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.611779351
Short name T203
Test name
Test status
Simulation time 13587690 ps
CPU time 0.58 seconds
Started Jun 10 05:55:37 PM PDT 24
Finished Jun 10 05:55:38 PM PDT 24
Peak memory 193960 kb
Host smart-79966750-8784-450a-bd53-9deededce516
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611779351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.611779351
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.76936885
Short name T374
Test name
Test status
Simulation time 103004661 ps
CPU time 0.85 seconds
Started Jun 10 05:55:36 PM PDT 24
Finished Jun 10 05:55:37 PM PDT 24
Peak memory 196644 kb
Host smart-61844526-4f87-4aeb-bb96-a3e203369149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76936885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.76936885
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.3782523135
Short name T555
Test name
Test status
Simulation time 1611366591 ps
CPU time 13.73 seconds
Started Jun 10 05:55:19 PM PDT 24
Finished Jun 10 05:55:33 PM PDT 24
Peak memory 196888 kb
Host smart-fb21e676-a152-4c50-a546-764f5ac70f2b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782523135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.3782523135
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.1930852449
Short name T344
Test name
Test status
Simulation time 54730591 ps
CPU time 0.74 seconds
Started Jun 10 05:55:36 PM PDT 24
Finished Jun 10 05:55:38 PM PDT 24
Peak memory 196656 kb
Host smart-bf96c7c6-e12d-4f97-af97-16f328fd374c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930852449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.1930852449
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.1868781453
Short name T345
Test name
Test status
Simulation time 59777937 ps
CPU time 0.98 seconds
Started Jun 10 05:55:34 PM PDT 24
Finished Jun 10 05:55:36 PM PDT 24
Peak memory 195944 kb
Host smart-4166ea56-8cb2-4f4b-bd1d-bfececedbb65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868781453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.1868781453
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.2973907158
Short name T136
Test name
Test status
Simulation time 232498239 ps
CPU time 2.41 seconds
Started Jun 10 05:55:40 PM PDT 24
Finished Jun 10 05:55:43 PM PDT 24
Peak memory 198128 kb
Host smart-8bebce7b-a162-41b7-9693-6464a91cd0b2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973907158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.2973907158
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.3659349694
Short name T464
Test name
Test status
Simulation time 89726043 ps
CPU time 1.88 seconds
Started Jun 10 05:55:20 PM PDT 24
Finished Jun 10 05:55:22 PM PDT 24
Peak memory 196136 kb
Host smart-285d5a20-5958-4b46-a50a-74839620ec6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659349694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.3659349694
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.3805781512
Short name T674
Test name
Test status
Simulation time 35226926 ps
CPU time 0.95 seconds
Started Jun 10 05:55:35 PM PDT 24
Finished Jun 10 05:55:37 PM PDT 24
Peak memory 196084 kb
Host smart-2e095602-cad8-4515-afaf-9a42ffbcccda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805781512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.3805781512
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.1078389018
Short name T381
Test name
Test status
Simulation time 73480252 ps
CPU time 0.7 seconds
Started Jun 10 05:55:34 PM PDT 24
Finished Jun 10 05:55:35 PM PDT 24
Peak memory 196216 kb
Host smart-f1fe738f-ee42-4c07-886e-52a173cc2276
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078389018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.1078389018
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.2879148231
Short name T188
Test name
Test status
Simulation time 366569071 ps
CPU time 4.24 seconds
Started Jun 10 05:55:20 PM PDT 24
Finished Jun 10 05:55:25 PM PDT 24
Peak memory 198024 kb
Host smart-dcf554af-c620-4913-9b86-c11788bfa497
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879148231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.2879148231
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.485838327
Short name T472
Test name
Test status
Simulation time 254408610 ps
CPU time 1.41 seconds
Started Jun 10 05:55:22 PM PDT 24
Finished Jun 10 05:55:24 PM PDT 24
Peak memory 197156 kb
Host smart-51fb743c-deac-4a02-8095-89202fe93198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485838327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.485838327
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.2197451050
Short name T331
Test name
Test status
Simulation time 104580126 ps
CPU time 1 seconds
Started Jun 10 05:55:23 PM PDT 24
Finished Jun 10 05:55:24 PM PDT 24
Peak memory 195736 kb
Host smart-049573a8-e9a6-4c57-854d-d3a970b647be
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197451050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.2197451050
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.3675053865
Short name T532
Test name
Test status
Simulation time 22264846025 ps
CPU time 58.25 seconds
Started Jun 10 05:55:22 PM PDT 24
Finished Jun 10 05:56:21 PM PDT 24
Peak memory 198240 kb
Host smart-7a56b5ef-1b7c-4ddd-9e09-e2ce2545642b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675053865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.3675053865
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.2111777865
Short name T210
Test name
Test status
Simulation time 36433881 ps
CPU time 0.56 seconds
Started Jun 10 05:55:34 PM PDT 24
Finished Jun 10 05:55:35 PM PDT 24
Peak memory 193992 kb
Host smart-9f3909d8-a4ea-4d76-b4dd-3cc3131367e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111777865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.2111777865
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.355628984
Short name T514
Test name
Test status
Simulation time 57896298 ps
CPU time 1 seconds
Started Jun 10 05:55:22 PM PDT 24
Finished Jun 10 05:55:23 PM PDT 24
Peak memory 195928 kb
Host smart-38517bc3-2d15-4cee-ae5f-e0f2bde9d47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355628984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.355628984
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.2963417138
Short name T61
Test name
Test status
Simulation time 469322383 ps
CPU time 5.02 seconds
Started Jun 10 05:55:30 PM PDT 24
Finished Jun 10 05:55:36 PM PDT 24
Peak memory 196012 kb
Host smart-46c2866e-0d17-4e73-875f-fd1eac1e5649
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963417138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.2963417138
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.2258423950
Short name T121
Test name
Test status
Simulation time 51146017 ps
CPU time 0.92 seconds
Started Jun 10 05:55:40 PM PDT 24
Finished Jun 10 05:55:42 PM PDT 24
Peak memory 197260 kb
Host smart-50c0ec7f-5af6-4166-a441-889bef137048
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258423950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.2258423950
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.4255674644
Short name T356
Test name
Test status
Simulation time 48211843 ps
CPU time 0.97 seconds
Started Jun 10 05:55:43 PM PDT 24
Finished Jun 10 05:55:45 PM PDT 24
Peak memory 196144 kb
Host smart-0a7c4a5b-bdab-4687-8ce9-e68fe887c1a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255674644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.4255674644
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.763135145
Short name T153
Test name
Test status
Simulation time 95385944 ps
CPU time 2.15 seconds
Started Jun 10 05:55:39 PM PDT 24
Finished Jun 10 05:55:42 PM PDT 24
Peak memory 198168 kb
Host smart-17f2ff77-ddd9-47a6-a317-2a03957a1a5b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763135145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.gpio_intr_with_filter_rand_intr_event.763135145
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.2480399905
Short name T626
Test name
Test status
Simulation time 93987376 ps
CPU time 2.86 seconds
Started Jun 10 05:55:22 PM PDT 24
Finished Jun 10 05:55:25 PM PDT 24
Peak memory 197056 kb
Host smart-723337d0-cefc-4154-9c6d-0a7118282bc9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480399905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.2480399905
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.319446873
Short name T208
Test name
Test status
Simulation time 116214164 ps
CPU time 1.33 seconds
Started Jun 10 05:55:36 PM PDT 24
Finished Jun 10 05:55:38 PM PDT 24
Peak memory 195892 kb
Host smart-11b956cd-1eb8-41a9-9b38-07458a83a95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319446873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.319446873
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.622484010
Short name T558
Test name
Test status
Simulation time 134990957 ps
CPU time 1.09 seconds
Started Jun 10 05:55:40 PM PDT 24
Finished Jun 10 05:55:41 PM PDT 24
Peak memory 195992 kb
Host smart-a608ac1a-9874-417b-a52b-2bd3d92bba0b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622484010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullup
_pulldown.622484010
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.3575882265
Short name T308
Test name
Test status
Simulation time 125510284 ps
CPU time 1.68 seconds
Started Jun 10 05:55:26 PM PDT 24
Finished Jun 10 05:55:28 PM PDT 24
Peak memory 198016 kb
Host smart-d0a13206-8e11-4ec1-ba4e-e7e51a5770d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575882265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.3575882265
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.709573862
Short name T497
Test name
Test status
Simulation time 310244194 ps
CPU time 0.95 seconds
Started Jun 10 05:55:21 PM PDT 24
Finished Jun 10 05:55:23 PM PDT 24
Peak memory 195420 kb
Host smart-7a020470-0540-4958-aa87-f2ada8b99189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709573862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.709573862
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.3410117713
Short name T270
Test name
Test status
Simulation time 119557278 ps
CPU time 1.07 seconds
Started Jun 10 05:55:51 PM PDT 24
Finished Jun 10 05:55:53 PM PDT 24
Peak memory 196424 kb
Host smart-6c46ac37-42ee-4dc4-9f72-ae9fcb227ab2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410117713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.3410117713
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.3691433574
Short name T268
Test name
Test status
Simulation time 25513234506 ps
CPU time 92.74 seconds
Started Jun 10 05:55:23 PM PDT 24
Finished Jun 10 05:56:56 PM PDT 24
Peak memory 198180 kb
Host smart-e7e856b2-7fbc-40ae-9f88-b962c9e65ba8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691433574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.3691433574
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.287021170
Short name T657
Test name
Test status
Simulation time 18697038 ps
CPU time 0.57 seconds
Started Jun 10 05:55:31 PM PDT 24
Finished Jun 10 05:55:32 PM PDT 24
Peak memory 194160 kb
Host smart-7fec5188-f3a6-4bc2-b024-b50e8428cdf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287021170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.287021170
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.449638771
Short name T706
Test name
Test status
Simulation time 188864247 ps
CPU time 1.02 seconds
Started Jun 10 05:55:24 PM PDT 24
Finished Jun 10 05:55:26 PM PDT 24
Peak memory 196536 kb
Host smart-78f050cc-37b2-4ba4-a8b4-22d5595320d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449638771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.449638771
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.2222271250
Short name T214
Test name
Test status
Simulation time 454887864 ps
CPU time 17.29 seconds
Started Jun 10 05:55:23 PM PDT 24
Finished Jun 10 05:55:40 PM PDT 24
Peak memory 196988 kb
Host smart-a555c6e4-2bc7-4611-9e51-1f7e516bfc0d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222271250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.2222271250
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.3171866535
Short name T409
Test name
Test status
Simulation time 73662596 ps
CPU time 0.79 seconds
Started Jun 10 05:55:21 PM PDT 24
Finished Jun 10 05:55:22 PM PDT 24
Peak memory 195940 kb
Host smart-afd9f37c-1f5b-462c-92e7-8d06326d97bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171866535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.3171866535
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.75210084
Short name T724
Test name
Test status
Simulation time 122169648 ps
CPU time 0.96 seconds
Started Jun 10 05:55:24 PM PDT 24
Finished Jun 10 05:55:26 PM PDT 24
Peak memory 196836 kb
Host smart-95e8a463-dd6e-4469-8a17-b9d204a213df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75210084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.75210084
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.2654864343
Short name T646
Test name
Test status
Simulation time 586016662 ps
CPU time 3.3 seconds
Started Jun 10 05:55:23 PM PDT 24
Finished Jun 10 05:55:27 PM PDT 24
Peak memory 198080 kb
Host smart-be288b19-8620-4069-b4a9-562937ba1d80
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654864343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.2654864343
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.4085312527
Short name T421
Test name
Test status
Simulation time 119111685 ps
CPU time 2.77 seconds
Started Jun 10 05:55:25 PM PDT 24
Finished Jun 10 05:55:28 PM PDT 24
Peak memory 198076 kb
Host smart-4e47113c-1c12-4034-8c16-42893315b0d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085312527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.4085312527
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.1216365918
Short name T639
Test name
Test status
Simulation time 141816045 ps
CPU time 1.17 seconds
Started Jun 10 05:55:24 PM PDT 24
Finished Jun 10 05:55:26 PM PDT 24
Peak memory 196844 kb
Host smart-cb998f11-c41f-4a65-b923-64ca7848dffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216365918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.1216365918
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.736830366
Short name T583
Test name
Test status
Simulation time 188436860 ps
CPU time 1.16 seconds
Started Jun 10 05:55:42 PM PDT 24
Finished Jun 10 05:55:44 PM PDT 24
Peak memory 196556 kb
Host smart-3c399bd4-6dbb-4b40-bb76-83b5b83480f4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736830366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullup
_pulldown.736830366
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.3658116374
Short name T536
Test name
Test status
Simulation time 572474651 ps
CPU time 7.55 seconds
Started Jun 10 05:55:25 PM PDT 24
Finished Jun 10 05:55:33 PM PDT 24
Peak memory 198100 kb
Host smart-24d56684-00a3-49fd-bfab-52d8241b8408
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658116374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.3658116374
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.1737903330
Short name T202
Test name
Test status
Simulation time 84838223 ps
CPU time 1.48 seconds
Started Jun 10 05:55:26 PM PDT 24
Finished Jun 10 05:55:28 PM PDT 24
Peak memory 196876 kb
Host smart-99cb9ae3-b913-4e54-b1f7-53efba4936ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737903330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.1737903330
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.922620858
Short name T710
Test name
Test status
Simulation time 60545966 ps
CPU time 1.18 seconds
Started Jun 10 05:55:40 PM PDT 24
Finished Jun 10 05:55:42 PM PDT 24
Peak memory 195736 kb
Host smart-29a81227-88e1-4517-b9f1-328476cf4aad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922620858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.922620858
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.3437400510
Short name T574
Test name
Test status
Simulation time 40556382789 ps
CPU time 216.51 seconds
Started Jun 10 05:55:21 PM PDT 24
Finished Jun 10 05:58:58 PM PDT 24
Peak memory 198252 kb
Host smart-9d20ad6f-37a9-4d2f-8857-14ecb55ebfb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437400510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.3437400510
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.3914455623
Short name T109
Test name
Test status
Simulation time 76653124155 ps
CPU time 1631.95 seconds
Started Jun 10 05:55:26 PM PDT 24
Finished Jun 10 06:22:38 PM PDT 24
Peak memory 198308 kb
Host smart-85822fa6-19ae-433b-89bb-2ced07dde06e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3914455623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.3914455623
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.201538583
Short name T480
Test name
Test status
Simulation time 24868795 ps
CPU time 0.56 seconds
Started Jun 10 05:55:41 PM PDT 24
Finished Jun 10 05:55:43 PM PDT 24
Peak memory 194640 kb
Host smart-71eabe10-378d-4e1a-a6f6-e099cbadd29d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201538583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.201538583
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.3744926587
Short name T353
Test name
Test status
Simulation time 111790837 ps
CPU time 0.89 seconds
Started Jun 10 05:55:24 PM PDT 24
Finished Jun 10 05:55:25 PM PDT 24
Peak memory 196676 kb
Host smart-172f2462-e7eb-4aa2-a6f4-c75bac689356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744926587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.3744926587
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.1815787946
Short name T280
Test name
Test status
Simulation time 208577251 ps
CPU time 5.98 seconds
Started Jun 10 05:55:24 PM PDT 24
Finished Jun 10 05:55:31 PM PDT 24
Peak memory 197024 kb
Host smart-744761f3-f317-45fb-ae2a-2bbb491d8af9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815787946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.1815787946
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.3063830622
Short name T721
Test name
Test status
Simulation time 383987874 ps
CPU time 1.12 seconds
Started Jun 10 05:55:39 PM PDT 24
Finished Jun 10 05:55:41 PM PDT 24
Peak memory 196676 kb
Host smart-3c4e7a4f-a220-49ff-ac6c-f24f3c5bc7c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063830622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.3063830622
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.241116633
Short name T140
Test name
Test status
Simulation time 615925794 ps
CPU time 1.03 seconds
Started Jun 10 05:55:34 PM PDT 24
Finished Jun 10 05:55:36 PM PDT 24
Peak memory 195840 kb
Host smart-55424ed0-45cd-4b49-89da-391c9feb667a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241116633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.241116633
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.617420506
Short name T346
Test name
Test status
Simulation time 57205820 ps
CPU time 2.42 seconds
Started Jun 10 05:55:25 PM PDT 24
Finished Jun 10 05:55:28 PM PDT 24
Peak memory 198132 kb
Host smart-ab5517c3-f189-452c-8e45-dd75506ab5dd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617420506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.gpio_intr_with_filter_rand_intr_event.617420506
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.2793830649
Short name T152
Test name
Test status
Simulation time 111874765 ps
CPU time 3.24 seconds
Started Jun 10 05:55:40 PM PDT 24
Finished Jun 10 05:55:44 PM PDT 24
Peak memory 197044 kb
Host smart-fd09e33e-2d26-44c1-8db3-3f2e63775fb0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793830649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.2793830649
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.1586470770
Short name T654
Test name
Test status
Simulation time 34745505 ps
CPU time 1.2 seconds
Started Jun 10 05:55:53 PM PDT 24
Finished Jun 10 05:55:54 PM PDT 24
Peak memory 197020 kb
Host smart-8240380b-292d-4f66-9915-bb02d2bd58d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586470770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.1586470770
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.837275839
Short name T525
Test name
Test status
Simulation time 39652657 ps
CPU time 0.67 seconds
Started Jun 10 05:55:39 PM PDT 24
Finished Jun 10 05:55:40 PM PDT 24
Peak memory 195144 kb
Host smart-4a51755c-9cbf-4199-8e1a-2555cf692730
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837275839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullup
_pulldown.837275839
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.1461069593
Short name T594
Test name
Test status
Simulation time 193668373 ps
CPU time 3.67 seconds
Started Jun 10 05:55:38 PM PDT 24
Finished Jun 10 05:55:42 PM PDT 24
Peak memory 197780 kb
Host smart-440c6c43-0718-4780-9e84-a2fecadeb648
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461069593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.1461069593
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.4069043612
Short name T687
Test name
Test status
Simulation time 133751151 ps
CPU time 0.85 seconds
Started Jun 10 05:55:40 PM PDT 24
Finished Jun 10 05:55:41 PM PDT 24
Peak memory 196516 kb
Host smart-3b47e88e-d9b7-49bd-bb82-c8ac39ad8baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069043612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.4069043612
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.3280295987
Short name T127
Test name
Test status
Simulation time 423643351 ps
CPU time 0.88 seconds
Started Jun 10 05:55:28 PM PDT 24
Finished Jun 10 05:55:29 PM PDT 24
Peak memory 197216 kb
Host smart-2a6186c9-3b87-471e-8259-0baefb55dce4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280295987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.3280295987
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.1037244718
Short name T689
Test name
Test status
Simulation time 9370137890 ps
CPU time 57.17 seconds
Started Jun 10 05:55:25 PM PDT 24
Finished Jun 10 05:56:23 PM PDT 24
Peak memory 198220 kb
Host smart-2caf5be5-7798-4622-8ba0-8320cb38c675
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037244718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.1037244718
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.4180493729
Short name T475
Test name
Test status
Simulation time 662320368721 ps
CPU time 2673.57 seconds
Started Jun 10 05:55:38 PM PDT 24
Finished Jun 10 06:40:12 PM PDT 24
Peak memory 198288 kb
Host smart-5ead2178-d0af-40f4-accb-2d1992426f9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4180493729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.4180493729
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.1421736119
Short name T650
Test name
Test status
Simulation time 20900221 ps
CPU time 0.55 seconds
Started Jun 10 05:53:53 PM PDT 24
Finished Jun 10 05:53:54 PM PDT 24
Peak memory 193968 kb
Host smart-0c46630b-61b5-46f8-aa8f-d402402c4019
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421736119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.1421736119
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.1683499637
Short name T462
Test name
Test status
Simulation time 70756873 ps
CPU time 0.77 seconds
Started Jun 10 05:53:52 PM PDT 24
Finished Jun 10 05:53:53 PM PDT 24
Peak memory 195300 kb
Host smart-3dba12f2-e4d7-4f89-9a33-ad5016d3e9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683499637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.1683499637
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.2369159343
Short name T46
Test name
Test status
Simulation time 310688079 ps
CPU time 16 seconds
Started Jun 10 05:53:46 PM PDT 24
Finished Jun 10 05:54:02 PM PDT 24
Peak memory 195568 kb
Host smart-f62feda9-be19-48e3-a9c8-23da9a76e3cf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369159343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.2369159343
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.2096498665
Short name T372
Test name
Test status
Simulation time 283742920 ps
CPU time 1.07 seconds
Started Jun 10 05:53:41 PM PDT 24
Finished Jun 10 05:53:43 PM PDT 24
Peak memory 196592 kb
Host smart-bddab311-a644-4873-bc50-b6bb0830c34c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096498665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.2096498665
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.946343485
Short name T576
Test name
Test status
Simulation time 83532898 ps
CPU time 0.69 seconds
Started Jun 10 05:53:47 PM PDT 24
Finished Jun 10 05:53:48 PM PDT 24
Peak memory 194420 kb
Host smart-ad0e7643-37fd-4993-bf5e-03432510416c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946343485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.946343485
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.2341757762
Short name T404
Test name
Test status
Simulation time 154963948 ps
CPU time 3.2 seconds
Started Jun 10 05:53:47 PM PDT 24
Finished Jun 10 05:53:51 PM PDT 24
Peak memory 197400 kb
Host smart-7fbcacaa-e39e-4594-9e0b-bfd61499c6ba
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341757762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.2341757762
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.933442271
Short name T206
Test name
Test status
Simulation time 424792405 ps
CPU time 2.18 seconds
Started Jun 10 05:54:03 PM PDT 24
Finished Jun 10 05:54:05 PM PDT 24
Peak memory 196076 kb
Host smart-b947ed81-97d5-4712-943f-2b3913ce595c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933442271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.933442271
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.2332446017
Short name T599
Test name
Test status
Simulation time 211648059 ps
CPU time 1.24 seconds
Started Jun 10 05:53:49 PM PDT 24
Finished Jun 10 05:53:50 PM PDT 24
Peak memory 197104 kb
Host smart-d774a549-d95d-4b27-9b52-d303dbcc3630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332446017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.2332446017
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.2093844214
Short name T519
Test name
Test status
Simulation time 27959553 ps
CPU time 1.19 seconds
Started Jun 10 05:53:43 PM PDT 24
Finished Jun 10 05:53:45 PM PDT 24
Peak memory 196784 kb
Host smart-aca210de-cb84-4bed-8b80-6d432508dd90
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093844214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.2093844214
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.3056108808
Short name T328
Test name
Test status
Simulation time 85097203 ps
CPU time 3.63 seconds
Started Jun 10 05:53:44 PM PDT 24
Finished Jun 10 05:53:48 PM PDT 24
Peak memory 198040 kb
Host smart-13364fef-f668-41f6-9bdb-ded35dfa6e94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056108808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.3056108808
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.3671796607
Short name T279
Test name
Test status
Simulation time 47586535 ps
CPU time 1.37 seconds
Started Jun 10 05:53:41 PM PDT 24
Finished Jun 10 05:53:43 PM PDT 24
Peak memory 198052 kb
Host smart-3b092996-6c56-4d81-95b2-b4ee26ccad78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671796607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.3671796607
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.264280000
Short name T327
Test name
Test status
Simulation time 127937542 ps
CPU time 1.17 seconds
Started Jun 10 05:53:48 PM PDT 24
Finished Jun 10 05:53:50 PM PDT 24
Peak memory 195944 kb
Host smart-0332ebb1-e00c-4dc6-a1d9-b38d8b196bec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264280000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.264280000
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.2155020853
Short name T182
Test name
Test status
Simulation time 8646744166 ps
CPU time 30.41 seconds
Started Jun 10 05:53:45 PM PDT 24
Finished Jun 10 05:54:16 PM PDT 24
Peak memory 198200 kb
Host smart-a3c9fd12-1ea1-4d2c-88ab-58b9e37e4aeb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155020853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.2155020853
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.2779303144
Short name T85
Test name
Test status
Simulation time 358289780146 ps
CPU time 1812.63 seconds
Started Jun 10 05:54:01 PM PDT 24
Finished Jun 10 06:24:15 PM PDT 24
Peak memory 198264 kb
Host smart-d844353e-7391-4e4b-b5a2-fab114da1658
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2779303144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.2779303144
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.1503411935
Short name T306
Test name
Test status
Simulation time 22944686 ps
CPU time 0.58 seconds
Started Jun 10 05:53:53 PM PDT 24
Finished Jun 10 05:53:53 PM PDT 24
Peak memory 193968 kb
Host smart-143ccebc-e6b5-448f-8e7f-9423d1ec784a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503411935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.1503411935
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.2686255740
Short name T443
Test name
Test status
Simulation time 108317513 ps
CPU time 0.8 seconds
Started Jun 10 05:53:52 PM PDT 24
Finished Jun 10 05:53:54 PM PDT 24
Peak memory 195492 kb
Host smart-7d991ed0-969f-434e-8b16-866f190f4b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686255740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.2686255740
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.3276007199
Short name T463
Test name
Test status
Simulation time 1413862420 ps
CPU time 20.16 seconds
Started Jun 10 05:53:58 PM PDT 24
Finished Jun 10 05:54:19 PM PDT 24
Peak memory 196276 kb
Host smart-a4c129dc-b1e6-496c-b91c-e6a701a854ea
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276007199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.3276007199
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.3972118385
Short name T500
Test name
Test status
Simulation time 78439324 ps
CPU time 1.08 seconds
Started Jun 10 05:53:46 PM PDT 24
Finished Jun 10 05:53:48 PM PDT 24
Peak memory 197968 kb
Host smart-02002e97-efb4-4c8a-8c73-24b512a59c9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972118385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.3972118385
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.2743515546
Short name T662
Test name
Test status
Simulation time 31132861 ps
CPU time 0.95 seconds
Started Jun 10 05:53:58 PM PDT 24
Finished Jun 10 05:53:59 PM PDT 24
Peak memory 196652 kb
Host smart-5c218794-b3b1-45db-a673-9de47d3c4af4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743515546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.2743515546
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.1164408688
Short name T22
Test name
Test status
Simulation time 155697002 ps
CPU time 3.19 seconds
Started Jun 10 05:53:46 PM PDT 24
Finished Jun 10 05:53:50 PM PDT 24
Peak memory 198180 kb
Host smart-e878cdb1-56e5-43ab-b0b4-19d92eb07e38
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164408688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.1164408688
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.847775962
Short name T60
Test name
Test status
Simulation time 58236028 ps
CPU time 0.97 seconds
Started Jun 10 05:53:49 PM PDT 24
Finished Jun 10 05:53:50 PM PDT 24
Peak memory 196348 kb
Host smart-ba41ca4b-9d68-43b2-b02e-f202432bfaf4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847775962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.847775962
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.473964597
Short name T220
Test name
Test status
Simulation time 104753696 ps
CPU time 0.78 seconds
Started Jun 10 05:53:46 PM PDT 24
Finished Jun 10 05:53:48 PM PDT 24
Peak memory 195576 kb
Host smart-d732226e-ebca-4d42-9e77-070a9ea1de50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473964597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.473964597
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.3644734325
Short name T78
Test name
Test status
Simulation time 92113240 ps
CPU time 0.78 seconds
Started Jun 10 05:53:47 PM PDT 24
Finished Jun 10 05:53:48 PM PDT 24
Peak memory 195648 kb
Host smart-7fdb481b-0793-4b98-ae2d-027bbfa50736
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644734325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.3644734325
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.109414616
Short name T159
Test name
Test status
Simulation time 51111357 ps
CPU time 2.37 seconds
Started Jun 10 05:53:51 PM PDT 24
Finished Jun 10 05:53:54 PM PDT 24
Peak memory 197980 kb
Host smart-8ae0b664-587b-4cca-99d3-cae96b5fcacc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109414616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand
om_long_reg_writes_reg_reads.109414616
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.3920326071
Short name T244
Test name
Test status
Simulation time 65265185 ps
CPU time 1.25 seconds
Started Jun 10 05:53:47 PM PDT 24
Finished Jun 10 05:53:49 PM PDT 24
Peak memory 195700 kb
Host smart-0d1ac018-1203-49d9-a8fd-6cee71ef0942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920326071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.3920326071
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.4198462468
Short name T298
Test name
Test status
Simulation time 105814874 ps
CPU time 1.6 seconds
Started Jun 10 05:54:00 PM PDT 24
Finished Jun 10 05:54:02 PM PDT 24
Peak memory 195668 kb
Host smart-5d9c3b90-7ec0-4e27-85ee-45a7199f7349
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198462468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.4198462468
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.1728593166
Short name T521
Test name
Test status
Simulation time 68893302924 ps
CPU time 91 seconds
Started Jun 10 05:53:46 PM PDT 24
Finished Jun 10 05:55:18 PM PDT 24
Peak memory 198072 kb
Host smart-4cc6e031-4453-4f56-bbf7-375eed2b32da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728593166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.1728593166
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.1238870954
Short name T485
Test name
Test status
Simulation time 14085814 ps
CPU time 0.59 seconds
Started Jun 10 05:53:50 PM PDT 24
Finished Jun 10 05:53:51 PM PDT 24
Peak memory 194168 kb
Host smart-25964510-2246-4833-be48-0476d81e59c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238870954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.1238870954
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.291452481
Short name T677
Test name
Test status
Simulation time 47944762 ps
CPU time 0.71 seconds
Started Jun 10 05:53:54 PM PDT 24
Finished Jun 10 05:53:56 PM PDT 24
Peak memory 194972 kb
Host smart-9f1afa61-490e-491f-ab3e-7387a0904e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291452481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.291452481
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.2956519780
Short name T239
Test name
Test status
Simulation time 86001083 ps
CPU time 3.7 seconds
Started Jun 10 05:53:52 PM PDT 24
Finished Jun 10 05:53:56 PM PDT 24
Peak memory 195992 kb
Host smart-5081b79b-793e-484c-91a5-d2e0e544ab39
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956519780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.2956519780
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.1199633861
Short name T513
Test name
Test status
Simulation time 115308466 ps
CPU time 0.68 seconds
Started Jun 10 05:53:49 PM PDT 24
Finished Jun 10 05:53:51 PM PDT 24
Peak memory 195352 kb
Host smart-96490b6c-ab11-48eb-9313-b90d33b05187
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199633861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.1199633861
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.3007856312
Short name T218
Test name
Test status
Simulation time 60049746 ps
CPU time 0.93 seconds
Started Jun 10 05:54:03 PM PDT 24
Finished Jun 10 05:54:05 PM PDT 24
Peak memory 195832 kb
Host smart-2b7ce5de-9a29-4a49-a4c2-3c662eaeb66e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007856312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.3007856312
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.826583791
Short name T460
Test name
Test status
Simulation time 96553849 ps
CPU time 3.95 seconds
Started Jun 10 05:53:49 PM PDT 24
Finished Jun 10 05:53:54 PM PDT 24
Peak memory 198144 kb
Host smart-d5026895-ca6e-4c03-8aa7-0372584af337
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826583791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.gpio_intr_with_filter_rand_intr_event.826583791
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.798581652
Short name T641
Test name
Test status
Simulation time 270479610 ps
CPU time 2.37 seconds
Started Jun 10 05:54:05 PM PDT 24
Finished Jun 10 05:54:08 PM PDT 24
Peak memory 196528 kb
Host smart-88e90407-dae8-41eb-9f53-af5adc9ef616
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798581652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.798581652
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.624399091
Short name T468
Test name
Test status
Simulation time 126946018 ps
CPU time 0.99 seconds
Started Jun 10 05:54:03 PM PDT 24
Finished Jun 10 05:54:04 PM PDT 24
Peak memory 196080 kb
Host smart-300d4a4a-ad96-47c6-98c9-8d6bf9001674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624399091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.624399091
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.3993222626
Short name T442
Test name
Test status
Simulation time 90960668 ps
CPU time 0.63 seconds
Started Jun 10 05:53:54 PM PDT 24
Finished Jun 10 05:53:55 PM PDT 24
Peak memory 194280 kb
Host smart-24805c03-845a-4192-bad3-3194a4cf94fb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993222626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.3993222626
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.1187428566
Short name T658
Test name
Test status
Simulation time 196848673 ps
CPU time 4.95 seconds
Started Jun 10 05:53:58 PM PDT 24
Finished Jun 10 05:54:04 PM PDT 24
Peak memory 198012 kb
Host smart-33879f7b-e888-4152-8cc7-f2a2551827bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187428566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.1187428566
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.1448059566
Short name T633
Test name
Test status
Simulation time 89816874 ps
CPU time 0.89 seconds
Started Jun 10 05:54:00 PM PDT 24
Finished Jun 10 05:54:01 PM PDT 24
Peak memory 195360 kb
Host smart-cd95e740-4a35-4f1c-8590-47fec57fc9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448059566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.1448059566
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.2311633605
Short name T378
Test name
Test status
Simulation time 127149484 ps
CPU time 1.17 seconds
Started Jun 10 05:53:48 PM PDT 24
Finished Jun 10 05:53:50 PM PDT 24
Peak memory 196924 kb
Host smart-b8fd9a33-4617-478a-9f7b-f93c94d637ec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311633605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.2311633605
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.3080043998
Short name T608
Test name
Test status
Simulation time 38452118108 ps
CPU time 143.58 seconds
Started Jun 10 05:54:00 PM PDT 24
Finished Jun 10 05:56:24 PM PDT 24
Peak memory 198292 kb
Host smart-a6aac83f-edfc-43d5-9fdf-a8a6088dfd6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080043998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.3080043998
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.1490436843
Short name T339
Test name
Test status
Simulation time 33108303 ps
CPU time 0.58 seconds
Started Jun 10 05:54:01 PM PDT 24
Finished Jun 10 05:54:02 PM PDT 24
Peak memory 193956 kb
Host smart-19bf7655-874f-45b4-ae97-b159253d1ae3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490436843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.1490436843
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.1718987704
Short name T539
Test name
Test status
Simulation time 53689569 ps
CPU time 0.66 seconds
Started Jun 10 05:53:51 PM PDT 24
Finished Jun 10 05:53:52 PM PDT 24
Peak memory 194088 kb
Host smart-343830cb-7a0e-43c6-ae80-cf06a5c4ec1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718987704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.1718987704
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.3502570860
Short name T544
Test name
Test status
Simulation time 414202126 ps
CPU time 3.58 seconds
Started Jun 10 05:53:58 PM PDT 24
Finished Jun 10 05:54:02 PM PDT 24
Peak memory 195524 kb
Host smart-8174d700-d1d9-4a9c-a7de-7664214a91dd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502570860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.3502570860
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.2506064254
Short name T162
Test name
Test status
Simulation time 100956252 ps
CPU time 0.71 seconds
Started Jun 10 05:54:01 PM PDT 24
Finished Jun 10 05:54:03 PM PDT 24
Peak memory 194700 kb
Host smart-38c10d63-d736-4eaa-ac0b-18eef1c82074
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506064254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.2506064254
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.313198205
Short name T224
Test name
Test status
Simulation time 23031317 ps
CPU time 0.78 seconds
Started Jun 10 05:53:51 PM PDT 24
Finished Jun 10 05:53:52 PM PDT 24
Peak memory 195436 kb
Host smart-a711b367-0f70-44c2-903e-097525cb90c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313198205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.313198205
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.527295163
Short name T63
Test name
Test status
Simulation time 91707370 ps
CPU time 1.08 seconds
Started Jun 10 05:54:01 PM PDT 24
Finished Jun 10 05:54:03 PM PDT 24
Peak memory 196392 kb
Host smart-278d9e70-c253-4d59-9c0b-f3ea2f19fff2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527295163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.gpio_intr_with_filter_rand_intr_event.527295163
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.260906108
Short name T451
Test name
Test status
Simulation time 82526271 ps
CPU time 1.3 seconds
Started Jun 10 05:53:48 PM PDT 24
Finished Jun 10 05:53:49 PM PDT 24
Peak memory 195792 kb
Host smart-62091e1b-5b3c-46ee-9e61-dfd50dbf81e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260906108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.260906108
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.3064762957
Short name T429
Test name
Test status
Simulation time 16851172 ps
CPU time 0.7 seconds
Started Jun 10 05:54:00 PM PDT 24
Finished Jun 10 05:54:02 PM PDT 24
Peak memory 195384 kb
Host smart-9fc2da78-e904-4792-a5d8-6907e819e348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064762957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.3064762957
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.2356867675
Short name T673
Test name
Test status
Simulation time 174215339 ps
CPU time 1.12 seconds
Started Jun 10 05:53:52 PM PDT 24
Finished Jun 10 05:53:53 PM PDT 24
Peak memory 196708 kb
Host smart-e6e4efbb-dc49-4424-852f-ff161b89e7fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356867675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.2356867675
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.449933436
Short name T382
Test name
Test status
Simulation time 210840186 ps
CPU time 1.95 seconds
Started Jun 10 05:54:05 PM PDT 24
Finished Jun 10 05:54:08 PM PDT 24
Peak memory 198024 kb
Host smart-38749818-39d8-4d6a-aabc-10f21fb0441d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449933436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand
om_long_reg_writes_reg_reads.449933436
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.1373991497
Short name T723
Test name
Test status
Simulation time 116697204 ps
CPU time 0.82 seconds
Started Jun 10 05:54:01 PM PDT 24
Finished Jun 10 05:54:03 PM PDT 24
Peak memory 195268 kb
Host smart-bba5c2eb-34ce-42e8-8fda-475f1183c7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373991497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.1373991497
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.2270685847
Short name T195
Test name
Test status
Simulation time 93492517 ps
CPU time 0.84 seconds
Started Jun 10 05:53:49 PM PDT 24
Finished Jun 10 05:53:50 PM PDT 24
Peak memory 196028 kb
Host smart-52960ef8-151f-4d69-a08a-ce0f19e72666
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270685847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.2270685847
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.4012436764
Short name T529
Test name
Test status
Simulation time 3906047994 ps
CPU time 38.34 seconds
Started Jun 10 05:54:07 PM PDT 24
Finished Jun 10 05:54:45 PM PDT 24
Peak memory 198180 kb
Host smart-7348c638-d097-4a17-8786-7fffd3c7c7f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012436764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.4012436764
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.904632227
Short name T56
Test name
Test status
Simulation time 305170669893 ps
CPU time 1298.81 seconds
Started Jun 10 05:54:04 PM PDT 24
Finished Jun 10 06:15:43 PM PDT 24
Peak memory 198292 kb
Host smart-3e4fc780-b0d2-47a6-a920-504491915dbe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=904632227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.904632227
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.626234219
Short name T259
Test name
Test status
Simulation time 29097739 ps
CPU time 0.54 seconds
Started Jun 10 05:53:56 PM PDT 24
Finished Jun 10 05:53:57 PM PDT 24
Peak memory 193964 kb
Host smart-0a3d3d01-8cc7-4fba-8075-33ef85a44b1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626234219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.626234219
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.464563731
Short name T471
Test name
Test status
Simulation time 25052159 ps
CPU time 0.68 seconds
Started Jun 10 05:54:05 PM PDT 24
Finished Jun 10 05:54:06 PM PDT 24
Peak memory 194180 kb
Host smart-47b960a6-19c1-4fb3-b054-ec1b30883deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464563731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.464563731
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.740539466
Short name T399
Test name
Test status
Simulation time 780871518 ps
CPU time 29 seconds
Started Jun 10 05:54:10 PM PDT 24
Finished Jun 10 05:54:39 PM PDT 24
Peak memory 198072 kb
Host smart-f2747c29-a6d1-4d21-9e92-4b22bc83c703
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740539466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stress
.740539466
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.4008275335
Short name T389
Test name
Test status
Simulation time 119319700 ps
CPU time 0.75 seconds
Started Jun 10 05:54:09 PM PDT 24
Finished Jun 10 05:54:10 PM PDT 24
Peak memory 196088 kb
Host smart-400031ae-05fe-40f4-a810-b074e0181249
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008275335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.4008275335
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.680723895
Short name T225
Test name
Test status
Simulation time 98504621 ps
CPU time 1.33 seconds
Started Jun 10 05:54:08 PM PDT 24
Finished Jun 10 05:54:09 PM PDT 24
Peak memory 198064 kb
Host smart-54450d22-2e34-46e4-a84a-9274edbde8ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680723895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.680723895
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.2596467566
Short name T124
Test name
Test status
Simulation time 169055063 ps
CPU time 3.8 seconds
Started Jun 10 05:54:00 PM PDT 24
Finished Jun 10 05:54:04 PM PDT 24
Peak memory 198172 kb
Host smart-815d87b5-9076-4fbb-b5fa-48cd0f074989
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596467566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.2596467566
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.2573327366
Short name T126
Test name
Test status
Simulation time 90133808 ps
CPU time 2.6 seconds
Started Jun 10 05:53:59 PM PDT 24
Finished Jun 10 05:54:02 PM PDT 24
Peak memory 197364 kb
Host smart-2e59d1c7-4ba9-4e46-9eea-e24977eb817a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573327366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
2573327366
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.2367548942
Short name T700
Test name
Test status
Simulation time 52765227 ps
CPU time 0.61 seconds
Started Jun 10 05:53:58 PM PDT 24
Finished Jun 10 05:53:59 PM PDT 24
Peak memory 194336 kb
Host smart-8fdd94a4-5c26-425f-9d0d-194b359e9148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367548942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.2367548942
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.16884032
Short name T562
Test name
Test status
Simulation time 125719059 ps
CPU time 0.78 seconds
Started Jun 10 05:54:02 PM PDT 24
Finished Jun 10 05:54:03 PM PDT 24
Peak memory 195580 kb
Host smart-0e6f81db-d985-4702-99dc-cd47341adc10
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16884032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup_p
ulldown.16884032
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.1419607254
Short name T682
Test name
Test status
Simulation time 241498870 ps
CPU time 2.74 seconds
Started Jun 10 05:54:06 PM PDT 24
Finished Jun 10 05:54:09 PM PDT 24
Peak memory 198076 kb
Host smart-7910d08d-8bca-4070-8928-9cc355646993
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419607254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.1419607254
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.966747875
Short name T571
Test name
Test status
Simulation time 36295509 ps
CPU time 1.02 seconds
Started Jun 10 05:54:05 PM PDT 24
Finished Jun 10 05:54:07 PM PDT 24
Peak memory 196396 kb
Host smart-b287ae75-6415-44c4-92f7-b802e0b1c367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966747875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.966747875
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.661050281
Short name T322
Test name
Test status
Simulation time 122224583 ps
CPU time 1.08 seconds
Started Jun 10 05:54:08 PM PDT 24
Finished Jun 10 05:54:09 PM PDT 24
Peak memory 195832 kb
Host smart-493514ea-8f9b-4e37-81eb-02954239719c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661050281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.661050281
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.359203013
Short name T190
Test name
Test status
Simulation time 11489742174 ps
CPU time 149.58 seconds
Started Jun 10 05:54:04 PM PDT 24
Finished Jun 10 05:56:34 PM PDT 24
Peak memory 198172 kb
Host smart-2354ce75-0556-4c3c-b57d-aa1a9355761a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359203013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gp
io_stress_all.359203013
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2120250949
Short name T867
Test name
Test status
Simulation time 66419393 ps
CPU time 1.26 seconds
Started Jun 10 05:50:03 PM PDT 24
Finished Jun 10 05:50:05 PM PDT 24
Peak memory 197044 kb
Host smart-01f5438f-f2ff-418a-8358-69d4d517d271
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2120250949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.2120250949
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2079576329
Short name T896
Test name
Test status
Simulation time 33422327 ps
CPU time 1.1 seconds
Started Jun 10 05:49:58 PM PDT 24
Finished Jun 10 05:50:00 PM PDT 24
Peak memory 196588 kb
Host smart-b601de4d-0740-41d9-9169-65499f1a54f8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079576329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2079576329
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1281895588
Short name T847
Test name
Test status
Simulation time 39188957 ps
CPU time 0.82 seconds
Started Jun 10 05:50:00 PM PDT 24
Finished Jun 10 05:50:01 PM PDT 24
Peak memory 195660 kb
Host smart-583e6618-32ba-45bf-b72d-dda514c4f089
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1281895588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.1281895588
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3236057071
Short name T898
Test name
Test status
Simulation time 27275043 ps
CPU time 0.86 seconds
Started Jun 10 05:50:00 PM PDT 24
Finished Jun 10 05:50:01 PM PDT 24
Peak memory 195588 kb
Host smart-02dd1466-aa4c-41d7-a14f-17b9145c1b1c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236057071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3236057071
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3070774728
Short name T900
Test name
Test status
Simulation time 698755000 ps
CPU time 1.05 seconds
Started Jun 10 05:49:59 PM PDT 24
Finished Jun 10 05:50:01 PM PDT 24
Peak memory 198308 kb
Host smart-2864cb63-3959-4132-9079-6b6119012040
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3070774728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.3070774728
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1379878484
Short name T880
Test name
Test status
Simulation time 38336264 ps
CPU time 1.1 seconds
Started Jun 10 05:50:02 PM PDT 24
Finished Jun 10 05:50:03 PM PDT 24
Peak memory 196108 kb
Host smart-360cad80-2699-47c2-8cf1-8482d527059d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379878484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1379878484
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1216512839
Short name T895
Test name
Test status
Simulation time 54847984 ps
CPU time 0.93 seconds
Started Jun 10 05:50:04 PM PDT 24
Finished Jun 10 05:50:05 PM PDT 24
Peak memory 196712 kb
Host smart-a0b9f505-63b7-4915-9ea5-a336fb622430
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1216512839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.1216512839
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4154462251
Short name T849
Test name
Test status
Simulation time 43363119 ps
CPU time 0.91 seconds
Started Jun 10 05:49:57 PM PDT 24
Finished Jun 10 05:49:58 PM PDT 24
Peak memory 196816 kb
Host smart-38797f75-492d-4f61-a3b9-1bff66db56c3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154462251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4154462251
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1052948803
Short name T856
Test name
Test status
Simulation time 158557199 ps
CPU time 1.25 seconds
Started Jun 10 05:50:02 PM PDT 24
Finished Jun 10 05:50:04 PM PDT 24
Peak memory 195932 kb
Host smart-ac44fa78-1e5d-49d4-a1bd-3fc0359ef58b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1052948803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.1052948803
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1258188501
Short name T885
Test name
Test status
Simulation time 637702297 ps
CPU time 1.14 seconds
Started Jun 10 05:50:02 PM PDT 24
Finished Jun 10 05:50:03 PM PDT 24
Peak memory 196972 kb
Host smart-313eef38-d758-4854-a170-f8737214dd3a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258188501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1258188501
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.157090276
Short name T888
Test name
Test status
Simulation time 471693147 ps
CPU time 1.09 seconds
Started Jun 10 05:50:02 PM PDT 24
Finished Jun 10 05:50:03 PM PDT 24
Peak memory 195908 kb
Host smart-68acd921-72e5-4688-aeae-aaad3cf534b6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=157090276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.157090276
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2958694337
Short name T939
Test name
Test status
Simulation time 144604684 ps
CPU time 1.17 seconds
Started Jun 10 05:50:02 PM PDT 24
Finished Jun 10 05:50:03 PM PDT 24
Peak memory 198236 kb
Host smart-a29cc759-bfdc-468f-b63c-6062c1906a63
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958694337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2958694337
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3433413289
Short name T932
Test name
Test status
Simulation time 43923172 ps
CPU time 0.91 seconds
Started Jun 10 05:50:00 PM PDT 24
Finished Jun 10 05:50:01 PM PDT 24
Peak memory 196768 kb
Host smart-2e6bd90d-e58c-4e39-b156-eaf5a064369e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3433413289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.3433413289
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1297096099
Short name T935
Test name
Test status
Simulation time 146627347 ps
CPU time 1.41 seconds
Started Jun 10 05:50:03 PM PDT 24
Finished Jun 10 05:50:05 PM PDT 24
Peak memory 197060 kb
Host smart-6ae8b48f-03b9-4594-b45e-d9b4b7921afd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297096099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1297096099
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3676869504
Short name T901
Test name
Test status
Simulation time 26893293 ps
CPU time 0.93 seconds
Started Jun 10 05:50:01 PM PDT 24
Finished Jun 10 05:50:02 PM PDT 24
Peak memory 195744 kb
Host smart-cbc73a1f-6919-417b-b13d-baa0e0d19c81
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3676869504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.3676869504
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2956773733
Short name T920
Test name
Test status
Simulation time 47980557 ps
CPU time 1.08 seconds
Started Jun 10 05:50:06 PM PDT 24
Finished Jun 10 05:50:08 PM PDT 24
Peak memory 198140 kb
Host smart-e249636c-1860-4a22-96ab-608f27e9d1d8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956773733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2956773733
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1938463006
Short name T941
Test name
Test status
Simulation time 54229890 ps
CPU time 1.04 seconds
Started Jun 10 05:50:07 PM PDT 24
Finished Jun 10 05:50:08 PM PDT 24
Peak memory 198116 kb
Host smart-76ac8553-0cb0-4ddd-a272-ffed55c19f2a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1938463006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.1938463006
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3167007939
Short name T883
Test name
Test status
Simulation time 72113889 ps
CPU time 0.88 seconds
Started Jun 10 05:50:09 PM PDT 24
Finished Jun 10 05:50:11 PM PDT 24
Peak memory 195780 kb
Host smart-cfce72e8-47ad-47e4-a16f-db54cf013949
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167007939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3167007939
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3346375332
Short name T945
Test name
Test status
Simulation time 57935628 ps
CPU time 1.19 seconds
Started Jun 10 05:50:08 PM PDT 24
Finished Jun 10 05:50:09 PM PDT 24
Peak memory 198260 kb
Host smart-22d84f00-34bb-492c-9f51-ce6eeec26c16
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3346375332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.3346375332
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2861170425
Short name T921
Test name
Test status
Simulation time 36357801 ps
CPU time 1.01 seconds
Started Jun 10 05:50:07 PM PDT 24
Finished Jun 10 05:50:08 PM PDT 24
Peak memory 197072 kb
Host smart-74f4e650-0959-4852-8846-035d392fc9a5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861170425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2861170425
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.844149702
Short name T905
Test name
Test status
Simulation time 59377862 ps
CPU time 1.14 seconds
Started Jun 10 05:50:05 PM PDT 24
Finished Jun 10 05:50:07 PM PDT 24
Peak memory 196676 kb
Host smart-858b6420-79de-4987-b6d3-599cacd77cf8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=844149702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.844149702
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4091542
Short name T931
Test name
Test status
Simulation time 1085313680 ps
CPU time 1.24 seconds
Started Jun 10 05:50:04 PM PDT 24
Finished Jun 10 05:50:05 PM PDT 24
Peak memory 196888 kb
Host smart-367f595b-8614-4bf5-a8b4-0156dcd69521
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.4091542
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2873981644
Short name T940
Test name
Test status
Simulation time 83719984 ps
CPU time 1.35 seconds
Started Jun 10 05:50:07 PM PDT 24
Finished Jun 10 05:50:09 PM PDT 24
Peak memory 197232 kb
Host smart-d139ad06-775a-4c8b-91a0-543c6a37485d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2873981644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.2873981644
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2404217480
Short name T892
Test name
Test status
Simulation time 72667853 ps
CPU time 0.86 seconds
Started Jun 10 05:50:06 PM PDT 24
Finished Jun 10 05:50:08 PM PDT 24
Peak memory 195532 kb
Host smart-1896b0e5-db56-4c6b-9415-cffc90f0089f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404217480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2404217480
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.422263592
Short name T944
Test name
Test status
Simulation time 551465786 ps
CPU time 1.35 seconds
Started Jun 10 05:49:56 PM PDT 24
Finished Jun 10 05:49:58 PM PDT 24
Peak memory 197204 kb
Host smart-95878503-17e5-4ad5-bf7f-921b6322c318
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=422263592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.422263592
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1165332087
Short name T933
Test name
Test status
Simulation time 257641451 ps
CPU time 0.88 seconds
Started Jun 10 05:49:59 PM PDT 24
Finished Jun 10 05:50:01 PM PDT 24
Peak memory 196772 kb
Host smart-5daf93ea-b463-4453-bda8-fb1d0bbafec6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165332087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1165332087
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.289052555
Short name T852
Test name
Test status
Simulation time 123600150 ps
CPU time 1.14 seconds
Started Jun 10 05:50:08 PM PDT 24
Finished Jun 10 05:50:10 PM PDT 24
Peak memory 196084 kb
Host smart-99612b52-7ecf-4959-aa01-e4b4c6f9285a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=289052555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.289052555
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1126231519
Short name T942
Test name
Test status
Simulation time 39209232 ps
CPU time 1.03 seconds
Started Jun 10 05:50:07 PM PDT 24
Finished Jun 10 05:50:09 PM PDT 24
Peak memory 196832 kb
Host smart-12501742-4504-4f38-b381-3d62f139fbcd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126231519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1126231519
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.728455258
Short name T848
Test name
Test status
Simulation time 45685251 ps
CPU time 1.05 seconds
Started Jun 10 05:50:09 PM PDT 24
Finished Jun 10 05:50:10 PM PDT 24
Peak memory 195908 kb
Host smart-a1b90b94-f805-4493-9b4f-2899e6143622
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=728455258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.728455258
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3906896401
Short name T925
Test name
Test status
Simulation time 93437713 ps
CPU time 0.92 seconds
Started Jun 10 05:50:06 PM PDT 24
Finished Jun 10 05:50:07 PM PDT 24
Peak memory 196792 kb
Host smart-d506130c-0d69-473a-85cf-25d41569cd7d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906896401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3906896401
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.4040599932
Short name T906
Test name
Test status
Simulation time 59322039 ps
CPU time 1.17 seconds
Started Jun 10 05:50:07 PM PDT 24
Finished Jun 10 05:50:09 PM PDT 24
Peak memory 196960 kb
Host smart-68767c6d-23f0-4748-b3de-6c0bd8f91bdf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4040599932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.4040599932
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2926650178
Short name T930
Test name
Test status
Simulation time 102452276 ps
CPU time 1.2 seconds
Started Jun 10 05:50:12 PM PDT 24
Finished Jun 10 05:50:13 PM PDT 24
Peak memory 196900 kb
Host smart-4e56ea27-1989-4fb5-ad02-0481e811a7dc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926650178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2926650178
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.4133533913
Short name T937
Test name
Test status
Simulation time 272427535 ps
CPU time 0.95 seconds
Started Jun 10 05:50:15 PM PDT 24
Finished Jun 10 05:50:17 PM PDT 24
Peak memory 196972 kb
Host smart-20a49f03-6b43-4d41-a506-92283763e25e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4133533913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.4133533913
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2768830654
Short name T851
Test name
Test status
Simulation time 652273266 ps
CPU time 1.19 seconds
Started Jun 10 05:50:11 PM PDT 24
Finished Jun 10 05:50:12 PM PDT 24
Peak memory 198220 kb
Host smart-c4cca1d9-cc90-4e06-9ea0-1d5603a164b9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768830654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2768830654
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3673491026
Short name T929
Test name
Test status
Simulation time 158270051 ps
CPU time 1.03 seconds
Started Jun 10 05:50:11 PM PDT 24
Finished Jun 10 05:50:12 PM PDT 24
Peak memory 198208 kb
Host smart-ac0dd53c-9282-466a-9e8c-849aab58af38
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3673491026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.3673491026
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2168383335
Short name T908
Test name
Test status
Simulation time 136514727 ps
CPU time 0.9 seconds
Started Jun 10 05:50:18 PM PDT 24
Finished Jun 10 05:50:19 PM PDT 24
Peak memory 195580 kb
Host smart-7216a886-37a8-4491-8351-8c91b63eadae
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168383335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2168383335
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.692511424
Short name T871
Test name
Test status
Simulation time 64060985 ps
CPU time 1.18 seconds
Started Jun 10 05:50:20 PM PDT 24
Finished Jun 10 05:50:22 PM PDT 24
Peak memory 196960 kb
Host smart-ebd74dde-e9bc-4875-9cef-6bd7eba553e4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=692511424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.692511424
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1878470704
Short name T858
Test name
Test status
Simulation time 40707679 ps
CPU time 0.97 seconds
Started Jun 10 05:50:11 PM PDT 24
Finished Jun 10 05:50:12 PM PDT 24
Peak memory 198148 kb
Host smart-5506c3df-9f34-4eb0-b76d-c9a14871fa80
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878470704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1878470704
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1000625006
Short name T861
Test name
Test status
Simulation time 123397798 ps
CPU time 1.24 seconds
Started Jun 10 05:50:14 PM PDT 24
Finished Jun 10 05:50:16 PM PDT 24
Peak memory 196756 kb
Host smart-6026ba87-7499-49c7-b614-60191e9f0585
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1000625006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1000625006
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3615611997
Short name T943
Test name
Test status
Simulation time 82166111 ps
CPU time 1.57 seconds
Started Jun 10 05:50:11 PM PDT 24
Finished Jun 10 05:50:13 PM PDT 24
Peak memory 198260 kb
Host smart-899c2d69-3710-4241-a54c-7732fd6db9ae
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615611997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3615611997
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3915527303
Short name T911
Test name
Test status
Simulation time 42779680 ps
CPU time 1.36 seconds
Started Jun 10 05:50:12 PM PDT 24
Finished Jun 10 05:50:14 PM PDT 24
Peak memory 198140 kb
Host smart-756b63ec-0bf3-4254-a9a3-ee37c40c4493
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3915527303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.3915527303
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.684957582
Short name T891
Test name
Test status
Simulation time 40477395 ps
CPU time 1.28 seconds
Started Jun 10 05:50:11 PM PDT 24
Finished Jun 10 05:50:13 PM PDT 24
Peak memory 196912 kb
Host smart-a0aa62f3-3b87-47cf-96a4-aabfffb792a4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684957582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.684957582
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.758435700
Short name T894
Test name
Test status
Simulation time 47351743 ps
CPU time 1.24 seconds
Started Jun 10 05:50:13 PM PDT 24
Finished Jun 10 05:50:15 PM PDT 24
Peak memory 196828 kb
Host smart-937b3f13-46fc-48f2-a249-07c31b169012
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=758435700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.758435700
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.225052940
Short name T889
Test name
Test status
Simulation time 101689064 ps
CPU time 0.95 seconds
Started Jun 10 05:50:11 PM PDT 24
Finished Jun 10 05:50:13 PM PDT 24
Peak memory 198172 kb
Host smart-738803e5-c963-4e70-a055-81d82c97d643
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225052940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.225052940
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2824475820
Short name T863
Test name
Test status
Simulation time 537275332 ps
CPU time 1.28 seconds
Started Jun 10 05:50:11 PM PDT 24
Finished Jun 10 05:50:12 PM PDT 24
Peak memory 197296 kb
Host smart-929d5478-d4b9-4c03-a8cb-a6da9c978ede
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2824475820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.2824475820
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2130102916
Short name T876
Test name
Test status
Simulation time 44041395 ps
CPU time 0.93 seconds
Started Jun 10 05:50:10 PM PDT 24
Finished Jun 10 05:50:11 PM PDT 24
Peak memory 196876 kb
Host smart-b66c6149-9840-49d8-8504-62234c87c6f1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130102916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2130102916
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.532595733
Short name T854
Test name
Test status
Simulation time 63077151 ps
CPU time 1.17 seconds
Started Jun 10 05:49:56 PM PDT 24
Finished Jun 10 05:49:58 PM PDT 24
Peak memory 196912 kb
Host smart-fe9e6045-3ad4-4314-b8e0-d80558132aee
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=532595733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.532595733
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1436546298
Short name T919
Test name
Test status
Simulation time 234467244 ps
CPU time 1.28 seconds
Started Jun 10 05:50:03 PM PDT 24
Finished Jun 10 05:50:05 PM PDT 24
Peak memory 195904 kb
Host smart-1bb8c5d3-3638-46de-b4ca-5680455aaff8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436546298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1436546298
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1046712120
Short name T875
Test name
Test status
Simulation time 31457471 ps
CPU time 1.01 seconds
Started Jun 10 05:50:15 PM PDT 24
Finished Jun 10 05:50:16 PM PDT 24
Peak memory 196728 kb
Host smart-e6ff5a6c-5fe5-421d-a734-1572317e145a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1046712120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.1046712120
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3449341543
Short name T928
Test name
Test status
Simulation time 58145970 ps
CPU time 1.25 seconds
Started Jun 10 05:50:12 PM PDT 24
Finished Jun 10 05:50:13 PM PDT 24
Peak memory 196764 kb
Host smart-7a942245-7deb-4e46-91b1-896fb3a47660
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449341543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3449341543
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.179284130
Short name T884
Test name
Test status
Simulation time 102879051 ps
CPU time 0.99 seconds
Started Jun 10 05:50:18 PM PDT 24
Finished Jun 10 05:50:20 PM PDT 24
Peak memory 196908 kb
Host smart-669701eb-f537-4ff5-85e5-5cf765cecd1b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=179284130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.179284130
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.296342683
Short name T909
Test name
Test status
Simulation time 92732161 ps
CPU time 1.4 seconds
Started Jun 10 05:50:15 PM PDT 24
Finished Jun 10 05:50:17 PM PDT 24
Peak memory 195844 kb
Host smart-220304f9-c420-44e3-a690-1c6e9317a44f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296342683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.296342683
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3986651476
Short name T903
Test name
Test status
Simulation time 264732316 ps
CPU time 1.38 seconds
Started Jun 10 05:50:11 PM PDT 24
Finished Jun 10 05:50:13 PM PDT 24
Peak memory 196820 kb
Host smart-171202f2-546c-450a-8105-7d5e065ca7e1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3986651476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.3986651476
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3716444784
Short name T902
Test name
Test status
Simulation time 75789634 ps
CPU time 1.33 seconds
Started Jun 10 05:50:13 PM PDT 24
Finished Jun 10 05:50:14 PM PDT 24
Peak memory 196652 kb
Host smart-78e98006-f235-4cf4-99eb-185c64120e95
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716444784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3716444784
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3680598532
Short name T946
Test name
Test status
Simulation time 157778235 ps
CPU time 1.12 seconds
Started Jun 10 05:50:19 PM PDT 24
Finished Jun 10 05:50:20 PM PDT 24
Peak memory 196732 kb
Host smart-e32d7f3e-8157-402b-aebf-c19733a902b5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3680598532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.3680598532
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1803150399
Short name T893
Test name
Test status
Simulation time 193911627 ps
CPU time 1.2 seconds
Started Jun 10 05:50:13 PM PDT 24
Finished Jun 10 05:50:15 PM PDT 24
Peak memory 196020 kb
Host smart-0a30a551-91aa-4a2c-8f77-a431304a857a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803150399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1803150399
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2587523609
Short name T868
Test name
Test status
Simulation time 114227728 ps
CPU time 0.77 seconds
Started Jun 10 05:50:19 PM PDT 24
Finished Jun 10 05:50:20 PM PDT 24
Peak memory 195736 kb
Host smart-2ee5439d-8a44-4e45-a92e-499122846263
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2587523609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.2587523609
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1334931893
Short name T878
Test name
Test status
Simulation time 276262764 ps
CPU time 1.16 seconds
Started Jun 10 05:50:18 PM PDT 24
Finished Jun 10 05:50:20 PM PDT 24
Peak memory 197972 kb
Host smart-9aa2443c-984b-4b38-96ab-6c788f8d8c92
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334931893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1334931893
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1674780480
Short name T859
Test name
Test status
Simulation time 922550135 ps
CPU time 1.2 seconds
Started Jun 10 05:50:13 PM PDT 24
Finished Jun 10 05:50:14 PM PDT 24
Peak memory 196156 kb
Host smart-b3b2c7e4-6711-452d-9783-28b7a2be36c3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1674780480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.1674780480
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3588522175
Short name T923
Test name
Test status
Simulation time 1122846933 ps
CPU time 1.2 seconds
Started Jun 10 05:50:13 PM PDT 24
Finished Jun 10 05:50:14 PM PDT 24
Peak memory 195864 kb
Host smart-9a3f60d0-e862-4f66-a19e-c05f5fb8e232
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588522175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3588522175
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.938799942
Short name T874
Test name
Test status
Simulation time 224022238 ps
CPU time 1.14 seconds
Started Jun 10 05:50:13 PM PDT 24
Finished Jun 10 05:50:14 PM PDT 24
Peak memory 196832 kb
Host smart-617c5996-2849-4b99-84ed-525f9f6a9e87
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=938799942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.938799942
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.958701441
Short name T886
Test name
Test status
Simulation time 35277320 ps
CPU time 0.82 seconds
Started Jun 10 05:50:14 PM PDT 24
Finished Jun 10 05:50:15 PM PDT 24
Peak memory 195796 kb
Host smart-ef4f8b5b-2515-4169-b2a9-47952064545e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958701441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.958701441
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1511255725
Short name T853
Test name
Test status
Simulation time 69782443 ps
CPU time 0.75 seconds
Started Jun 10 05:50:19 PM PDT 24
Finished Jun 10 05:50:20 PM PDT 24
Peak memory 195628 kb
Host smart-2dcbaa9e-b28e-4163-b4a1-d012a99192bb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1511255725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.1511255725
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.628338499
Short name T879
Test name
Test status
Simulation time 79959275 ps
CPU time 1.04 seconds
Started Jun 10 05:50:12 PM PDT 24
Finished Jun 10 05:50:13 PM PDT 24
Peak memory 196832 kb
Host smart-3ccfc147-2d91-4cd8-8d68-adfc2cb7905f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628338499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.628338499
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3863863755
Short name T866
Test name
Test status
Simulation time 465906439 ps
CPU time 1.01 seconds
Started Jun 10 05:50:09 PM PDT 24
Finished Jun 10 05:50:10 PM PDT 24
Peak memory 198180 kb
Host smart-47ea90dd-5d97-4a1c-9272-bc89f44869a3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3863863755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.3863863755
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3062056934
Short name T862
Test name
Test status
Simulation time 138004944 ps
CPU time 1.24 seconds
Started Jun 10 05:50:18 PM PDT 24
Finished Jun 10 05:50:20 PM PDT 24
Peak memory 196964 kb
Host smart-4f803dc3-48e6-4bea-a0ec-fea813410be1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062056934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3062056934
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2181860544
Short name T864
Test name
Test status
Simulation time 60405144 ps
CPU time 1.41 seconds
Started Jun 10 05:50:12 PM PDT 24
Finished Jun 10 05:50:14 PM PDT 24
Peak memory 196660 kb
Host smart-a58792ed-fa6d-4b2c-a3f3-d95b78a29e2d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2181860544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.2181860544
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2539435294
Short name T899
Test name
Test status
Simulation time 96343194 ps
CPU time 1.54 seconds
Started Jun 10 05:50:18 PM PDT 24
Finished Jun 10 05:50:20 PM PDT 24
Peak memory 196816 kb
Host smart-22268431-3fae-42b1-af69-1b139fc0172f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539435294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2539435294
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2059042564
Short name T882
Test name
Test status
Simulation time 43746016 ps
CPU time 1 seconds
Started Jun 10 05:50:02 PM PDT 24
Finished Jun 10 05:50:03 PM PDT 24
Peak memory 196276 kb
Host smart-6d611e40-5fba-42cc-9d0d-b9b65550ab06
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2059042564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.2059042564
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1763860036
Short name T918
Test name
Test status
Simulation time 205254922 ps
CPU time 0.82 seconds
Started Jun 10 05:49:58 PM PDT 24
Finished Jun 10 05:50:00 PM PDT 24
Peak memory 195564 kb
Host smart-107ae8c5-8bc3-4332-9221-67ecf79ae09c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763860036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1763860036
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.568645609
Short name T904
Test name
Test status
Simulation time 73918241 ps
CPU time 1.14 seconds
Started Jun 10 05:50:15 PM PDT 24
Finished Jun 10 05:50:16 PM PDT 24
Peak memory 196592 kb
Host smart-6008aa47-18dc-42b3-88b0-a758eb5005ca
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=568645609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.568645609
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3718201591
Short name T922
Test name
Test status
Simulation time 326070093 ps
CPU time 1.37 seconds
Started Jun 10 05:50:15 PM PDT 24
Finished Jun 10 05:50:17 PM PDT 24
Peak memory 196832 kb
Host smart-ad28df15-bfaa-4303-8c1a-417039e905c1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718201591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3718201591
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.2611998550
Short name T914
Test name
Test status
Simulation time 64535620 ps
CPU time 1.25 seconds
Started Jun 10 05:50:16 PM PDT 24
Finished Jun 10 05:50:17 PM PDT 24
Peak memory 197280 kb
Host smart-8dceeeff-98f7-4014-b45f-68344e04a805
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2611998550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.2611998550
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2912583714
Short name T869
Test name
Test status
Simulation time 46344522 ps
CPU time 1.24 seconds
Started Jun 10 05:50:15 PM PDT 24
Finished Jun 10 05:50:17 PM PDT 24
Peak memory 196204 kb
Host smart-7eef50bf-39bb-4067-b6b8-185d58f1c707
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912583714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2912583714
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1909056902
Short name T912
Test name
Test status
Simulation time 78782919 ps
CPU time 1.17 seconds
Started Jun 10 05:50:13 PM PDT 24
Finished Jun 10 05:50:15 PM PDT 24
Peak memory 197004 kb
Host smart-54177d0c-a5b0-45e1-a7d5-4a2db7def56f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1909056902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.1909056902
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.555277938
Short name T865
Test name
Test status
Simulation time 36666420 ps
CPU time 1.07 seconds
Started Jun 10 05:50:14 PM PDT 24
Finished Jun 10 05:50:15 PM PDT 24
Peak memory 196116 kb
Host smart-8a0906aa-ef2b-4ca1-8188-f3f8faec33fb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555277938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.555277938
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1655706422
Short name T916
Test name
Test status
Simulation time 254174950 ps
CPU time 1.09 seconds
Started Jun 10 05:50:15 PM PDT 24
Finished Jun 10 05:50:16 PM PDT 24
Peak memory 196980 kb
Host smart-0954309a-9ce5-46c3-8f2e-9de8fb878818
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1655706422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.1655706422
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1458726305
Short name T860
Test name
Test status
Simulation time 58967724 ps
CPU time 1.09 seconds
Started Jun 10 05:50:12 PM PDT 24
Finished Jun 10 05:50:13 PM PDT 24
Peak memory 195920 kb
Host smart-15da09bc-c1c7-4769-a3ae-8dc54bd7d8e3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458726305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1458726305
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3175611851
Short name T934
Test name
Test status
Simulation time 26712890 ps
CPU time 0.81 seconds
Started Jun 10 05:50:15 PM PDT 24
Finished Jun 10 05:50:16 PM PDT 24
Peak memory 195628 kb
Host smart-aa45b1a2-ed3a-48a8-8796-4e7e8d810411
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3175611851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.3175611851
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4223056719
Short name T872
Test name
Test status
Simulation time 173144549 ps
CPU time 1.36 seconds
Started Jun 10 05:50:14 PM PDT 24
Finished Jun 10 05:50:16 PM PDT 24
Peak memory 195924 kb
Host smart-6c0c9de0-b9c3-47a8-a203-e35ce5a76048
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223056719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4223056719
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2695919250
Short name T855
Test name
Test status
Simulation time 420029631 ps
CPU time 1.58 seconds
Started Jun 10 05:50:15 PM PDT 24
Finished Jun 10 05:50:17 PM PDT 24
Peak memory 196972 kb
Host smart-1ef18d25-0ef6-495c-86a1-ad096317cbf6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2695919250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.2695919250
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4249383708
Short name T910
Test name
Test status
Simulation time 103952872 ps
CPU time 1.12 seconds
Started Jun 10 05:50:16 PM PDT 24
Finished Jun 10 05:50:17 PM PDT 24
Peak memory 196744 kb
Host smart-c766f63a-58f0-4fae-856c-d38dc20981f8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249383708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4249383708
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.4188278849
Short name T890
Test name
Test status
Simulation time 68750547 ps
CPU time 1.19 seconds
Started Jun 10 05:50:15 PM PDT 24
Finished Jun 10 05:50:16 PM PDT 24
Peak memory 196792 kb
Host smart-7d682a2d-0a29-4191-8e68-a8c8714732d1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4188278849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.4188278849
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.664508719
Short name T873
Test name
Test status
Simulation time 46847688 ps
CPU time 1 seconds
Started Jun 10 05:50:18 PM PDT 24
Finished Jun 10 05:50:20 PM PDT 24
Peak memory 196800 kb
Host smart-f3b82168-787e-449e-a1dd-6a4dec1de4fa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664508719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.664508719
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2886297431
Short name T913
Test name
Test status
Simulation time 38377216 ps
CPU time 1.24 seconds
Started Jun 10 05:50:11 PM PDT 24
Finished Jun 10 05:50:13 PM PDT 24
Peak memory 198184 kb
Host smart-239cf7dd-c383-46bc-8436-63b475037156
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2886297431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.2886297431
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4214115297
Short name T857
Test name
Test status
Simulation time 34542247 ps
CPU time 1.05 seconds
Started Jun 10 05:50:16 PM PDT 24
Finished Jun 10 05:50:17 PM PDT 24
Peak memory 196756 kb
Host smart-9f919b18-4282-4bb7-bd6c-6689230d2516
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214115297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4214115297
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.2692718142
Short name T938
Test name
Test status
Simulation time 78053264 ps
CPU time 0.9 seconds
Started Jun 10 05:50:17 PM PDT 24
Finished Jun 10 05:50:18 PM PDT 24
Peak memory 196480 kb
Host smart-0548eb53-1588-4f49-b256-62837d3a33a4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2692718142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.2692718142
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3208368375
Short name T881
Test name
Test status
Simulation time 84972148 ps
CPU time 0.95 seconds
Started Jun 10 05:50:20 PM PDT 24
Finished Jun 10 05:50:21 PM PDT 24
Peak memory 196784 kb
Host smart-e9febce1-b168-4227-85ec-30474c5c70bd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208368375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3208368375
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3397461484
Short name T870
Test name
Test status
Simulation time 126877446 ps
CPU time 1.2 seconds
Started Jun 10 05:50:19 PM PDT 24
Finished Jun 10 05:50:21 PM PDT 24
Peak memory 196728 kb
Host smart-b135ac47-cb52-42ed-9cd9-94f422e996c6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3397461484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.3397461484
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3652396011
Short name T897
Test name
Test status
Simulation time 137539325 ps
CPU time 0.94 seconds
Started Jun 10 05:50:18 PM PDT 24
Finished Jun 10 05:50:19 PM PDT 24
Peak memory 197516 kb
Host smart-ae9d5cf9-43c6-43a6-8b6b-569092a170dc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652396011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3652396011
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2079998109
Short name T887
Test name
Test status
Simulation time 268970681 ps
CPU time 1.3 seconds
Started Jun 10 05:49:56 PM PDT 24
Finished Jun 10 05:49:58 PM PDT 24
Peak memory 196984 kb
Host smart-35c1ae7b-bb7d-4164-8162-f6f6bf85f7e8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2079998109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.2079998109
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3206746636
Short name T907
Test name
Test status
Simulation time 172351163 ps
CPU time 1.39 seconds
Started Jun 10 05:50:00 PM PDT 24
Finished Jun 10 05:50:02 PM PDT 24
Peak memory 197168 kb
Host smart-72caf088-4b06-4962-aae3-167288081251
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206746636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3206746636
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.441331197
Short name T926
Test name
Test status
Simulation time 808593383 ps
CPU time 1.03 seconds
Started Jun 10 05:49:58 PM PDT 24
Finished Jun 10 05:49:59 PM PDT 24
Peak memory 196116 kb
Host smart-ac74ccf3-a103-4a52-9cf9-1e1a68b70d88
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=441331197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.441331197
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2934798367
Short name T850
Test name
Test status
Simulation time 131692122 ps
CPU time 1.24 seconds
Started Jun 10 05:49:58 PM PDT 24
Finished Jun 10 05:50:00 PM PDT 24
Peak memory 197076 kb
Host smart-4d4891b0-8e84-4ac9-9591-031a4472a81b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934798367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2934798367
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3392544706
Short name T917
Test name
Test status
Simulation time 78484139 ps
CPU time 0.67 seconds
Started Jun 10 05:50:01 PM PDT 24
Finished Jun 10 05:50:02 PM PDT 24
Peak memory 194592 kb
Host smart-9835d1d9-2f72-4d5f-96ac-bab743922fc6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3392544706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.3392544706
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.98237761
Short name T877
Test name
Test status
Simulation time 53008008 ps
CPU time 1.2 seconds
Started Jun 10 05:49:58 PM PDT 24
Finished Jun 10 05:50:00 PM PDT 24
Peak memory 196772 kb
Host smart-0e39085e-8ed7-470b-a6c3-c90e3e9b3b38
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98237761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.98237761
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.510003171
Short name T927
Test name
Test status
Simulation time 44254061 ps
CPU time 1.41 seconds
Started Jun 10 05:50:03 PM PDT 24
Finished Jun 10 05:50:05 PM PDT 24
Peak memory 198204 kb
Host smart-1077bb15-30d2-4244-b862-d29d818d67c0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=510003171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.510003171
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4140847647
Short name T924
Test name
Test status
Simulation time 55320304 ps
CPU time 1.01 seconds
Started Jun 10 05:50:02 PM PDT 24
Finished Jun 10 05:50:04 PM PDT 24
Peak memory 196932 kb
Host smart-1c7fd210-aab2-4cd8-bc32-676fe4d5f3ea
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140847647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4140847647
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3080426943
Short name T915
Test name
Test status
Simulation time 41864792 ps
CPU time 1.24 seconds
Started Jun 10 05:50:04 PM PDT 24
Finished Jun 10 05:50:05 PM PDT 24
Peak memory 197364 kb
Host smart-d4080eb3-4b73-488e-a27e-1d6e267a5614
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3080426943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.3080426943
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2439459015
Short name T936
Test name
Test status
Simulation time 113824942 ps
CPU time 1.08 seconds
Started Jun 10 05:50:02 PM PDT 24
Finished Jun 10 05:50:03 PM PDT 24
Peak memory 195932 kb
Host smart-a46b27e5-dbce-4420-a4e2-c5de092111ed
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439459015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2439459015
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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