Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3896435	1			T22	1		T23	1		T24	1
all_pins[1]	3896435	1			T22	1		T23	1		T24	1
all_pins[2]	3896435	1			T22	1		T23	1		T24	1
all_pins[3]	3896435	1			T22	1		T23	1		T24	1
all_pins[4]	3896435	1			T22	1		T23	1		T24	1
all_pins[5]	3896435	1			T22	1		T23	1		T24	1
all_pins[6]	3896435	1			T22	1		T23	1		T24	1
all_pins[7]	3896435	1			T22	1		T23	1		T24	1
all_pins[8]	3896435	1			T22	1		T23	1		T24	1
all_pins[9]	3896435	1			T22	1		T23	1		T24	1
all_pins[10]	3896435	1			T22	1		T23	1		T24	1
all_pins[11]	3896435	1			T22	1		T23	1		T24	1
all_pins[12]	3896435	1			T22	1		T23	1		T24	1
all_pins[13]	3896435	1			T22	1		T23	1		T24	1
all_pins[14]	3896435	1			T22	1		T23	1		T24	1
all_pins[15]	3896435	1			T22	1		T23	1		T24	1
all_pins[16]	3896435	1			T22	1		T23	1		T24	1
all_pins[17]	3896435	1			T22	1		T23	1		T24	1
all_pins[18]	3896435	1			T22	1		T23	1		T24	1
all_pins[19]	3896435	1			T22	1		T23	1		T24	1
all_pins[20]	3896435	1			T22	1		T23	1		T24	1
all_pins[21]	3896435	1			T22	1		T23	1		T24	1
all_pins[22]	3896435	1			T22	1		T23	1		T24	1
all_pins[23]	3896435	1			T22	1		T23	1		T24	1
all_pins[24]	3896435	1			T22	1		T23	1		T24	1
all_pins[25]	3896435	1			T22	1		T23	1		T24	1
all_pins[26]	3896435	1			T22	1		T23	1		T24	1
all_pins[27]	3896435	1			T22	1		T23	1		T24	1
all_pins[28]	3896435	1			T22	1		T23	1		T24	1
all_pins[29]	3896435	1			T22	1		T23	1		T24	1
all_pins[30]	3896435	1			T22	1		T23	1		T24	1
all_pins[31]	3896435	1			T22	1		T23	1		T24	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	77434346	1			T22	32		T23	32		T24	32
values[0x1]	47251574	1			T27	978		T28	299		T29	6904
transitions[0x0=>0x1]	28310786	1			T27	601		T28	195		T29	4264
transitions[0x1=>0x0]	28310632	1			T27	601		T28	194		T29	4264

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2421427	1			T22	1		T23	1		T24	1
all_pins[0]	values[0x1]	1475008	1			T27	20		T28	7		T29	230
all_pins[0]	transitions[0x0=>0x1]	912383	1			T27	7		T28	7		T29	134
all_pins[0]	transitions[0x1=>0x0]	917357	1			T27	12		T28	4		T29	170
all_pins[1]	values[0x0]	2420669	1			T22	1		T23	1		T24	1
all_pins[1]	values[0x1]	1475766	1			T27	27		T28	11		T29	189
all_pins[1]	transitions[0x0=>0x1]	882447	1			T27	19		T28	10		T29	120
all_pins[1]	transitions[0x1=>0x0]	881689	1			T27	12		T28	6		T29	161
all_pins[2]	values[0x0]	2421698	1			T22	1		T23	1		T24	1
all_pins[2]	values[0x1]	1474737	1			T27	26		T28	2		T29	192
all_pins[2]	transitions[0x0=>0x1]	882845	1			T27	21		T29	121		T31	171
all_pins[2]	transitions[0x1=>0x0]	883874	1			T27	22		T28	9		T29	118
all_pins[3]	values[0x0]	2418550	1			T22	1		T23	1		T24	1
all_pins[3]	values[0x1]	1477885	1			T27	25		T28	6		T29	241
all_pins[3]	transitions[0x0=>0x1]	886985	1			T27	18		T28	5		T29	170
all_pins[3]	transitions[0x1=>0x0]	883837	1			T27	19		T28	1		T29	121
all_pins[4]	values[0x0]	2422810	1			T22	1		T23	1		T24	1
all_pins[4]	values[0x1]	1473625	1			T27	39		T28	13		T29	214
all_pins[4]	transitions[0x0=>0x1]	881926	1			T27	19		T28	10		T29	99
all_pins[4]	transitions[0x1=>0x0]	886186	1			T27	5		T28	3		T29	126
all_pins[5]	values[0x0]	2416048	1			T22	1		T23	1		T24	1
all_pins[5]	values[0x1]	1480387	1			T27	38		T28	3		T29	171
all_pins[5]	transitions[0x0=>0x1]	888304	1			T27	28		T28	2		T29	100
all_pins[5]	transitions[0x1=>0x0]	881542	1			T27	29		T28	12		T29	143
all_pins[6]	values[0x0]	2419677	1			T22	1		T23	1		T24	1
all_pins[6]	values[0x1]	1476758	1			T27	36		T28	8		T29	182
all_pins[6]	transitions[0x0=>0x1]	882930	1			T27	22		T28	6		T29	128
all_pins[6]	transitions[0x1=>0x0]	886559	1			T27	24		T28	1		T29	117
all_pins[7]	values[0x0]	2419691	1			T22	1		T23	1		T24	1
all_pins[7]	values[0x1]	1476744	1			T27	39		T28	13		T29	219
all_pins[7]	transitions[0x0=>0x1]	881478	1			T27	25		T28	9		T29	136
all_pins[7]	transitions[0x1=>0x0]	881492	1			T27	22		T28	4		T29	99
all_pins[8]	values[0x0]	2418174	1			T22	1		T23	1		T24	1
all_pins[8]	values[0x1]	1478261	1			T27	32		T28	11		T29	183
all_pins[8]	transitions[0x0=>0x1]	885382	1			T27	23		T28	2		T29	123
all_pins[8]	transitions[0x1=>0x0]	883865	1			T27	30		T28	4		T29	159
all_pins[9]	values[0x0]	2417169	1			T22	1		T23	1		T24	1
all_pins[9]	values[0x1]	1479266	1			T27	32		T28	14		T29	271
all_pins[9]	transitions[0x0=>0x1]	885706	1			T27	18		T28	9		T29	204
all_pins[9]	transitions[0x1=>0x0]	884701	1			T27	18		T28	6		T29	116
all_pins[10]	values[0x0]	2419395	1			T22	1		T23	1		T24	1
all_pins[10]	values[0x1]	1477040	1			T27	39		T28	9		T29	228
all_pins[10]	transitions[0x0=>0x1]	884814	1			T27	25		T28	6		T29	120
all_pins[10]	transitions[0x1=>0x0]	887040	1			T27	18		T28	11		T29	163
all_pins[11]	values[0x0]	2420037	1			T22	1		T23	1		T24	1
all_pins[11]	values[0x1]	1476398	1			T27	39		T28	15		T29	244
all_pins[11]	transitions[0x0=>0x1]	882915	1			T27	28		T28	14		T29	137
all_pins[11]	transitions[0x1=>0x0]	883557	1			T27	28		T28	8		T29	121
all_pins[12]	values[0x0]	2421644	1			T22	1		T23	1		T24	1
all_pins[12]	values[0x1]	1474791	1			T27	46		T28	9		T29	226
all_pins[12]	transitions[0x0=>0x1]	886739	1			T27	20		T28	7		T29	126
all_pins[12]	transitions[0x1=>0x0]	888346	1			T27	13		T28	13		T29	144
all_pins[13]	values[0x0]	2418947	1			T22	1		T23	1		T24	1
all_pins[13]	values[0x1]	1477488	1			T27	20		T28	15		T29	241
all_pins[13]	transitions[0x0=>0x1]	884784	1			T27	8		T28	6		T29	125
all_pins[13]	transitions[0x1=>0x0]	882087	1			T27	34		T29	110		T31	140
all_pins[14]	values[0x0]	2412664	1			T22	1		T23	1		T24	1
all_pins[14]	values[0x1]	1483771	1			T27	15		T28	5		T29	219
all_pins[14]	transitions[0x0=>0x1]	887913	1			T27	6		T29	137		T31	120
all_pins[14]	transitions[0x1=>0x0]	881630	1			T27	11		T28	10		T29	159
all_pins[15]	values[0x0]	2422206	1			T22	1		T23	1		T24	1
all_pins[15]	values[0x1]	1474229	1			T27	32		T28	4		T29	216
all_pins[15]	transitions[0x0=>0x1]	879269	1			T27	23		T28	4		T29	125
all_pins[15]	transitions[0x1=>0x0]	888811	1			T27	6		T28	5		T29	128
all_pins[16]	values[0x0]	2423405	1			T22	1		T23	1		T24	1
all_pins[16]	values[0x1]	1473030	1			T27	34		T28	4		T29	176
all_pins[16]	transitions[0x0=>0x1]	881521	1			T27	14		T28	4		T29	119
all_pins[16]	transitions[0x1=>0x0]	882720	1			T27	12		T28	4		T29	159
all_pins[17]	values[0x0]	2422656	1			T22	1		T23	1		T24	1
all_pins[17]	values[0x1]	1473779	1			T27	31		T28	16		T29	181
all_pins[17]	transitions[0x0=>0x1]	884984	1			T27	21		T28	16		T29	136
all_pins[17]	transitions[0x1=>0x0]	884235	1			T27	24		T28	4		T29	131
all_pins[18]	values[0x0]	2422432	1			T22	1		T23	1		T24	1
all_pins[18]	values[0x1]	1474003	1			T27	55		T28	2		T29	195
all_pins[18]	transitions[0x0=>0x1]	883156	1			T27	31		T28	2		T29	125
all_pins[18]	transitions[0x1=>0x0]	882932	1			T27	7		T28	16		T29	111
all_pins[19]	values[0x0]	2423474	1			T22	1		T23	1		T24	1
all_pins[19]	values[0x1]	1472961	1			T27	24		T28	8		T29	228
all_pins[19]	transitions[0x0=>0x1]	884053	1			T27	6		T28	8		T29	165
all_pins[19]	transitions[0x1=>0x0]	885095	1			T27	37		T28	2		T29	132
all_pins[20]	values[0x0]	2418703	1			T22	1		T23	1		T24	1
all_pins[20]	values[0x1]	1477732	1			T27	34		T28	7		T29	177
all_pins[20]	transitions[0x0=>0x1]	884185	1			T27	17		T28	2		T29	107
all_pins[20]	transitions[0x1=>0x0]	879414	1			T27	7		T28	3		T29	158
all_pins[21]	values[0x0]	2421986	1			T22	1		T23	1		T24	1
all_pins[21]	values[0x1]	1474449	1			T27	41		T28	7		T29	171
all_pins[21]	transitions[0x0=>0x1]	882911	1			T27	19		T28	5		T29	123
all_pins[21]	transitions[0x1=>0x0]	886194	1			T27	12		T28	5		T29	129
all_pins[22]	values[0x0]	2418141	1			T22	1		T23	1		T24	1
all_pins[22]	values[0x1]	1478294	1			T27	16		T28	7		T29	164
all_pins[22]	transitions[0x0=>0x1]	883064	1			T27	10		T28	6		T29	112
all_pins[22]	transitions[0x1=>0x0]	879219	1			T27	35		T28	6		T29	119
all_pins[23]	values[0x0]	2413793	1			T22	1		T23	1		T24	1
all_pins[23]	values[0x1]	1482642	1			T27	19		T28	10		T29	229
all_pins[23]	transitions[0x0=>0x1]	887221	1			T27	13		T28	5		T29	152
all_pins[23]	transitions[0x1=>0x0]	882873	1			T27	10		T28	2		T29	87
all_pins[24]	values[0x0]	2424367	1			T22	1		T23	1		T24	1
all_pins[24]	values[0x1]	1472068	1			T27	25		T28	18		T29	247
all_pins[24]	transitions[0x0=>0x1]	878752	1			T27	20		T28	8		T29	145
all_pins[24]	transitions[0x1=>0x0]	889326	1			T27	14		T29	127		T31	229
all_pins[25]	values[0x0]	2417176	1			T22	1		T23	1		T24	1
all_pins[25]	values[0x1]	1479259	1			T27	36		T28	15		T29	231
all_pins[25]	transitions[0x0=>0x1]	888369	1			T27	28		T28	7		T29	137
all_pins[25]	transitions[0x1=>0x0]	881178	1			T27	17		T28	10		T29	153
all_pins[26]	values[0x0]	2421379	1			T22	1		T23	1		T24	1
all_pins[26]	values[0x1]	1475056	1			T27	25		T28	13		T29	245
all_pins[26]	transitions[0x0=>0x1]	881012	1			T27	14		T28	7		T29	145
all_pins[26]	transitions[0x1=>0x0]	885215	1			T27	25		T28	9		T29	131
all_pins[27]	values[0x0]	2421157	1			T22	1		T23	1		T24	1
all_pins[27]	values[0x1]	1475278	1			T27	28		T28	14		T29	238
all_pins[27]	transitions[0x0=>0x1]	882187	1			T27	19		T28	6		T29	138
all_pins[27]	transitions[0x1=>0x0]	881965	1			T27	16		T28	5		T29	145
all_pins[28]	values[0x0]	2419127	1			T22	1		T23	1		T24	1
all_pins[28]	values[0x1]	1477308	1			T27	18		T28	7		T29	238
all_pins[28]	transitions[0x0=>0x1]	882930	1			T27	13		T28	4		T29	138
all_pins[28]	transitions[0x1=>0x0]	880900	1			T27	23		T28	11		T29	138
all_pins[29]	values[0x0]	2422531	1			T22	1		T23	1		T24	1
all_pins[29]	values[0x1]	1473904	1			T27	19		T28	5		T29	260
all_pins[29]	transitions[0x0=>0x1]	880956	1			T27	15		T28	5		T29	143
all_pins[29]	transitions[0x1=>0x0]	884360	1			T27	14		T28	7		T29	121
all_pins[30]	values[0x0]	2416914	1			T22	1		T23	1		T24	1
all_pins[30]	values[0x1]	1479521	1			T27	43		T28	16		T29	192
all_pins[30]	transitions[0x0=>0x1]	884010	1			T27	35		T28	13		T29	96
all_pins[30]	transitions[0x1=>0x0]	878393	1			T27	11		T28	2		T29	164
all_pins[31]	values[0x0]	2416299	1			T22	1		T23	1		T24	1
all_pins[31]	values[0x1]	1480136	1			T27	25		T28	5		T29	266
all_pins[31]	transitions[0x0=>0x1]	884655	1			T27	16		T29	178		T31	165
all_pins[31]	transitions[0x1=>0x0]	884040	1			T27	34		T28	11		T29	104