Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	13183104	1			T22	202		T23	190		T24	136
all_values[1]	13183104	1			T22	202		T23	190		T24	136
all_values[2]	13183104	1			T22	202		T23	190		T24	136
all_values[3]	13183104	1			T22	202		T23	190		T24	136
all_values[4]	13183104	1			T22	202		T23	190		T24	136
all_values[5]	13183104	1			T22	202		T23	190		T24	136
all_values[6]	13183104	1			T22	202		T23	190		T24	136
all_values[7]	13183104	1			T22	202		T23	190		T24	136
all_values[8]	13183104	1			T22	202		T23	190		T24	136
all_values[9]	13183104	1			T22	202		T23	190		T24	136
all_values[10]	13183104	1			T22	202		T23	190		T24	136
all_values[11]	13183104	1			T22	202		T23	190		T24	136
all_values[12]	13183104	1			T22	202		T23	190		T24	136
all_values[13]	13183104	1			T22	202		T23	190		T24	136
all_values[14]	13183104	1			T22	202		T23	190		T24	136
all_values[15]	13183104	1			T22	202		T23	190		T24	136
all_values[16]	13183104	1			T22	202		T23	190		T24	136
all_values[17]	13183104	1			T22	202		T23	190		T24	136
all_values[18]	13183104	1			T22	202		T23	190		T24	136
all_values[19]	13183104	1			T22	202		T23	190		T24	136
all_values[20]	13183104	1			T22	202		T23	190		T24	136
all_values[21]	13183104	1			T22	202		T23	190		T24	136
all_values[22]	13183104	1			T22	202		T23	190		T24	136
all_values[23]	13183104	1			T22	202		T23	190		T24	136
all_values[24]	13183104	1			T22	202		T23	190		T24	136
all_values[25]	13183104	1			T22	202		T23	190		T24	136
all_values[26]	13183104	1			T22	202		T23	190		T24	136
all_values[27]	13183104	1			T22	202		T23	190		T24	136
all_values[28]	13183104	1			T22	202		T23	190		T24	136
all_values[29]	13183104	1			T22	202		T23	190		T24	136
all_values[30]	13183104	1			T22	202		T23	190		T24	136
all_values[31]	13183104	1			T22	202		T23	190		T24	136

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

244894261

1

T22

6464

T23

6080

T24

4352

auto[1]

176965067

1

T27

2266

T28

935

T29

23174

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

102010722

1

T22

6464

T23

6080

T24

4352

auto[1]

319848606

1

T27

3690

T28

1253

T29

39801

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

417294598

1

T22

6464

T23

6080

T24

4352

auto[1]

4564730

1

T28

121

T29

1679

T32

32646

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2646235	1			T22	202		T23	190		T24	136
all_values[0]	auto[0]	auto[0]	auto[1]	4957502	1			T27	49		T28	18		T29	524
all_values[0]	auto[0]	auto[1]	auto[0]	536752	1			T27	29		T28	8		T29	82
all_values[0]	auto[0]	auto[1]	auto[1]	4900089	1			T27	36		T28	12		T29	679
all_values[0]	auto[1]	auto[0]	auto[1]	71346	1			T28	3		T29	20		T32	551
all_values[0]	auto[1]	auto[1]	auto[1]	71180	1			T28	3		T29	34		T32	482
all_values[1]	auto[0]	auto[0]	auto[0]	2650515	1			T22	202		T23	190		T24	136
all_values[1]	auto[0]	auto[0]	auto[1]	4932633	1			T27	66		T28	17		T29	641
all_values[1]	auto[0]	auto[1]	auto[0]	533501	1			T27	1		T28	23		T29	59
all_values[1]	auto[0]	auto[1]	auto[1]	4923609	1			T27	61		T28	19		T29	580
all_values[1]	auto[1]	auto[0]	auto[1]	71711	1			T29	22		T32	530		T34	1
all_values[1]	auto[1]	auto[1]	auto[1]	71135	1			T28	2		T29	31		T32	472
all_values[2]	auto[0]	auto[0]	auto[0]	2650824	1			T22	202		T23	190		T24	136
all_values[2]	auto[0]	auto[0]	auto[1]	4954505	1			T27	72		T28	20		T29	664
all_values[2]	auto[0]	auto[1]	auto[0]	533745	1			T27	5		T28	15		T29	100
all_values[2]	auto[0]	auto[1]	auto[1]	4901373	1			T27	60		T28	3		T29	497
all_values[2]	auto[1]	auto[0]	auto[1]	71614	1			T28	3		T29	28		T32	492
all_values[2]	auto[1]	auto[1]	auto[1]	71043	1			T28	1		T29	25		T32	551
all_values[3]	auto[0]	auto[0]	auto[0]	2647573	1			T22	202		T23	190		T24	136
all_values[3]	auto[0]	auto[0]	auto[1]	4917445	1			T27	66		T28	25		T29	603
all_values[3]	auto[0]	auto[1]	auto[0]	531287	1			T27	16		T28	12		T29	73
all_values[3]	auto[0]	auto[1]	auto[1]	4944602	1			T27	52		T28	14		T29	637
all_values[3]	auto[1]	auto[0]	auto[1]	71204	1			T28	4		T29	21		T32	472
all_values[3]	auto[1]	auto[1]	auto[1]	70993	1			T28	1		T29	36		T32	541
all_values[4]	auto[0]	auto[0]	auto[0]	2656224	1			T22	202		T23	190		T24	136
all_values[4]	auto[0]	auto[0]	auto[1]	4933357	1			T27	20		T28	21		T29	521
all_values[4]	auto[0]	auto[1]	auto[0]	538286	1			T27	15		T28	10		T29	131
all_values[4]	auto[0]	auto[1]	auto[1]	4912704	1			T27	76		T28	19		T29	606
all_values[4]	auto[1]	auto[0]	auto[1]	71341	1			T28	3		T29	29		T32	505
all_values[4]	auto[1]	auto[1]	auto[1]	71192	1			T28	1		T29	33		T32	502
all_values[5]	auto[0]	auto[0]	auto[0]	2656592	1			T22	202		T23	190		T24	136
all_values[5]	auto[0]	auto[0]	auto[1]	4957126	1			T27	57		T28	21		T29	604
all_values[5]	auto[0]	auto[1]	auto[0]	535299	1			T27	8		T28	8		T29	164
all_values[5]	auto[0]	auto[1]	auto[1]	4891220	1			T27	69		T28	9		T29	475
all_values[5]	auto[1]	auto[0]	auto[1]	71640	1			T28	4		T29	30		T32	530
all_values[5]	auto[1]	auto[1]	auto[1]	71227	1			T28	1		T29	21		T32	478
all_values[6]	auto[0]	auto[0]	auto[0]	2653500	1			T22	202		T23	190		T24	136
all_values[6]	auto[0]	auto[0]	auto[1]	4911127	1			T27	47		T28	14		T29	617
all_values[6]	auto[0]	auto[1]	auto[0]	537451	1			T27	13		T28	12		T29	104
all_values[6]	auto[0]	auto[1]	auto[1]	4938361	1			T27	70		T28	19		T29	517
all_values[6]	auto[1]	auto[0]	auto[1]	71183	1			T28	1		T29	27		T32	512
all_values[6]	auto[1]	auto[1]	auto[1]	71482	1			T28	2		T29	18		T32	465
all_values[7]	auto[0]	auto[0]	auto[0]	2654360	1			T22	202		T23	190		T24	136
all_values[7]	auto[0]	auto[0]	auto[1]	4904799	1			T27	76		T28	12		T29	570
all_values[7]	auto[0]	auto[1]	auto[0]	535624	1			T28	15		T29	111		T31	65
all_values[7]	auto[0]	auto[1]	auto[1]	4945957	1			T27	59		T28	24		T29	602
all_values[7]	auto[1]	auto[0]	auto[1]	71715	1			T28	1		T29	23		T32	518
all_values[7]	auto[1]	auto[1]	auto[1]	70649	1			T28	3		T29	23		T32	497
all_values[8]	auto[0]	auto[0]	auto[0]	2645779	1			T22	202		T23	190		T24	136
all_values[8]	auto[0]	auto[0]	auto[1]	4922689	1			T27	57		T28	11		T29	696
all_values[8]	auto[0]	auto[1]	auto[0]	535829	1			T27	14		T28	12		T29	101
all_values[8]	auto[0]	auto[1]	auto[1]	4936430	1			T27	62		T28	21		T29	482
all_values[8]	auto[1]	auto[0]	auto[1]	71703	1			T28	3		T29	31		T32	557
all_values[8]	auto[1]	auto[1]	auto[1]	70674	1			T28	1		T29	23		T32	499
all_values[9]	auto[0]	auto[0]	auto[0]	2649564	1			T22	202		T23	190		T24	136
all_values[9]	auto[0]	auto[0]	auto[1]	4903747	1			T27	64		T28	21		T29	489
all_values[9]	auto[0]	auto[1]	auto[0]	537430	1			T27	7		T28	4		T29	70
all_values[9]	auto[0]	auto[1]	auto[1]	4949277	1			T27	69		T28	21		T29	702
all_values[9]	auto[1]	auto[0]	auto[1]	71927	1			T28	1		T29	20		T32	474
all_values[9]	auto[1]	auto[1]	auto[1]	71159	1			T28	1		T29	31		T32	558
all_values[10]	auto[0]	auto[0]	auto[0]	2656640	1			T22	202		T23	190		T24	136
all_values[10]	auto[0]	auto[0]	auto[1]	4934788	1			T27	59		T28	17		T29	482
all_values[10]	auto[0]	auto[1]	auto[0]	533143	1			T27	5		T28	19		T29	119
all_values[10]	auto[0]	auto[1]	auto[1]	4915437	1			T27	64		T28	10		T29	666
all_values[10]	auto[1]	auto[0]	auto[1]	72228	1			T28	1		T29	19		T32	532
all_values[10]	auto[1]	auto[1]	auto[1]	70868	1			T28	1		T29	35		T32	507
all_values[11]	auto[0]	auto[0]	auto[0]	2646716	1			T22	202		T23	190		T24	136
all_values[11]	auto[0]	auto[0]	auto[1]	4928535	1			T27	46		T28	15		T29	515
all_values[11]	auto[0]	auto[1]	auto[0]	532645	1			T27	7		T28	4		T29	104
all_values[11]	auto[0]	auto[1]	auto[1]	4932223	1			T27	75		T28	30		T29	642
all_values[11]	auto[1]	auto[0]	auto[1]	71513	1			T28	2		T29	26		T32	527
all_values[11]	auto[1]	auto[1]	auto[1]	71472	1			T28	2		T29	34		T32	514
all_values[12]	auto[0]	auto[0]	auto[0]	2651982	1			T22	202		T23	190		T24	136
all_values[12]	auto[0]	auto[0]	auto[1]	4946336	1			T27	36		T28	36		T29	591
all_values[12]	auto[0]	auto[1]	auto[0]	531844	1			T27	8		T29	116		T31	122
all_values[12]	auto[0]	auto[1]	auto[1]	4910202	1			T27	93		T28	13		T29	630
all_values[12]	auto[1]	auto[0]	auto[1]	71481	1			T28	4		T29	21		T32	525
all_values[12]	auto[1]	auto[1]	auto[1]	71259	1			T28	2		T29	24		T32	514
all_values[13]	auto[0]	auto[0]	auto[0]	2658211	1			T22	202		T23	190		T24	136
all_values[13]	auto[0]	auto[0]	auto[1]	4935683	1			T27	61		T28	19		T29	660
all_values[13]	auto[0]	auto[1]	auto[0]	534912	1			T27	29		T28	12		T29	34
all_values[13]	auto[0]	auto[1]	auto[1]	4911645	1			T27	49		T28	22		T29	606
all_values[13]	auto[1]	auto[0]	auto[1]	71395	1			T28	1		T29	30		T32	461
all_values[13]	auto[1]	auto[1]	auto[1]	71258	1			T28	3		T29	22		T32	542
all_values[14]	auto[0]	auto[0]	auto[0]	2652764	1			T22	202		T23	190		T24	136
all_values[14]	auto[0]	auto[0]	auto[1]	4907726	1			T27	93		T28	37		T29	548
all_values[14]	auto[0]	auto[1]	auto[0]	541651	1			T27	9		T28	7		T29	72
all_values[14]	auto[0]	auto[1]	auto[1]	4938584	1			T27	29		T28	9		T29	663
all_values[14]	auto[1]	auto[0]	auto[1]	71277	1			T28	3		T29	28		T32	523
all_values[14]	auto[1]	auto[1]	auto[1]	71102	1			T28	2		T29	24		T32	511
all_values[15]	auto[0]	auto[0]	auto[0]	2656698	1			T22	202		T23	190		T24	136
all_values[15]	auto[0]	auto[0]	auto[1]	4925607	1			T27	44		T28	15		T29	631
all_values[15]	auto[0]	auto[1]	auto[0]	536666	1			T27	2		T28	14		T29	79
all_values[15]	auto[0]	auto[1]	auto[1]	4921459	1			T27	70		T28	10		T29	592
all_values[15]	auto[1]	auto[0]	auto[1]	71023	1			T28	3		T29	37		T32	528
all_values[15]	auto[1]	auto[1]	auto[1]	71651	1			T28	1		T29	23		T32	501
all_values[16]	auto[0]	auto[0]	auto[0]	2649859	1			T22	202		T23	190		T24	136
all_values[16]	auto[0]	auto[0]	auto[1]	4952297	1			T27	51		T28	41		T29	646
all_values[16]	auto[0]	auto[1]	auto[0]	530794	1			T27	10		T28	7		T29	99
all_values[16]	auto[0]	auto[1]	auto[1]	4907549	1			T27	61		T28	4		T29	511
all_values[16]	auto[1]	auto[0]	auto[1]	71780	1			T28	1		T29	23		T32	447
all_values[16]	auto[1]	auto[1]	auto[1]	70825	1			T28	1		T29	28		T32	577
all_values[17]	auto[0]	auto[0]	auto[0]	2652623	1			T22	202		T23	190		T24	136
all_values[17]	auto[0]	auto[0]	auto[1]	4931412	1			T27	73		T28	17		T29	642
all_values[17]	auto[0]	auto[1]	auto[0]	530792	1			T27	5		T28	3		T29	151
all_values[17]	auto[0]	auto[1]	auto[1]	4925758	1			T27	58		T28	28		T29	500
all_values[17]	auto[1]	auto[0]	auto[1]	71694	1			T28	3		T29	34		T32	585
all_values[17]	auto[1]	auto[1]	auto[1]	70825	1			T28	2		T29	18		T32	507
all_values[18]	auto[0]	auto[0]	auto[0]	2660329	1			T22	202		T23	190		T24	136
all_values[18]	auto[0]	auto[0]	auto[1]	4917615	1			T27	46		T28	28		T29	696
all_values[18]	auto[0]	auto[1]	auto[0]	536321	1			T27	18		T28	5		T29	65
all_values[18]	auto[0]	auto[1]	auto[1]	4926176	1			T27	78		T28	2		T29	534
all_values[18]	auto[1]	auto[0]	auto[1]	71437	1			T28	3		T29	28		T32	515
all_values[18]	auto[1]	auto[1]	auto[1]	71226	1			T29	21		T32	501		T33	866
all_values[19]	auto[0]	auto[0]	auto[0]	2656654	1			T22	202		T23	190		T24	136
all_values[19]	auto[0]	auto[0]	auto[1]	4932826	1			T27	24		T28	23		T29	631
all_values[19]	auto[0]	auto[1]	auto[0]	535455	1			T27	24		T28	4		T29	60
all_values[19]	auto[0]	auto[1]	auto[1]	4915402	1			T27	50		T28	15		T29	631
all_values[19]	auto[1]	auto[0]	auto[1]	72074	1			T28	4		T29	31		T32	519
all_values[19]	auto[1]	auto[1]	auto[1]	70693	1			T28	2		T29	22		T32	488
all_values[20]	auto[0]	auto[0]	auto[0]	2648514	1			T22	202		T23	190		T24	136
all_values[20]	auto[0]	auto[0]	auto[1]	4925111	1			T27	24		T28	21		T29	685
all_values[20]	auto[0]	auto[1]	auto[0]	534206	1			T27	36		T29	54		T31	97
all_values[20]	auto[0]	auto[1]	auto[1]	4932468	1			T27	55		T28	16		T29	509
all_values[20]	auto[1]	auto[0]	auto[1]	71605	1			T28	3		T29	32		T32	530
all_values[20]	auto[1]	auto[1]	auto[1]	71200	1			T28	1		T29	24		T32	501
all_values[21]	auto[0]	auto[0]	auto[0]	2664158	1			T22	202		T23	190		T24	136
all_values[21]	auto[0]	auto[0]	auto[1]	4949475	1			T27	37		T28	18		T29	659
all_values[21]	auto[0]	auto[1]	auto[0]	530464	1			T27	16		T28	29		T29	91
all_values[21]	auto[0]	auto[1]	auto[1]	4896126	1			T27	73		T28	9		T29	508
all_values[21]	auto[1]	auto[0]	auto[1]	71289	1			T28	2		T29	28		T32	522
all_values[21]	auto[1]	auto[1]	auto[1]	71592	1			T28	1		T29	23		T32	547
all_values[22]	auto[0]	auto[0]	auto[0]	2647860	1			T22	202		T23	190		T24	136
all_values[22]	auto[0]	auto[0]	auto[1]	4902862	1			T27	78		T28	14		T29	642
all_values[22]	auto[0]	auto[1]	auto[0]	532292	1			T27	13		T28	23		T29	138
all_values[22]	auto[0]	auto[1]	auto[1]	4957759	1			T27	41		T28	11		T29	493
all_values[22]	auto[1]	auto[0]	auto[1]	71327	1			T28	1		T29	30		T32	540
all_values[22]	auto[1]	auto[1]	auto[1]	71004	1			T28	1		T29	24		T32	474
all_values[23]	auto[0]	auto[0]	auto[0]	2655911	1			T22	202		T23	190		T24	136
all_values[23]	auto[0]	auto[0]	auto[1]	4930667	1			T27	48		T28	9		T29	576
all_values[23]	auto[0]	auto[1]	auto[0]	530172	1			T27	12		T28	25		T29	58
all_values[23]	auto[0]	auto[1]	auto[1]	4924232	1			T27	49		T28	18		T29	642
all_values[23]	auto[1]	auto[0]	auto[1]	71127	1			T28	2		T29	23		T32	489
all_values[23]	auto[1]	auto[1]	auto[1]	70995	1			T28	1		T29	28		T32	482
all_values[24]	auto[0]	auto[0]	auto[0]	2657398	1			T22	202		T23	190		T24	136
all_values[24]	auto[0]	auto[0]	auto[1]	4944663	1			T27	63		T28	6		T29	524
all_values[24]	auto[0]	auto[1]	auto[0]	537394	1			T27	8		T28	23		T29	91
all_values[24]	auto[0]	auto[1]	auto[1]	4900974	1			T27	46		T28	28		T29	703
all_values[24]	auto[1]	auto[0]	auto[1]	72232	1			T28	1		T29	23		T32	489
all_values[24]	auto[1]	auto[1]	auto[1]	70443	1			T28	3		T29	28		T32	538
all_values[25]	auto[0]	auto[0]	auto[0]	2644026	1			T22	202		T23	190		T24	136
all_values[25]	auto[0]	auto[0]	auto[1]	4946763	1			T27	64		T28	9		T29	570
all_values[25]	auto[0]	auto[1]	auto[0]	539336	1			T27	6		T28	20		T29	112
all_values[25]	auto[0]	auto[1]	auto[1]	4910293	1			T27	70		T28	21		T29	665
all_values[25]	auto[1]	auto[0]	auto[1]	71622	1			T28	1		T29	25		T32	526
all_values[25]	auto[1]	auto[1]	auto[1]	71064	1			T28	1		T29	29		T32	490
all_values[26]	auto[0]	auto[0]	auto[0]	2654734	1			T22	202		T23	190		T24	136
all_values[26]	auto[0]	auto[0]	auto[1]	4919321	1			T27	88		T28	21		T29	550
all_values[26]	auto[0]	auto[1]	auto[0]	539610	1			T28	19		T29	98		T31	149
all_values[26]	auto[0]	auto[1]	auto[1]	4927132	1			T27	43		T28	17		T29	698
all_values[26]	auto[1]	auto[0]	auto[1]	71345	1			T28	1		T29	20		T32	478
all_values[26]	auto[1]	auto[1]	auto[1]	70962	1			T28	3		T29	29		T32	504
all_values[27]	auto[0]	auto[0]	auto[0]	2653967	1			T22	202		T23	190		T24	136
all_values[27]	auto[0]	auto[0]	auto[1]	4929172	1			T27	77		T28	20		T29	600
all_values[27]	auto[0]	auto[1]	auto[0]	539950	1			T27	6		T28	4		T29	89
all_values[27]	auto[0]	auto[1]	auto[1]	4917495	1			T27	46		T28	23		T29	633
all_values[27]	auto[1]	auto[0]	auto[1]	71803	1			T28	2		T29	24		T32	526
all_values[27]	auto[1]	auto[1]	auto[1]	70717	1			T28	2		T29	28		T32	469
all_values[28]	auto[0]	auto[0]	auto[0]	2647359	1			T22	202		T23	190		T24	136
all_values[28]	auto[0]	auto[0]	auto[1]	4926069	1			T27	46		T28	23		T29	627
all_values[28]	auto[0]	auto[1]	auto[0]	538838	1			T27	31		T28	12		T29	128
all_values[28]	auto[0]	auto[1]	auto[1]	4928287	1			T27	45		T28	12		T29	593
all_values[28]	auto[1]	auto[0]	auto[1]	71515	1			T28	3		T29	22		T32	497
all_values[28]	auto[1]	auto[1]	auto[1]	71036	1			T28	1		T29	25		T32	500
all_values[29]	auto[0]	auto[0]	auto[0]	2655845	1			T22	202		T23	190		T24	136
all_values[29]	auto[0]	auto[0]	auto[1]	4933865	1			T27	83		T28	26		T29	424
all_values[29]	auto[0]	auto[1]	auto[0]	533113	1			T27	9		T28	3		T29	88
all_values[29]	auto[0]	auto[1]	auto[1]	4917388	1			T27	41		T28	12		T29	757
all_values[29]	auto[1]	auto[0]	auto[1]	71937	1			T28	1		T29	17		T32	482
all_values[29]	auto[1]	auto[1]	auto[1]	70956	1			T28	2		T29	32		T32	519
all_values[30]	auto[0]	auto[0]	auto[0]	2651280	1			T22	202		T23	190		T24	136
all_values[30]	auto[0]	auto[0]	auto[1]	4906950	1			T27	44		T28	6		T29	517
all_values[30]	auto[0]	auto[1]	auto[0]	534031	1			T27	15		T28	19		T29	183
all_values[30]	auto[0]	auto[1]	auto[1]	4947846	1			T27	73		T28	23		T29	571
all_values[30]	auto[1]	auto[0]	auto[1]	71397	1			T28	2		T29	20		T32	528
all_values[30]	auto[1]	auto[1]	auto[1]	71600	1			T28	3		T29	30		T32	473
all_values[31]	auto[0]	auto[0]	auto[0]	2651908	1			T22	202		T23	190		T24	136
all_values[31]	auto[0]	auto[0]	auto[1]	4894547	1			T27	55		T28	26		T29	539
all_values[31]	auto[0]	auto[1]	auto[0]	535287	1			T27	13		T28	8		T29	55
all_values[31]	auto[0]	auto[1]	auto[1]	4958599	1			T27	53		T28	11		T29	714
all_values[31]	auto[1]	auto[0]	auto[1]	71954	1			T28	3		T29	30		T32	489
all_values[31]	auto[1]	auto[1]	auto[1]	70809	1			T29	31		T32	543		T33	869

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal