Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[1]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[2]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[3]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[4]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[5]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[6]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[7]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[8]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[9]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[10]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[11]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[12]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[13]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[14]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[15]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[16]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[17]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[18]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[19]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[20]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[21]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[22]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[23]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[24]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[25]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[26]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[27]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[28]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[29]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[30]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[31]	13006947	1			T22	393		T23	250		T24	244

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

240722322

1

T22

2849

T23

4986

T24

1464

auto[1]

175499982

1

T22

9727

T23

3014

T24

6344

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

334272856

1

T22

9858

T23

6166

T24

7078

auto[1]

81949448

1

T22

2718

T23

1834

T24

730

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

310147101

1

T22

6652

T23

6044

T24

4436

auto[1]

106075203

1

T22

5924

T23

1956

T24

3372

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4712183	1			T22	27		T23	112		T24	22
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3689778	1			T22	147		T23	60		T24	122
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1287999	1			T22	35		T23	34		T24	14
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1517841	1			T22	24		T23	26		T24	14
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	521211	1			T22	115		T24	60		T28	17
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1277935	1			T22	45		T23	18		T24	12
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4716012	1			T22	21		T23	95		T24	22
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3690817	1			T22	170		T23	66		T24	137
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1292930	1			T22	31		T23	29		T24	12
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1513416	1			T22	31		T23	36		T24	12
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	520448	1			T22	122		T24	59		T28	17
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1273324	1			T22	18		T23	24		T24	2
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4716419	1			T22	16		T23	90		T24	15
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3691051	1			T22	139		T23	64		T24	99
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1291172	1			T22	60		T23	28		T24	16
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1514766	1			T22	20		T23	28		T24	14
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	519622	1			T22	129		T24	83		T28	4
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1273917	1			T22	29		T23	40		T24	17
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4710348	1			T22	14		T23	91		T24	17
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3692845	1			T22	163		T23	66		T24	100
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1289951	1			T22	60		T23	25		T24	6
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1517839	1			T22	20		T23	28		T24	19
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	520462	1			T22	112		T24	88		T28	14
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1275502	1			T22	24		T23	40		T24	14
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4718410	1			T22	20		T23	95		T24	23
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3688177	1			T22	132		T23	70		T24	102
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1292961	1			T22	55		T23	18		T24	20
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1515665	1			T22	26		T23	40		T24	13
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	520505	1			T22	116		T24	66		T28	23
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1271229	1			T22	44		T23	27		T24	20
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4716269	1			T22	17		T23	102		T24	10
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3689172	1			T22	125		T23	63		T24	95
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1286265	1			T22	35		T23	22		T24	9
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1515314	1			T22	27		T23	40		T24	15
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	521390	1			T22	158		T24	103		T28	22
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1278537	1			T22	31		T23	23		T24	12
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4704574	1			T22	21		T23	93		T24	33
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3697667	1			T22	159		T23	68		T24	156
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1290666	1			T22	22		T23	26		T24	27
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1512676	1			T22	16		T23	25		T24	7
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	525065	1			T22	140		T24	19		T28	27
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1276299	1			T22	35		T23	38		T24	2
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4731193	1			T22	20		T23	98		T24	21
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3678075	1			T22	121		T23	66		T24	132
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1284984	1			T22	41		T23	30		T24	8
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1513389	1			T22	21		T23	30		T24	14
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	523475	1			T22	133		T24	65		T28	19
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1275831	1			T22	57		T23	26		T24	4
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4706555	1			T22	37		T23	114		T24	16
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3692435	1			T22	138		T23	61		T24	121
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1283627	1			T22	76		T23	28		T24	10
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1520465	1			T22	8		T23	26		T24	17
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	520943	1			T22	107		T24	74		T28	15
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1282922	1			T22	27		T23	21		T24	6
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4722229	1			T22	24		T23	101		T24	5
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3681842	1			T22	130		T23	56		T24	53
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1286119	1			T22	49		T23	17		T24	5
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1518415	1			T22	15		T23	48		T24	31
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	520217	1			T22	125		T24	132		T28	22
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1278125	1			T22	50		T23	28		T24	18
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4718793	1			T22	28		T23	106		T24	18
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3682837	1			T22	123		T23	63		T24	89
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1285051	1			T22	42		T23	18		T24	29
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1521115	1			T22	20		T23	40		T24	9
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	521297	1			T22	152		T24	87		T28	18
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1277854	1			T22	28		T23	23		T24	12
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4718768	1			T22	23		T23	81		T24	8
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3684256	1			T22	91		T23	77		T24	107
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1282009	1			T22	45		T23	44		T24	5
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1518277	1			T22	22		T23	16		T24	13
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	524065	1			T22	182		T24	101		T28	15
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1279572	1			T22	30		T23	32		T24	10
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4712021	1			T22	31		T23	97		T24	28
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3692058	1			T22	172		T23	58		T24	127
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1286702	1			T22	59		T23	24		T24	16
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1518177	1			T22	10		T23	35		T24	6
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	521515	1			T22	96		T24	57		T28	25
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1276474	1			T22	25		T23	36		T24	10
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4719971	1			T22	19		T23	86		T24	13
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3677957	1			T22	96		T23	76		T24	76
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1287050	1			T22	44		T23	36		T24	11
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1519025	1			T22	31		T23	28		T24	14
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	522256	1			T22	142		T24	120		T28	19
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1280688	1			T22	61		T23	24		T24	10
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4724517	1			T22	29		T23	83		T24	27
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3680798	1			T22	127		T23	66		T24	115
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1287006	1			T22	17		T23	22		T24	17
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1515710	1			T22	21		T23	56		T24	11
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	523792	1			T22	164		T24	64		T28	9
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1275124	1			T22	35		T23	23		T24	10
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4712013	1			T22	36		T23	102		T24	29
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3695321	1			T22	136		T23	63		T24	126
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1288680	1			T22	40		T23	38		T24	25
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1510980	1			T22	21		T23	17		T24	11
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	523086	1			T22	92		T24	45		T28	8
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1276867	1			T22	68		T23	30		T24	8
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4732888	1			T22	9		T23	87		T24	11
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3676445	1			T22	112		T23	63		T24	61
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1286017	1			T22	29		T23	24		T24	6
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1519640	1			T22	30		T23	24		T24	27
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	518088	1			T22	182		T24	127		T28	17
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1273869	1			T22	31		T23	52		T24	12
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4727233	1			T22	10		T23	88		T24	20
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3680880	1			T22	84		T23	67		T24	86
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1278483	1			T22	38		T23	31		T24	6
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1522948	1			T22	38		T23	30		T24	21
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	523461	1			T22	167		T24	105		T28	7
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1273942	1			T22	56		T23	34		T24	6
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4722278	1			T22	24		T23	80		T24	21
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3689017	1			T22	148		T23	67		T24	105
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1289453	1			T22	38		T23	28		T24	2
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1515214	1			T22	14		T23	51		T24	15
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	519072	1			T22	142		T24	88		T28	8
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1271913	1			T22	27		T23	24		T24	13
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4726168	1			T22	39		T23	95		T24	22
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3683325	1			T22	158		T23	56		T24	123
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1283273	1			T22	67		T23	36		T24	12
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1518414	1			T22	12		T23	31		T24	9
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	525466	1			T22	80		T24	76		T28	7
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1270301	1			T22	37		T23	32		T24	2
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4715729	1			T22	22		T23	104		T24	22
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3689784	1			T22	137		T23	65		T24	106
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1287598	1			T22	35		T23	38		T24	16
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1516228	1			T22	16		T23	16		T24	8
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	525663	1			T22	151		T24	82		T28	27
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1271945	1			T22	32		T23	27		T24	10
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4719066	1			T22	19		T23	99		T24	18
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3687642	1			T22	168		T23	63		T24	102
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1291946	1			T22	44		T23	20		T24	8
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1517940	1			T22	10		T23	36		T24	18
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	518998	1			T22	116		T24	88		T28	30
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1271355	1			T22	36		T23	32		T24	10
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4715774	1			T22	22		T23	110		T24	25
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3694372	1			T22	126		T23	56		T24	136
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1286836	1			T22	55		T23	36		T24	18
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1518766	1			T22	24		T23	20		T24	10
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	522412	1			T22	116		T24	47		T28	15
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1268787	1			T22	50		T23	28		T24	8
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4715896	1			T22	26		T23	82		T24	15
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3686194	1			T22	145		T23	85		T24	96
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1284878	1			T22	36		T23	16		T24	12
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1522110	1			T22	16		T23	34		T24	16
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	525783	1			T22	111		T24	99		T28	9
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1272086	1			T22	59		T23	33		T24	6
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4721981	1			T22	22		T23	111		T24	24
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3685562	1			T22	108		T23	58		T24	106
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1282558	1			T22	54		T23	14		T24	10
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1522296	1			T22	21		T23	49		T24	13
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	521360	1			T22	139		T24	73		T28	10
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1273190	1			T22	49		T23	18		T24	18
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4715292	1			T22	25		T23	97		T24	14
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3691591	1			T22	155		T23	55		T24	53
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1284878	1			T22	46		T23	38		T24	4
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1519051	1			T22	13		T23	18		T24	25
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	522542	1			T22	99		T24	126		T28	25
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1273593	1			T22	55		T23	42		T24	22
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4715847	1			T22	34		T23	104		T24	11
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3692119	1			T22	156		T23	58		T24	85
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1289315	1			T22	57		T23	16		T24	4
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1516831	1			T22	11		T23	36		T24	24
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	519875	1			T22	121		T24	110		T28	18
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1272960	1			T22	14		T23	36		T24	10
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4714615	1			T22	35		T23	109		T24	24
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3692609	1			T22	170		T23	56		T24	154
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1284126	1			T22	55		T23	33		T24	20
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1517817	1			T22	15		T23	20		T24	5
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	523664	1			T22	84		T24	39		T28	18
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1274116	1			T22	34		T23	32		T24	2
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4718814	1			T22	36		T23	93		T24	19
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3685326	1			T22	151		T23	66		T24	147
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1276740	1			T22	41		T23	24		T24	21
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1527242	1			T22	13		T23	35		T24	11
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	523450	1			T22	103		T24	36		T28	19
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1275375	1			T22	49		T23	32		T24	10
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4719249	1			T22	30		T23	82		T24	14
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3689742	1			T22	188		T23	75		T24	93
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1286753	1			T22	61		T23	26		T24	6
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1517165	1			T22	12		T23	32		T24	18
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	521530	1			T22	77		T24	101		T28	16
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1272508	1			T22	25		T23	35		T24	12
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4724447	1			T22	22		T23	95		T24	24
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3686700	1			T22	127		T23	68		T24	142
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1281020	1			T22	51		T23	36		T24	12
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1520434	1			T22	10		T23	31		T24	7
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	521801	1			T22	142		T24	51		T28	29
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1272545	1			T22	41		T23	20		T24	8
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4717551	1			T22	16		T23	114		T24	12
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3687581	1			T22	113		T23	63		T24	84
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1282977	1			T22	45		T23	29		T24	10
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1524030	1			T22	24		T23	24		T24	17
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	524068	1			T22	142		T24	104		T28	10
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1270740	1			T22	53		T23	20		T24	17

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal