Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[1]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[2]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[3]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[4]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[5]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[6]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[7]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[8]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[9]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[10]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[11]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[12]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[13]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[14]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[15]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[16]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[17]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[18]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[19]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[20]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[21]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[22]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[23]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[24]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[25]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[26]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[27]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[28]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[29]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[30]	13006947	1			T22	393		T23	250		T24	244
bins_for_gpio_bits[31]	13006947	1			T22	393		T23	250		T24	244

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

240722322

1

T22

2849

T23

4986

T24

1464

auto[1]

175499982

1

T22

9727

T23

3014

T24

6344

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

240716131

1

T22

2849

T23

4978

T24

1464

auto[1]

175506173

1

T22

9727

T23

3022

T24

6344

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	7288132	1			T22	79		T23	167		T24	43
bins_for_gpio_bits[0]	auto[0]	auto[1]	229722	1			T22	7		T23	5		T24	7
bins_for_gpio_bits[0]	auto[1]	auto[0]	229891	1			T22	7		T23	5		T24	7
bins_for_gpio_bits[0]	auto[1]	auto[1]	5259202	1			T22	300		T23	73		T24	187
bins_for_gpio_bits[1]	auto[0]	auto[0]	7292188	1			T22	77		T23	152		T24	42
bins_for_gpio_bits[1]	auto[0]	auto[1]	229986	1			T22	6		T23	8		T24	4
bins_for_gpio_bits[1]	auto[1]	auto[0]	230170	1			T22	6		T23	8		T24	4
bins_for_gpio_bits[1]	auto[1]	auto[1]	5254603	1			T22	304		T23	82		T24	194
bins_for_gpio_bits[2]	auto[0]	auto[0]	7292682	1			T22	84		T23	136		T24	42
bins_for_gpio_bits[2]	auto[0]	auto[1]	229495	1			T22	12		T23	10		T24	3
bins_for_gpio_bits[2]	auto[1]	auto[0]	229675	1			T22	12		T23	10		T24	3
bins_for_gpio_bits[2]	auto[1]	auto[1]	5255095	1			T22	285		T23	94		T24	196
bins_for_gpio_bits[3]	auto[0]	auto[0]	7287786	1			T22	86		T23	135		T24	40
bins_for_gpio_bits[3]	auto[0]	auto[1]	230156	1			T22	8		T23	9		T24	2
bins_for_gpio_bits[3]	auto[1]	auto[0]	230352	1			T22	8		T23	9		T24	2
bins_for_gpio_bits[3]	auto[1]	auto[1]	5258653	1			T22	291		T23	97		T24	200
bins_for_gpio_bits[4]	auto[0]	auto[0]	7297361	1			T22	92		T23	145		T24	50
bins_for_gpio_bits[4]	auto[0]	auto[1]	229437	1			T22	9		T23	7		T24	6
bins_for_gpio_bits[4]	auto[1]	auto[0]	229675	1			T22	9		T23	8		T24	6
bins_for_gpio_bits[4]	auto[1]	auto[1]	5250474	1			T22	283		T23	90		T24	182
bins_for_gpio_bits[5]	auto[0]	auto[0]	7288014	1			T22	72		T23	159		T24	31
bins_for_gpio_bits[5]	auto[0]	auto[1]	229653	1			T22	7		T23	4		T24	3
bins_for_gpio_bits[5]	auto[1]	auto[0]	229834	1			T22	7		T23	5		T24	3
bins_for_gpio_bits[5]	auto[1]	auto[1]	5259446	1			T22	307		T23	82		T24	207
bins_for_gpio_bits[6]	auto[0]	auto[0]	7278057	1			T22	54		T23	136		T24	58
bins_for_gpio_bits[6]	auto[0]	auto[1]	229692	1			T22	5		T23	8		T24	9
bins_for_gpio_bits[6]	auto[1]	auto[0]	229859	1			T22	5		T23	8		T24	9
bins_for_gpio_bits[6]	auto[1]	auto[1]	5269339	1			T22	329		T23	98		T24	168
bins_for_gpio_bits[7]	auto[0]	auto[0]	7300071	1			T22	74		T23	151		T24	39
bins_for_gpio_bits[7]	auto[0]	auto[1]	229298	1			T22	8		T23	7		T24	4
bins_for_gpio_bits[7]	auto[1]	auto[0]	229495	1			T22	8		T23	7		T24	4
bins_for_gpio_bits[7]	auto[1]	auto[1]	5248083	1			T22	303		T23	85		T24	197
bins_for_gpio_bits[8]	auto[0]	auto[0]	7280350	1			T22	108		T23	161		T24	39
bins_for_gpio_bits[8]	auto[0]	auto[1]	230095	1			T22	13		T23	6		T24	4
bins_for_gpio_bits[8]	auto[1]	auto[0]	230297	1			T22	13		T23	7		T24	4
bins_for_gpio_bits[8]	auto[1]	auto[1]	5266205	1			T22	259		T23	76		T24	197
bins_for_gpio_bits[9]	auto[0]	auto[0]	7296365	1			T22	80		T23	160		T24	39
bins_for_gpio_bits[9]	auto[0]	auto[1]	230201	1			T22	8		T23	6		T24	2
bins_for_gpio_bits[9]	auto[1]	auto[0]	230398	1			T22	8		T23	6		T24	2
bins_for_gpio_bits[9]	auto[1]	auto[1]	5249983	1			T22	297		T23	78		T24	201
bins_for_gpio_bits[10]	auto[0]	auto[0]	7295054	1			T22	83		T23	158		T24	48
bins_for_gpio_bits[10]	auto[0]	auto[1]	229681	1			T22	7		T23	5		T24	8
bins_for_gpio_bits[10]	auto[1]	auto[0]	229905	1			T22	7		T23	6		T24	8
bins_for_gpio_bits[10]	auto[1]	auto[1]	5252307	1			T22	296		T23	81		T24	180
bins_for_gpio_bits[11]	auto[0]	auto[0]	7288852	1			T22	83		T23	132		T24	24
bins_for_gpio_bits[11]	auto[0]	auto[1]	229989	1			T22	7		T23	9		T24	2
bins_for_gpio_bits[11]	auto[1]	auto[0]	230202	1			T22	7		T23	9		T24	2
bins_for_gpio_bits[11]	auto[1]	auto[1]	5257904	1			T22	296		T23	100		T24	216
bins_for_gpio_bits[12]	auto[0]	auto[0]	7287251	1			T22	91		T23	147		T24	44
bins_for_gpio_bits[12]	auto[0]	auto[1]	229448	1			T22	9		T23	9		T24	6
bins_for_gpio_bits[12]	auto[1]	auto[0]	229649	1			T22	9		T23	9		T24	6
bins_for_gpio_bits[12]	auto[1]	auto[1]	5260599	1			T22	284		T23	85		T24	188
bins_for_gpio_bits[13]	auto[0]	auto[0]	7296240	1			T22	88		T23	145		T24	34
bins_for_gpio_bits[13]	auto[0]	auto[1]	229637	1			T22	6		T23	5		T24	4
bins_for_gpio_bits[13]	auto[1]	auto[0]	229806	1			T22	6		T23	5		T24	4
bins_for_gpio_bits[13]	auto[1]	auto[1]	5251264	1			T22	293		T23	95		T24	202
bins_for_gpio_bits[14]	auto[0]	auto[0]	7297769	1			T22	62		T23	155		T24	50
bins_for_gpio_bits[14]	auto[0]	auto[1]	229233	1			T22	5		T23	5		T24	5
bins_for_gpio_bits[14]	auto[1]	auto[0]	229464	1			T22	5		T23	6		T24	5
bins_for_gpio_bits[14]	auto[1]	auto[1]	5250481	1			T22	321		T23	84		T24	184
bins_for_gpio_bits[15]	auto[0]	auto[0]	7281326	1			T22	86		T23	150		T24	58
bins_for_gpio_bits[15]	auto[0]	auto[1]	230171	1			T22	11		T23	7		T24	7
bins_for_gpio_bits[15]	auto[1]	auto[0]	230347	1			T22	11		T23	7		T24	7
bins_for_gpio_bits[15]	auto[1]	auto[1]	5265103	1			T22	285		T23	86		T24	172
bins_for_gpio_bits[16]	auto[0]	auto[0]	7308167	1			T22	64		T23	125		T24	41
bins_for_gpio_bits[16]	auto[0]	auto[1]	230170	1			T22	4		T23	10		T24	3
bins_for_gpio_bits[16]	auto[1]	auto[0]	230378	1			T22	4		T23	10		T24	3
bins_for_gpio_bits[16]	auto[1]	auto[1]	5238232	1			T22	321		T23	105		T24	197
bins_for_gpio_bits[17]	auto[0]	auto[0]	7298367	1			T22	78		T23	140		T24	44
bins_for_gpio_bits[17]	auto[0]	auto[1]	230093	1			T22	8		T23	9		T24	3
bins_for_gpio_bits[17]	auto[1]	auto[0]	230297	1			T22	8		T23	9		T24	3
bins_for_gpio_bits[17]	auto[1]	auto[1]	5248190	1			T22	299		T23	92		T24	194
bins_for_gpio_bits[18]	auto[0]	auto[0]	7297308	1			T22	67		T23	151		T24	37
bins_for_gpio_bits[18]	auto[0]	auto[1]	229468	1			T22	9		T23	8		T24	1
bins_for_gpio_bits[18]	auto[1]	auto[0]	229637	1			T22	9		T23	8		T24	1
bins_for_gpio_bits[18]	auto[1]	auto[1]	5250534	1			T22	308		T23	83		T24	205
bins_for_gpio_bits[19]	auto[0]	auto[0]	7298181	1			T22	107		T23	154		T24	39
bins_for_gpio_bits[19]	auto[0]	auto[1]	229480	1			T22	11		T23	8		T24	4
bins_for_gpio_bits[19]	auto[1]	auto[0]	229674	1			T22	11		T23	8		T24	4
bins_for_gpio_bits[19]	auto[1]	auto[1]	5249612	1			T22	264		T23	80		T24	197
bins_for_gpio_bits[20]	auto[0]	auto[0]	7290227	1			T22	62		T23	151		T24	41
bins_for_gpio_bits[20]	auto[0]	auto[1]	229145	1			T22	11		T23	6		T24	5
bins_for_gpio_bits[20]	auto[1]	auto[0]	229328	1			T22	11		T23	7		T24	5
bins_for_gpio_bits[20]	auto[1]	auto[1]	5258247	1			T22	309		T23	86		T24	193
bins_for_gpio_bits[21]	auto[0]	auto[0]	7298700	1			T22	64		T23	148		T24	40
bins_for_gpio_bits[21]	auto[0]	auto[1]	230048	1			T22	9		T23	7		T24	4
bins_for_gpio_bits[21]	auto[1]	auto[0]	230252	1			T22	9		T23	7		T24	4
bins_for_gpio_bits[21]	auto[1]	auto[1]	5247947	1			T22	311		T23	88		T24	196
bins_for_gpio_bits[22]	auto[0]	auto[0]	7291723	1			T22	92		T23	159		T24	45
bins_for_gpio_bits[22]	auto[0]	auto[1]	229480	1			T22	9		T23	7		T24	8
bins_for_gpio_bits[22]	auto[1]	auto[0]	229653	1			T22	9		T23	7		T24	8
bins_for_gpio_bits[22]	auto[1]	auto[1]	5256091	1			T22	283		T23	77		T24	183
bins_for_gpio_bits[23]	auto[0]	auto[0]	7292618	1			T22	70		T23	122		T24	38
bins_for_gpio_bits[23]	auto[0]	auto[1]	230120	1			T22	8		T23	9		T24	5
bins_for_gpio_bits[23]	auto[1]	auto[0]	230266	1			T22	8		T23	10		T24	5
bins_for_gpio_bits[23]	auto[1]	auto[1]	5253943	1			T22	307		T23	109		T24	196
bins_for_gpio_bits[24]	auto[0]	auto[0]	7297010	1			T22	88		T23	166		T24	42
bins_for_gpio_bits[24]	auto[0]	auto[1]	229638	1			T22	9		T23	8		T24	5
bins_for_gpio_bits[24]	auto[1]	auto[0]	229825	1			T22	9		T23	8		T24	5
bins_for_gpio_bits[24]	auto[1]	auto[1]	5250474	1			T22	287		T23	68		T24	192
bins_for_gpio_bits[25]	auto[0]	auto[0]	7288832	1			T22	77		T23	145		T24	41
bins_for_gpio_bits[25]	auto[0]	auto[1]	230179	1			T22	7		T23	8		T24	2
bins_for_gpio_bits[25]	auto[1]	auto[0]	230389	1			T22	7		T23	8		T24	2
bins_for_gpio_bits[25]	auto[1]	auto[1]	5257547	1			T22	302		T23	89		T24	199
bins_for_gpio_bits[26]	auto[0]	auto[0]	7291630	1			T22	93		T23	149		T24	37
bins_for_gpio_bits[26]	auto[0]	auto[1]	230196	1			T22	9		T23	7		T24	2
bins_for_gpio_bits[26]	auto[1]	auto[0]	230363	1			T22	9		T23	7		T24	2
bins_for_gpio_bits[26]	auto[1]	auto[1]	5254758	1			T22	282		T23	87		T24	203
bins_for_gpio_bits[27]	auto[0]	auto[0]	7286298	1			T22	96		T23	155		T24	43
bins_for_gpio_bits[27]	auto[0]	auto[1]	230022	1			T22	9		T23	7		T24	6
bins_for_gpio_bits[27]	auto[1]	auto[0]	230260	1			T22	9		T23	7		T24	6
bins_for_gpio_bits[27]	auto[1]	auto[1]	5260367	1			T22	279		T23	81		T24	189
bins_for_gpio_bits[28]	auto[0]	auto[0]	7292821	1			T22	83		T23	145		T24	43
bins_for_gpio_bits[28]	auto[0]	auto[1]	229757	1			T22	7		T23	7		T24	8
bins_for_gpio_bits[28]	auto[1]	auto[0]	229975	1			T22	7		T23	7		T24	8
bins_for_gpio_bits[28]	auto[1]	auto[1]	5254394	1			T22	296		T23	91		T24	185
bins_for_gpio_bits[29]	auto[0]	auto[0]	7293139	1			T22	93		T23	130		T24	35
bins_for_gpio_bits[29]	auto[0]	auto[1]	229815	1			T22	10		T23	9		T24	3
bins_for_gpio_bits[29]	auto[1]	auto[0]	230028	1			T22	10		T23	10		T24	3
bins_for_gpio_bits[29]	auto[1]	auto[1]	5253965	1			T22	280		T23	101		T24	203
bins_for_gpio_bits[30]	auto[0]	auto[0]	7295730	1			T22	72		T23	155		T24	37
bins_for_gpio_bits[30]	auto[0]	auto[1]	229989	1			T22	11		T23	7		T24	6
bins_for_gpio_bits[30]	auto[1]	auto[0]	230171	1			T22	11		T23	7		T24	6
bins_for_gpio_bits[30]	auto[1]	auto[1]	5251057	1			T22	299		T23	81		T24	195
bins_for_gpio_bits[31]	auto[0]	auto[0]	7294373	1			T22	76		T23	158		T24	35
bins_for_gpio_bits[31]	auto[0]	auto[1]	230015	1			T22	9		T23	9		T24	4
bins_for_gpio_bits[31]	auto[1]	auto[0]	230185	1			T22	9		T23	9		T24	4
bins_for_gpio_bits[31]	auto[1]	auto[1]	5252374	1			T22	299		T23	74		T24	201