Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7635810 |
1 |
|
|
T22 |
202 |
|
T23 |
190 |
|
T24 |
136 |
| auto[1] |
5547294 |
1 |
|
|
T27 |
83 |
|
T28 |
33 |
|
T29 |
639 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12477722 |
1 |
|
|
T22 |
202 |
|
T23 |
190 |
|
T24 |
136 |
| auto[1] |
705382 |
1 |
|
|
T27 |
2 |
|
T28 |
1 |
|
T29 |
34 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7679771 |
1 |
|
|
T22 |
202 |
|
T23 |
190 |
|
T24 |
136 |
| auto[1] |
5503333 |
1 |
|
|
T27 |
51 |
|
T28 |
52 |
|
T29 |
802 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2400154 |
1 |
|
|
T27 |
7 |
|
T28 |
24 |
|
T29 |
389 |
| auto[1] |
auto[0] |
auto[1] |
352752 |
1 |
|
|
T29 |
18 |
|
T31 |
84 |
|
T32 |
3305 |
| auto[1] |
auto[1] |
auto[0] |
2397797 |
1 |
|
|
T27 |
42 |
|
T28 |
27 |
|
T29 |
379 |
| auto[1] |
auto[1] |
auto[1] |
352630 |
1 |
|
|
T27 |
2 |
|
T28 |
1 |
|
T29 |
16 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |