Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7646764 |
1 |
|
|
T22 |
202 |
|
T23 |
190 |
|
T24 |
136 |
| auto[1] |
5536340 |
1 |
|
|
T27 |
82 |
|
T28 |
36 |
|
T29 |
780 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10816050 |
1 |
|
|
T22 |
202 |
|
T23 |
190 |
|
T24 |
136 |
| auto[1] |
2367054 |
1 |
|
|
T27 |
46 |
|
T28 |
3 |
|
T29 |
166 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7650256 |
1 |
|
|
T22 |
202 |
|
T23 |
190 |
|
T24 |
136 |
| auto[1] |
5532848 |
1 |
|
|
T27 |
79 |
|
T28 |
12 |
|
T29 |
687 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1583056 |
1 |
|
|
T27 |
8 |
|
T28 |
5 |
|
T29 |
254 |
| auto[1] |
auto[0] |
auto[1] |
1182898 |
1 |
|
|
T27 |
20 |
|
T28 |
3 |
|
T29 |
53 |
| auto[1] |
auto[1] |
auto[0] |
1582738 |
1 |
|
|
T27 |
25 |
|
T28 |
4 |
|
T29 |
267 |
| auto[1] |
auto[1] |
auto[1] |
1184156 |
1 |
|
|
T27 |
26 |
|
T29 |
113 |
|
T31 |
373 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |