Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7622049 |
1 |
|
|
T22 |
202 |
|
T23 |
190 |
|
T24 |
136 |
| auto[1] |
5561055 |
1 |
|
|
T27 |
54 |
|
T28 |
35 |
|
T29 |
655 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10824804 |
1 |
|
|
T22 |
202 |
|
T23 |
190 |
|
T24 |
136 |
| auto[1] |
2358300 |
1 |
|
|
T27 |
47 |
|
T28 |
4 |
|
T29 |
131 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7659948 |
1 |
|
|
T22 |
202 |
|
T23 |
190 |
|
T24 |
136 |
| auto[1] |
5523156 |
1 |
|
|
T27 |
92 |
|
T28 |
13 |
|
T29 |
534 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1571015 |
1 |
|
|
T27 |
31 |
|
T28 |
1 |
|
T29 |
259 |
| auto[1] |
auto[0] |
auto[1] |
1172751 |
1 |
|
|
T27 |
20 |
|
T28 |
4 |
|
T29 |
80 |
| auto[1] |
auto[1] |
auto[0] |
1593841 |
1 |
|
|
T27 |
14 |
|
T28 |
8 |
|
T29 |
144 |
| auto[1] |
auto[1] |
auto[1] |
1185549 |
1 |
|
|
T27 |
27 |
|
T29 |
51 |
|
T31 |
360 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |