Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7644943 |
1 |
|
|
T22 |
202 |
|
T23 |
190 |
|
T24 |
136 |
| auto[1] |
5538161 |
1 |
|
|
T27 |
76 |
|
T28 |
25 |
|
T29 |
746 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12477626 |
1 |
|
|
T22 |
202 |
|
T23 |
190 |
|
T24 |
136 |
| auto[1] |
705478 |
1 |
|
|
T27 |
4 |
|
T28 |
1 |
|
T29 |
30 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7680639 |
1 |
|
|
T22 |
202 |
|
T23 |
190 |
|
T24 |
136 |
| auto[1] |
5502465 |
1 |
|
|
T27 |
83 |
|
T28 |
33 |
|
T29 |
814 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2392691 |
1 |
|
|
T27 |
39 |
|
T28 |
12 |
|
T29 |
404 |
| auto[1] |
auto[0] |
auto[1] |
351220 |
1 |
|
|
T27 |
2 |
|
T29 |
18 |
|
T31 |
131 |
| auto[1] |
auto[1] |
auto[0] |
2404296 |
1 |
|
|
T27 |
40 |
|
T28 |
20 |
|
T29 |
380 |
| auto[1] |
auto[1] |
auto[1] |
354258 |
1 |
|
|
T27 |
2 |
|
T28 |
1 |
|
T29 |
12 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |