Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7636222 |
1 |
|
|
T22 |
202 |
|
T23 |
190 |
|
T24 |
136 |
| auto[1] |
5546882 |
1 |
|
|
T27 |
68 |
|
T28 |
27 |
|
T29 |
746 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12470924 |
1 |
|
|
T22 |
202 |
|
T23 |
190 |
|
T24 |
136 |
| auto[1] |
712180 |
1 |
|
|
T27 |
8 |
|
T28 |
2 |
|
T29 |
36 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7634203 |
1 |
|
|
T22 |
202 |
|
T23 |
190 |
|
T24 |
136 |
| auto[1] |
5548901 |
1 |
|
|
T27 |
89 |
|
T28 |
26 |
|
T29 |
732 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2414632 |
1 |
|
|
T27 |
35 |
|
T28 |
16 |
|
T29 |
283 |
| auto[1] |
auto[0] |
auto[1] |
355081 |
1 |
|
|
T27 |
4 |
|
T28 |
2 |
|
T29 |
15 |
| auto[1] |
auto[1] |
auto[0] |
2422089 |
1 |
|
|
T27 |
46 |
|
T28 |
8 |
|
T29 |
413 |
| auto[1] |
auto[1] |
auto[1] |
357099 |
1 |
|
|
T27 |
4 |
|
T29 |
21 |
|
T31 |
107 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |