Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 939
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html
T766 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.4102598287 Jun 11 01:22:48 PM PDT 24 Jun 11 01:22:51 PM PDT 24 214839111 ps
T50 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2470460339 Jun 11 01:23:13 PM PDT 24 Jun 11 01:23:14 PM PDT 24 89170852 ps
T767 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1673449797 Jun 11 01:22:37 PM PDT 24 Jun 11 01:22:41 PM PDT 24 171556231 ps
T768 /workspace/coverage/cover_reg_top/19.gpio_intr_test.3690720373 Jun 11 01:23:27 PM PDT 24 Jun 11 01:23:28 PM PDT 24 52314299 ps
T97 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3000839558 Jun 11 01:22:47 PM PDT 24 Jun 11 01:22:50 PM PDT 24 42591767 ps
T84 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.3232208047 Jun 11 01:23:12 PM PDT 24 Jun 11 01:23:13 PM PDT 24 28351103 ps
T98 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2192140298 Jun 11 01:22:36 PM PDT 24 Jun 11 01:22:38 PM PDT 24 42830072 ps
T769 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2218698594 Jun 11 01:23:10 PM PDT 24 Jun 11 01:23:12 PM PDT 24 562002782 ps
T770 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3703769663 Jun 11 01:22:37 PM PDT 24 Jun 11 01:22:39 PM PDT 24 15082241 ps
T771 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1376387685 Jun 11 01:22:48 PM PDT 24 Jun 11 01:22:51 PM PDT 24 103748928 ps
T772 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.806149925 Jun 11 01:23:27 PM PDT 24 Jun 11 01:23:29 PM PDT 24 74193355 ps
T773 /workspace/coverage/cover_reg_top/21.gpio_intr_test.3669447092 Jun 11 01:23:25 PM PDT 24 Jun 11 01:23:27 PM PDT 24 13257395 ps
T774 /workspace/coverage/cover_reg_top/38.gpio_intr_test.1877985411 Jun 11 01:23:36 PM PDT 24 Jun 11 01:23:37 PM PDT 24 52941764 ps
T775 /workspace/coverage/cover_reg_top/44.gpio_intr_test.3610865379 Jun 11 01:23:36 PM PDT 24 Jun 11 01:23:37 PM PDT 24 36206120 ps
T85 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.525569505 Jun 11 01:22:04 PM PDT 24 Jun 11 01:22:05 PM PDT 24 19922280 ps
T776 /workspace/coverage/cover_reg_top/16.gpio_intr_test.1520101391 Jun 11 01:23:27 PM PDT 24 Jun 11 01:23:29 PM PDT 24 17996311 ps
T777 /workspace/coverage/cover_reg_top/18.gpio_intr_test.147280094 Jun 11 01:23:27 PM PDT 24 Jun 11 01:23:29 PM PDT 24 14290694 ps
T778 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1991744539 Jun 11 01:22:03 PM PDT 24 Jun 11 01:22:05 PM PDT 24 311093545 ps
T779 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1138456604 Jun 11 01:22:14 PM PDT 24 Jun 11 01:22:16 PM PDT 24 41075119 ps
T86 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3818845459 Jun 11 01:22:04 PM PDT 24 Jun 11 01:22:06 PM PDT 24 104922907 ps
T99 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.1213770838 Jun 11 01:22:47 PM PDT 24 Jun 11 01:22:49 PM PDT 24 221095447 ps
T780 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.2723518956 Jun 11 01:23:09 PM PDT 24 Jun 11 01:23:11 PM PDT 24 37573063 ps
T87 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2627657078 Jun 11 01:22:27 PM PDT 24 Jun 11 01:22:29 PM PDT 24 22075120 ps
T781 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2087896135 Jun 11 01:22:57 PM PDT 24 Jun 11 01:23:00 PM PDT 24 313866482 ps
T100 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3992951158 Jun 11 01:23:25 PM PDT 24 Jun 11 01:23:27 PM PDT 24 40016558 ps
T782 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3897496536 Jun 11 01:22:14 PM PDT 24 Jun 11 01:22:15 PM PDT 24 161299150 ps
T783 /workspace/coverage/cover_reg_top/13.gpio_intr_test.2365506663 Jun 11 01:23:10 PM PDT 24 Jun 11 01:23:11 PM PDT 24 52392540 ps
T88 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3723312284 Jun 11 01:22:57 PM PDT 24 Jun 11 01:22:59 PM PDT 24 152582115 ps
T784 /workspace/coverage/cover_reg_top/14.gpio_intr_test.721023800 Jun 11 01:23:10 PM PDT 24 Jun 11 01:23:12 PM PDT 24 33201060 ps
T785 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1767844264 Jun 11 01:22:49 PM PDT 24 Jun 11 01:22:51 PM PDT 24 26671997 ps
T786 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2397836733 Jun 11 01:22:58 PM PDT 24 Jun 11 01:23:01 PM PDT 24 110439663 ps
T787 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.539610653 Jun 11 01:22:46 PM PDT 24 Jun 11 01:22:48 PM PDT 24 128653482 ps
T788 /workspace/coverage/cover_reg_top/26.gpio_intr_test.4102216286 Jun 11 01:23:37 PM PDT 24 Jun 11 01:23:39 PM PDT 24 11487284 ps
T789 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3482310101 Jun 11 01:22:26 PM PDT 24 Jun 11 01:22:28 PM PDT 24 51645466 ps
T790 /workspace/coverage/cover_reg_top/15.gpio_intr_test.331842218 Jun 11 01:23:11 PM PDT 24 Jun 11 01:23:13 PM PDT 24 13700593 ps
T791 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1160235771 Jun 11 01:22:47 PM PDT 24 Jun 11 01:22:50 PM PDT 24 136543644 ps
T792 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3969944488 Jun 11 01:23:25 PM PDT 24 Jun 11 01:23:27 PM PDT 24 36794443 ps
T91 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2660324269 Jun 11 01:23:28 PM PDT 24 Jun 11 01:23:29 PM PDT 24 24626984 ps
T793 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2569809046 Jun 11 01:22:25 PM PDT 24 Jun 11 01:22:27 PM PDT 24 215034306 ps
T794 /workspace/coverage/cover_reg_top/33.gpio_intr_test.3978332163 Jun 11 01:23:36 PM PDT 24 Jun 11 01:23:38 PM PDT 24 14446332 ps
T795 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3431820897 Jun 11 01:23:10 PM PDT 24 Jun 11 01:23:12 PM PDT 24 37816872 ps
T796 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.3563005598 Jun 11 01:21:50 PM PDT 24 Jun 11 01:21:52 PM PDT 24 18578897 ps
T797 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1013725759 Jun 11 01:22:58 PM PDT 24 Jun 11 01:23:01 PM PDT 24 132440025 ps
T798 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3058855724 Jun 11 01:23:26 PM PDT 24 Jun 11 01:23:28 PM PDT 24 47489168 ps
T799 /workspace/coverage/cover_reg_top/0.gpio_intr_test.3142552955 Jun 11 01:22:03 PM PDT 24 Jun 11 01:22:05 PM PDT 24 29846571 ps
T800 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1910606255 Jun 11 01:23:27 PM PDT 24 Jun 11 01:23:29 PM PDT 24 83248813 ps
T801 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1021611031 Jun 11 01:22:37 PM PDT 24 Jun 11 01:22:39 PM PDT 24 34729652 ps
T802 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3199679885 Jun 11 01:22:15 PM PDT 24 Jun 11 01:22:18 PM PDT 24 71362330 ps
T803 /workspace/coverage/cover_reg_top/31.gpio_intr_test.2663701661 Jun 11 01:23:37 PM PDT 24 Jun 11 01:23:38 PM PDT 24 142097858 ps
T804 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2874098825 Jun 11 01:22:26 PM PDT 24 Jun 11 01:22:28 PM PDT 24 14552096 ps
T805 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.3607841787 Jun 11 01:22:15 PM PDT 24 Jun 11 01:22:18 PM PDT 24 30496870 ps
T806 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.2014038243 Jun 11 01:22:58 PM PDT 24 Jun 11 01:23:00 PM PDT 24 70780258 ps
T807 /workspace/coverage/cover_reg_top/5.gpio_intr_test.2912361065 Jun 11 01:22:37 PM PDT 24 Jun 11 01:22:38 PM PDT 24 13226023 ps
T808 /workspace/coverage/cover_reg_top/10.gpio_intr_test.3123992261 Jun 11 01:22:58 PM PDT 24 Jun 11 01:23:00 PM PDT 24 24386308 ps
T809 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.4066883389 Jun 11 01:22:58 PM PDT 24 Jun 11 01:23:01 PM PDT 24 38062337 ps
T89 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.1242289745 Jun 11 01:23:12 PM PDT 24 Jun 11 01:23:14 PM PDT 24 29295378 ps
T810 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1424026968 Jun 11 01:23:25 PM PDT 24 Jun 11 01:23:27 PM PDT 24 353667282 ps
T811 /workspace/coverage/cover_reg_top/11.gpio_intr_test.842350317 Jun 11 01:22:58 PM PDT 24 Jun 11 01:22:59 PM PDT 24 54992535 ps
T812 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.209985473 Jun 11 01:22:58 PM PDT 24 Jun 11 01:22:59 PM PDT 24 112228233 ps
T813 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.2506256770 Jun 11 01:22:48 PM PDT 24 Jun 11 01:22:51 PM PDT 24 112709729 ps
T814 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.1744458292 Jun 11 01:23:12 PM PDT 24 Jun 11 01:23:15 PM PDT 24 552206134 ps
T815 /workspace/coverage/cover_reg_top/9.gpio_intr_test.2078772132 Jun 11 01:22:58 PM PDT 24 Jun 11 01:23:00 PM PDT 24 47966070 ps
T816 /workspace/coverage/cover_reg_top/29.gpio_intr_test.1996348680 Jun 11 01:23:35 PM PDT 24 Jun 11 01:23:36 PM PDT 24 41479578 ps
T93 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1688919999 Jun 11 01:23:11 PM PDT 24 Jun 11 01:23:12 PM PDT 24 14046707 ps
T817 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.2926554934 Jun 11 01:22:59 PM PDT 24 Jun 11 01:23:01 PM PDT 24 59926787 ps
T818 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3391100766 Jun 11 01:23:26 PM PDT 24 Jun 11 01:23:28 PM PDT 24 15589852 ps
T819 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1248449623 Jun 11 01:23:11 PM PDT 24 Jun 11 01:23:13 PM PDT 24 60653399 ps
T820 /workspace/coverage/cover_reg_top/46.gpio_intr_test.1895801629 Jun 11 01:23:38 PM PDT 24 Jun 11 01:23:40 PM PDT 24 38437809 ps
T821 /workspace/coverage/cover_reg_top/48.gpio_intr_test.2930604329 Jun 11 01:23:38 PM PDT 24 Jun 11 01:23:40 PM PDT 24 55139970 ps
T822 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3068437813 Jun 11 01:22:48 PM PDT 24 Jun 11 01:22:50 PM PDT 24 20602072 ps
T823 /workspace/coverage/cover_reg_top/28.gpio_intr_test.535564201 Jun 11 01:23:39 PM PDT 24 Jun 11 01:23:41 PM PDT 24 23356707 ps
T824 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.407863243 Jun 11 01:23:10 PM PDT 24 Jun 11 01:23:11 PM PDT 24 48607996 ps
T825 /workspace/coverage/cover_reg_top/39.gpio_intr_test.1039844875 Jun 11 01:23:38 PM PDT 24 Jun 11 01:23:40 PM PDT 24 67320317 ps
T90 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.4219340949 Jun 11 01:22:48 PM PDT 24 Jun 11 01:22:50 PM PDT 24 133068863 ps
T826 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.3730893433 Jun 11 01:23:09 PM PDT 24 Jun 11 01:23:10 PM PDT 24 69387277 ps
T827 /workspace/coverage/cover_reg_top/41.gpio_intr_test.1274003581 Jun 11 01:23:38 PM PDT 24 Jun 11 01:23:40 PM PDT 24 37772679 ps
T828 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.861605103 Jun 11 01:23:12 PM PDT 24 Jun 11 01:23:13 PM PDT 24 15536862 ps
T829 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3122687494 Jun 11 01:22:27 PM PDT 24 Jun 11 01:22:29 PM PDT 24 22471337 ps
T830 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3720671432 Jun 11 01:22:38 PM PDT 24 Jun 11 01:22:39 PM PDT 24 49681173 ps
T831 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3987736590 Jun 11 01:22:59 PM PDT 24 Jun 11 01:23:00 PM PDT 24 109040309 ps
T832 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1597786769 Jun 11 01:22:47 PM PDT 24 Jun 11 01:22:50 PM PDT 24 770745789 ps
T833 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.266166797 Jun 11 01:22:04 PM PDT 24 Jun 11 01:22:05 PM PDT 24 27682269 ps
T834 /workspace/coverage/cover_reg_top/20.gpio_intr_test.3244947901 Jun 11 01:23:29 PM PDT 24 Jun 11 01:23:30 PM PDT 24 18619824 ps
T92 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2901113023 Jun 11 01:22:25 PM PDT 24 Jun 11 01:22:29 PM PDT 24 260285334 ps
T835 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.3352683801 Jun 11 01:22:14 PM PDT 24 Jun 11 01:22:16 PM PDT 24 119396092 ps
T836 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.913143170 Jun 11 01:22:59 PM PDT 24 Jun 11 01:23:01 PM PDT 24 108717235 ps
T837 /workspace/coverage/cover_reg_top/23.gpio_intr_test.4148851056 Jun 11 01:23:26 PM PDT 24 Jun 11 01:23:28 PM PDT 24 44260485 ps
T838 /workspace/coverage/cover_reg_top/49.gpio_intr_test.1011485376 Jun 11 01:23:39 PM PDT 24 Jun 11 01:23:41 PM PDT 24 149087561 ps
T839 /workspace/coverage/cover_reg_top/25.gpio_intr_test.2138444739 Jun 11 01:23:38 PM PDT 24 Jun 11 01:23:40 PM PDT 24 16191480 ps
T840 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2016410059 Jun 11 01:24:16 PM PDT 24 Jun 11 01:24:20 PM PDT 24 178959914 ps
T841 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3240263693 Jun 11 01:24:03 PM PDT 24 Jun 11 01:24:05 PM PDT 24 125148294 ps
T842 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1304136170 Jun 11 01:23:51 PM PDT 24 Jun 11 01:23:53 PM PDT 24 46998145 ps
T843 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4194722526 Jun 11 01:24:15 PM PDT 24 Jun 11 01:24:20 PM PDT 24 29337172 ps
T844 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1453796695 Jun 11 01:24:15 PM PDT 24 Jun 11 01:24:19 PM PDT 24 195658664 ps
T845 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3387612497 Jun 11 01:24:02 PM PDT 24 Jun 11 01:24:04 PM PDT 24 49130840 ps
T846 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1167982049 Jun 11 01:24:03 PM PDT 24 Jun 11 01:24:05 PM PDT 24 71821801 ps
T847 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2304438676 Jun 11 01:23:39 PM PDT 24 Jun 11 01:23:41 PM PDT 24 68988667 ps
T848 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3399523594 Jun 11 01:24:03 PM PDT 24 Jun 11 01:24:05 PM PDT 24 78980427 ps
T849 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2459754281 Jun 11 01:24:16 PM PDT 24 Jun 11 01:24:20 PM PDT 24 76010238 ps
T850 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1789486484 Jun 11 01:23:50 PM PDT 24 Jun 11 01:23:52 PM PDT 24 94126472 ps
T851 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.271375884 Jun 11 01:23:52 PM PDT 24 Jun 11 01:23:54 PM PDT 24 281308849 ps
T852 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2776761170 Jun 11 01:23:50 PM PDT 24 Jun 11 01:23:52 PM PDT 24 156690104 ps
T853 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2748064083 Jun 11 01:24:15 PM PDT 24 Jun 11 01:24:19 PM PDT 24 206496156 ps
T854 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3803196620 Jun 11 01:24:13 PM PDT 24 Jun 11 01:24:14 PM PDT 24 54544479 ps
T855 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2927107672 Jun 11 01:24:14 PM PDT 24 Jun 11 01:24:17 PM PDT 24 440163121 ps
T856 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2050124709 Jun 11 01:23:50 PM PDT 24 Jun 11 01:23:52 PM PDT 24 249252265 ps
T857 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2463367782 Jun 11 01:23:51 PM PDT 24 Jun 11 01:23:53 PM PDT 24 157440059 ps
T858 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1993865011 Jun 11 01:24:13 PM PDT 24 Jun 11 01:24:15 PM PDT 24 100134715 ps
T859 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2078230687 Jun 11 01:24:24 PM PDT 24 Jun 11 01:24:27 PM PDT 24 47910038 ps
T860 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1332632305 Jun 11 01:24:04 PM PDT 24 Jun 11 01:24:06 PM PDT 24 179821512 ps
T861 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1287065698 Jun 11 01:23:51 PM PDT 24 Jun 11 01:23:53 PM PDT 24 186254177 ps
T862 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3990151961 Jun 11 01:24:04 PM PDT 24 Jun 11 01:24:07 PM PDT 24 281781511 ps
T863 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2526513790 Jun 11 01:24:04 PM PDT 24 Jun 11 01:24:06 PM PDT 24 114827161 ps
T864 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1423573687 Jun 11 01:24:15 PM PDT 24 Jun 11 01:24:20 PM PDT 24 50958522 ps
T865 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.255788483 Jun 11 01:23:51 PM PDT 24 Jun 11 01:23:53 PM PDT 24 40592237 ps
T866 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1998748030 Jun 11 01:24:27 PM PDT 24 Jun 11 01:24:29 PM PDT 24 108850354 ps
T867 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1713996736 Jun 11 01:24:04 PM PDT 24 Jun 11 01:24:06 PM PDT 24 47818305 ps
T868 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3037929097 Jun 11 01:23:51 PM PDT 24 Jun 11 01:23:53 PM PDT 24 66805431 ps
T869 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3550229264 Jun 11 01:24:01 PM PDT 24 Jun 11 01:24:03 PM PDT 24 48107437 ps
T870 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4206717903 Jun 11 01:24:04 PM PDT 24 Jun 11 01:24:06 PM PDT 24 138403638 ps
T871 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3207573464 Jun 11 01:24:04 PM PDT 24 Jun 11 01:24:07 PM PDT 24 272484028 ps
T872 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3093221047 Jun 11 01:24:16 PM PDT 24 Jun 11 01:24:20 PM PDT 24 192745669 ps
T873 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2847860495 Jun 11 01:23:55 PM PDT 24 Jun 11 01:23:57 PM PDT 24 47656483 ps
T874 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1154979216 Jun 11 01:24:25 PM PDT 24 Jun 11 01:24:27 PM PDT 24 194143644 ps
T875 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3921428600 Jun 11 01:24:14 PM PDT 24 Jun 11 01:24:18 PM PDT 24 149308533 ps
T876 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.4266861638 Jun 11 01:24:05 PM PDT 24 Jun 11 01:24:07 PM PDT 24 118224859 ps
T877 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1166770912 Jun 11 01:23:53 PM PDT 24 Jun 11 01:23:55 PM PDT 24 188066407 ps
T878 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3355123488 Jun 11 01:23:51 PM PDT 24 Jun 11 01:23:53 PM PDT 24 258851455 ps
T879 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.88481402 Jun 11 01:23:50 PM PDT 24 Jun 11 01:23:52 PM PDT 24 39499149 ps
T880 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.704440466 Jun 11 01:24:18 PM PDT 24 Jun 11 01:24:22 PM PDT 24 276849020 ps
T881 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.445267333 Jun 11 01:24:02 PM PDT 24 Jun 11 01:24:04 PM PDT 24 381975118 ps
T882 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2009128743 Jun 11 01:24:14 PM PDT 24 Jun 11 01:24:16 PM PDT 24 180654492 ps
T883 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1845462917 Jun 11 01:24:27 PM PDT 24 Jun 11 01:24:30 PM PDT 24 77805094 ps
T884 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.139547835 Jun 11 01:24:15 PM PDT 24 Jun 11 01:24:20 PM PDT 24 79854130 ps
T885 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2441786331 Jun 11 01:23:38 PM PDT 24 Jun 11 01:23:41 PM PDT 24 595967056 ps
T886 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.581722030 Jun 11 01:24:05 PM PDT 24 Jun 11 01:24:07 PM PDT 24 33290260 ps
T887 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2019388825 Jun 11 01:24:03 PM PDT 24 Jun 11 01:24:05 PM PDT 24 88335554 ps
T888 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.3579893861 Jun 11 01:24:25 PM PDT 24 Jun 11 01:24:27 PM PDT 24 169736985 ps
T889 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2821182293 Jun 11 01:23:51 PM PDT 24 Jun 11 01:23:53 PM PDT 24 154393927 ps
T890 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3320353891 Jun 11 01:24:04 PM PDT 24 Jun 11 01:24:07 PM PDT 24 1102337035 ps
T891 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2506406229 Jun 11 01:23:51 PM PDT 24 Jun 11 01:23:53 PM PDT 24 77920613 ps
T892 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2498522013 Jun 11 01:24:27 PM PDT 24 Jun 11 01:24:29 PM PDT 24 157935038 ps
T893 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1833563794 Jun 11 01:24:14 PM PDT 24 Jun 11 01:24:15 PM PDT 24 97625394 ps
T894 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4174664029 Jun 11 01:24:02 PM PDT 24 Jun 11 01:24:04 PM PDT 24 171600096 ps
T895 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2971361637 Jun 11 01:24:16 PM PDT 24 Jun 11 01:24:20 PM PDT 24 53923538 ps
T896 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2768097605 Jun 11 01:24:05 PM PDT 24 Jun 11 01:24:07 PM PDT 24 123250329 ps
T897 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1614099942 Jun 11 01:24:26 PM PDT 24 Jun 11 01:24:28 PM PDT 24 140121206 ps
T898 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2895745780 Jun 11 01:23:53 PM PDT 24 Jun 11 01:23:55 PM PDT 24 217660341 ps
T899 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1731211429 Jun 11 01:24:05 PM PDT 24 Jun 11 01:24:07 PM PDT 24 123363522 ps
T900 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1702814879 Jun 11 01:23:38 PM PDT 24 Jun 11 01:23:40 PM PDT 24 119371312 ps
T901 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2647691528 Jun 11 01:24:18 PM PDT 24 Jun 11 01:24:21 PM PDT 24 723560940 ps
T902 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1168165264 Jun 11 01:24:04 PM PDT 24 Jun 11 01:24:06 PM PDT 24 141381679 ps
T903 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1574846056 Jun 11 01:23:54 PM PDT 24 Jun 11 01:23:56 PM PDT 24 95416471 ps
T904 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.480875752 Jun 11 01:24:15 PM PDT 24 Jun 11 01:24:19 PM PDT 24 170709503 ps
T905 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3033537362 Jun 11 01:24:03 PM PDT 24 Jun 11 01:24:05 PM PDT 24 271841507 ps
T906 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3476994454 Jun 11 01:24:15 PM PDT 24 Jun 11 01:24:19 PM PDT 24 36356993 ps
T907 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2368061915 Jun 11 01:23:51 PM PDT 24 Jun 11 01:23:53 PM PDT 24 943376319 ps
T908 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2307879377 Jun 11 01:23:50 PM PDT 24 Jun 11 01:23:52 PM PDT 24 51978750 ps
T909 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.4225929667 Jun 11 01:23:37 PM PDT 24 Jun 11 01:23:39 PM PDT 24 521137885 ps
T910 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1292215603 Jun 11 01:24:17 PM PDT 24 Jun 11 01:24:21 PM PDT 24 116323633 ps
T911 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3520743166 Jun 11 01:24:15 PM PDT 24 Jun 11 01:24:20 PM PDT 24 142299713 ps
T912 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.169831198 Jun 11 01:23:51 PM PDT 24 Jun 11 01:23:53 PM PDT 24 38330231 ps
T913 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.124470984 Jun 11 01:24:15 PM PDT 24 Jun 11 01:24:19 PM PDT 24 333191999 ps
T914 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.2868579235 Jun 11 01:24:26 PM PDT 24 Jun 11 01:24:28 PM PDT 24 103108073 ps
T915 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1498379358 Jun 11 01:24:02 PM PDT 24 Jun 11 01:24:05 PM PDT 24 177822589 ps
T916 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2942431014 Jun 11 01:23:51 PM PDT 24 Jun 11 01:23:53 PM PDT 24 61466607 ps
T917 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.931008133 Jun 11 01:24:03 PM PDT 24 Jun 11 01:24:05 PM PDT 24 229101625 ps
T918 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1103923831 Jun 11 01:24:15 PM PDT 24 Jun 11 01:24:20 PM PDT 24 72825462 ps
T919 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2567248864 Jun 11 01:23:52 PM PDT 24 Jun 11 01:23:55 PM PDT 24 320302247 ps
T920 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3039366424 Jun 11 01:24:03 PM PDT 24 Jun 11 01:24:05 PM PDT 24 48147776 ps
T921 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.554160989 Jun 11 01:24:06 PM PDT 24 Jun 11 01:24:08 PM PDT 24 33930552 ps
T922 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3253649061 Jun 11 01:24:03 PM PDT 24 Jun 11 01:24:05 PM PDT 24 22861782 ps
T923 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.581025956 Jun 11 01:24:14 PM PDT 24 Jun 11 01:24:19 PM PDT 24 43766324 ps
T924 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2239296744 Jun 11 01:24:02 PM PDT 24 Jun 11 01:24:03 PM PDT 24 33005448 ps
T925 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3978951970 Jun 11 01:24:25 PM PDT 24 Jun 11 01:24:27 PM PDT 24 38025306 ps
T926 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3682018048 Jun 11 01:24:15 PM PDT 24 Jun 11 01:24:20 PM PDT 24 100469614 ps
T927 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1950703849 Jun 11 01:24:15 PM PDT 24 Jun 11 01:24:20 PM PDT 24 120749368 ps
T928 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1394191907 Jun 11 01:24:26 PM PDT 24 Jun 11 01:24:28 PM PDT 24 69198752 ps
T929 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2808560230 Jun 11 01:24:03 PM PDT 24 Jun 11 01:24:05 PM PDT 24 104503278 ps
T930 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.124916892 Jun 11 01:24:17 PM PDT 24 Jun 11 01:24:21 PM PDT 24 67304103 ps
T931 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1155913024 Jun 11 01:24:16 PM PDT 24 Jun 11 01:24:20 PM PDT 24 141534092 ps
T932 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.2305305221 Jun 11 01:24:14 PM PDT 24 Jun 11 01:24:18 PM PDT 24 214605143 ps
T933 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3731534467 Jun 11 01:24:05 PM PDT 24 Jun 11 01:24:07 PM PDT 24 319214405 ps
T934 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.483550334 Jun 11 01:24:03 PM PDT 24 Jun 11 01:24:06 PM PDT 24 67360835 ps
T935 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.4251705196 Jun 11 01:24:04 PM PDT 24 Jun 11 01:24:07 PM PDT 24 53970254 ps
T936 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2130726317 Jun 11 01:24:03 PM PDT 24 Jun 11 01:24:05 PM PDT 24 699452468 ps
T937 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.4154614523 Jun 11 01:24:15 PM PDT 24 Jun 11 01:24:20 PM PDT 24 51137578 ps
T938 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3431877312 Jun 11 01:24:14 PM PDT 24 Jun 11 01:24:16 PM PDT 24 288021175 ps
T939 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2414785081 Jun 11 01:23:52 PM PDT 24 Jun 11 01:23:54 PM PDT 24 53568796 ps

Test location /workspace/coverage/default/6.gpio_full_random.1731751853
Short name T28
Test name
Test status
Simulation time 190737133 ps
CPU time 0.78 seconds
Started Jun 11 12:27:22 PM PDT 24
Finished Jun 11 12:27:28 PM PDT 24
Peak memory 195832 kb
Host smart-e15a7890-c9fb-4d6c-9a9c-61e4b99cbfec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731751853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.1731751853
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.387041158
Short name T31
Test name
Test status
Simulation time 274780056 ps
CPU time 3.07 seconds
Started Jun 11 12:28:38 PM PDT 24
Finished Jun 11 12:28:42 PM PDT 24
Peak memory 198312 kb
Host smart-22fcfd74-fff4-40e9-8e14-c938bcd5893c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387041158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger.
387041158
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.3792746489
Short name T35
Test name
Test status
Simulation time 370557226 ps
CPU time 2.53 seconds
Started Jun 11 12:27:49 PM PDT 24
Finished Jun 11 12:27:54 PM PDT 24
Peak memory 197964 kb
Host smart-7cbc0400-c960-47e7-b390-957834a7f90b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792746489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.3792746489
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.2602998186
Short name T1
Test name
Test status
Simulation time 92115646910 ps
CPU time 814.79 seconds
Started Jun 11 12:27:48 PM PDT 24
Finished Jun 11 12:41:24 PM PDT 24
Peak memory 198132 kb
Host smart-7ac2866f-8d9f-4a44-81b4-59fa5a5fb3f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2602998186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.2602998186
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.2611446686
Short name T15
Test name
Test status
Simulation time 142428592 ps
CPU time 0.8 seconds
Started Jun 11 12:27:12 PM PDT 24
Finished Jun 11 12:27:16 PM PDT 24
Peak memory 213608 kb
Host smart-a160d9e8-0f56-4116-af1c-8e92938a9563
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611446686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.2611446686
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.1962193066
Short name T74
Test name
Test status
Simulation time 74476223 ps
CPU time 0.89 seconds
Started Jun 11 01:22:15 PM PDT 24
Finished Jun 11 01:22:17 PM PDT 24
Peak memory 196176 kb
Host smart-3268b955-5548-497e-a1ef-c8c7b420cf50
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962193066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.1962193066
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2331394533
Short name T49
Test name
Test status
Simulation time 185437053 ps
CPU time 1.36 seconds
Started Jun 11 01:22:25 PM PDT 24
Finished Jun 11 01:22:27 PM PDT 24
Peak memory 197996 kb
Host smart-781066c8-a170-4e23-8702-e34d47e40d9e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331394533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.2331394533
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.1836597146
Short name T29
Test name
Test status
Simulation time 898642694 ps
CPU time 3.59 seconds
Started Jun 11 12:27:46 PM PDT 24
Finished Jun 11 12:27:51 PM PDT 24
Peak memory 197864 kb
Host smart-f71599b6-66bd-4f06-bfe0-f5b03a41bcd9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836597146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.1836597146
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_alert_test.1954708477
Short name T174
Test name
Test status
Simulation time 23518925 ps
CPU time 0.55 seconds
Started Jun 11 12:27:41 PM PDT 24
Finished Jun 11 12:27:45 PM PDT 24
Peak memory 193752 kb
Host smart-b66fcb1f-3334-4d9c-9d87-c33758f61665
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954708477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.1954708477
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.927402212
Short name T96
Test name
Test status
Simulation time 24823590 ps
CPU time 0.68 seconds
Started Jun 11 01:21:50 PM PDT 24
Finished Jun 11 01:21:51 PM PDT 24
Peak memory 194984 kb
Host smart-17fd8e22-938c-45cf-9f86-a76ec9a05f3d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927402212 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.gpio_same_csr_outstanding.927402212
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.1242289745
Short name T89
Test name
Test status
Simulation time 29295378 ps
CPU time 0.62 seconds
Started Jun 11 01:23:12 PM PDT 24
Finished Jun 11 01:23:14 PM PDT 24
Peak memory 195204 kb
Host smart-8e860b77-bcb7-477c-9b2a-f10b2e1f39d8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242289745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.1242289745
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.539610653
Short name T787
Test name
Test status
Simulation time 128653482 ps
CPU time 1.39 seconds
Started Jun 11 01:22:46 PM PDT 24
Finished Jun 11 01:22:48 PM PDT 24
Peak memory 198028 kb
Host smart-4cad2b3c-ee21-4e6e-94a6-c18aacf9e6a0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539610653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.gpio_tl_intg_err.539610653
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3818845459
Short name T86
Test name
Test status
Simulation time 104922907 ps
CPU time 0.75 seconds
Started Jun 11 01:22:04 PM PDT 24
Finished Jun 11 01:22:06 PM PDT 24
Peak memory 195648 kb
Host smart-7476fdf2-d78b-44e7-b95d-5bd7a3df2566
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818845459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.3818845459
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3072460781
Short name T758
Test name
Test status
Simulation time 82484359 ps
CPU time 2.9 seconds
Started Jun 11 01:22:04 PM PDT 24
Finished Jun 11 01:22:08 PM PDT 24
Peak memory 196660 kb
Host smart-1baf5220-594e-463b-aacc-8ab73426efe1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072460781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.3072460781
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.3981599300
Short name T79
Test name
Test status
Simulation time 41441062 ps
CPU time 0.64 seconds
Started Jun 11 01:22:04 PM PDT 24
Finished Jun 11 01:22:05 PM PDT 24
Peak memory 194832 kb
Host smart-a365bb04-9685-488f-9f4a-abc87766ef0e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981599300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.3981599300
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1991744539
Short name T778
Test name
Test status
Simulation time 311093545 ps
CPU time 0.85 seconds
Started Jun 11 01:22:03 PM PDT 24
Finished Jun 11 01:22:05 PM PDT 24
Peak memory 197980 kb
Host smart-9d4f60cb-3eff-484a-b7fc-5e036371e485
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991744539 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.1991744539
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.3563005598
Short name T796
Test name
Test status
Simulation time 18578897 ps
CPU time 0.59 seconds
Started Jun 11 01:21:50 PM PDT 24
Finished Jun 11 01:21:52 PM PDT 24
Peak memory 193272 kb
Host smart-76e9788a-ba3a-4838-b3f4-6d868c33f19c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563005598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.3563005598
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.3142552955
Short name T799
Test name
Test status
Simulation time 29846571 ps
CPU time 0.68 seconds
Started Jun 11 01:22:03 PM PDT 24
Finished Jun 11 01:22:05 PM PDT 24
Peak memory 193912 kb
Host smart-b66e4b00-2aa5-4922-afd4-b1376feed5be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142552955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.3142552955
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2407698957
Short name T749
Test name
Test status
Simulation time 414731191 ps
CPU time 2.17 seconds
Started Jun 11 01:22:03 PM PDT 24
Finished Jun 11 01:22:06 PM PDT 24
Peak memory 197916 kb
Host smart-8dbcb8fa-789a-4777-b942-78f3dfd91bda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407698957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.2407698957
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.3768134644
Short name T46
Test name
Test status
Simulation time 49954661 ps
CPU time 0.95 seconds
Started Jun 11 01:22:05 PM PDT 24
Finished Jun 11 01:22:08 PM PDT 24
Peak memory 197256 kb
Host smart-b3b6d7d8-1dc9-4a3a-83f8-c44772e58bff
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768134644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.3768134644
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.525569505
Short name T85
Test name
Test status
Simulation time 19922280 ps
CPU time 0.64 seconds
Started Jun 11 01:22:04 PM PDT 24
Finished Jun 11 01:22:05 PM PDT 24
Peak memory 194112 kb
Host smart-b2f98925-fc6a-4b2b-8ec8-fd9c7490d777
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525569505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.gpio_csr_aliasing.525569505
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.3352683801
Short name T835
Test name
Test status
Simulation time 119396092 ps
CPU time 1.53 seconds
Started Jun 11 01:22:14 PM PDT 24
Finished Jun 11 01:22:16 PM PDT 24
Peak memory 198080 kb
Host smart-d29d46c5-af5e-4afb-aaee-f59dc00d1fa4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352683801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.3352683801
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.155922321
Short name T78
Test name
Test status
Simulation time 26439731 ps
CPU time 0.64 seconds
Started Jun 11 01:22:15 PM PDT 24
Finished Jun 11 01:22:17 PM PDT 24
Peak memory 195224 kb
Host smart-e1d047ad-12aa-4145-8e32-919f3e25371b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155922321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.155922321
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3897496536
Short name T782
Test name
Test status
Simulation time 161299150 ps
CPU time 1.04 seconds
Started Jun 11 01:22:14 PM PDT 24
Finished Jun 11 01:22:15 PM PDT 24
Peak memory 197980 kb
Host smart-fe508f60-2e08-40f7-a4e5-9c177a0d993a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897496536 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.3897496536
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.266166797
Short name T833
Test name
Test status
Simulation time 27682269 ps
CPU time 0.61 seconds
Started Jun 11 01:22:04 PM PDT 24
Finished Jun 11 01:22:05 PM PDT 24
Peak memory 194472 kb
Host smart-8f23f2b2-3fbf-4a47-b1fc-ce633993402a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266166797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_
csr_rw.266166797
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.670301422
Short name T756
Test name
Test status
Simulation time 33829941 ps
CPU time 0.58 seconds
Started Jun 11 01:22:14 PM PDT 24
Finished Jun 11 01:22:16 PM PDT 24
Peak memory 193636 kb
Host smart-03a19297-af81-465b-a9d3-de6d31ccc179
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670301422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.670301422
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.2138042779
Short name T95
Test name
Test status
Simulation time 39116627 ps
CPU time 0.66 seconds
Started Jun 11 01:22:04 PM PDT 24
Finished Jun 11 01:22:06 PM PDT 24
Peak memory 194440 kb
Host smart-af4a480c-dba1-4943-9c54-c6975d1b6e38
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138042779 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.2138042779
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3199679885
Short name T802
Test name
Test status
Simulation time 71362330 ps
CPU time 1.71 seconds
Started Jun 11 01:22:15 PM PDT 24
Finished Jun 11 01:22:18 PM PDT 24
Peak memory 197944 kb
Host smart-433adc95-6d88-4169-a3e2-b3ca55c1d4ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199679885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.3199679885
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.4031705160
Short name T40
Test name
Test status
Simulation time 260124810 ps
CPU time 1.11 seconds
Started Jun 11 01:22:15 PM PDT 24
Finished Jun 11 01:22:17 PM PDT 24
Peak memory 197508 kb
Host smart-0a514e37-806f-4f1f-80c7-096dca61e48f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031705160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.4031705160
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.4066883389
Short name T809
Test name
Test status
Simulation time 38062337 ps
CPU time 1.73 seconds
Started Jun 11 01:22:58 PM PDT 24
Finished Jun 11 01:23:01 PM PDT 24
Peak memory 198092 kb
Host smart-f5eb92c2-115d-4cf4-99c6-f43914e0489a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066883389 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.4066883389
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3723312284
Short name T88
Test name
Test status
Simulation time 152582115 ps
CPU time 0.61 seconds
Started Jun 11 01:22:57 PM PDT 24
Finished Jun 11 01:22:59 PM PDT 24
Peak memory 195312 kb
Host smart-88bbdb21-6b6f-4845-b902-e2900bd20b0b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723312284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.3723312284
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.3123992261
Short name T808
Test name
Test status
Simulation time 24386308 ps
CPU time 0.58 seconds
Started Jun 11 01:22:58 PM PDT 24
Finished Jun 11 01:23:00 PM PDT 24
Peak memory 193640 kb
Host smart-9055c4b2-12cb-46ef-8d13-44e346593d2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123992261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.3123992261
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.2926554934
Short name T817
Test name
Test status
Simulation time 59926787 ps
CPU time 0.87 seconds
Started Jun 11 01:22:59 PM PDT 24
Finished Jun 11 01:23:01 PM PDT 24
Peak memory 196276 kb
Host smart-e76070b2-b371-496e-b842-d385ca237225
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926554934 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.2926554934
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2397836733
Short name T786
Test name
Test status
Simulation time 110439663 ps
CPU time 2.33 seconds
Started Jun 11 01:22:58 PM PDT 24
Finished Jun 11 01:23:01 PM PDT 24
Peak memory 198184 kb
Host smart-1bccadd1-396c-445a-b9e8-a09e84f9deb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397836733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.2397836733
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.2014038243
Short name T806
Test name
Test status
Simulation time 70780258 ps
CPU time 1.06 seconds
Started Jun 11 01:22:58 PM PDT 24
Finished Jun 11 01:23:00 PM PDT 24
Peak memory 198000 kb
Host smart-76d89790-2dfe-4bde-8732-6e9e84b58ddc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014038243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.2014038243
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2087896135
Short name T781
Test name
Test status
Simulation time 313866482 ps
CPU time 1.93 seconds
Started Jun 11 01:22:57 PM PDT 24
Finished Jun 11 01:23:00 PM PDT 24
Peak memory 198024 kb
Host smart-dbcbe70c-13b5-4b95-9a2f-b2a82fc14ca1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087896135 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.2087896135
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.825475071
Short name T750
Test name
Test status
Simulation time 33382497 ps
CPU time 0.6 seconds
Started Jun 11 01:22:59 PM PDT 24
Finished Jun 11 01:23:00 PM PDT 24
Peak memory 194564 kb
Host smart-c3e24900-bc75-484f-b140-45d1dc85e26e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825475071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio
_csr_rw.825475071
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.842350317
Short name T811
Test name
Test status
Simulation time 54992535 ps
CPU time 0.61 seconds
Started Jun 11 01:22:58 PM PDT 24
Finished Jun 11 01:22:59 PM PDT 24
Peak memory 193652 kb
Host smart-ff5cb99b-16f9-437b-b783-b36697f8ab4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842350317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.842350317
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3987736590
Short name T831
Test name
Test status
Simulation time 109040309 ps
CPU time 0.69 seconds
Started Jun 11 01:22:59 PM PDT 24
Finished Jun 11 01:23:00 PM PDT 24
Peak memory 194784 kb
Host smart-2a6b8c1c-aca4-499d-bf46-2e86cd05e696
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987736590 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.3987736590
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.806951823
Short name T747
Test name
Test status
Simulation time 46617187 ps
CPU time 1.27 seconds
Started Jun 11 01:22:58 PM PDT 24
Finished Jun 11 01:23:00 PM PDT 24
Peak memory 197984 kb
Host smart-02d13f66-b6d5-4b70-8c02-b5cab4a209c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806951823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.806951823
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2601727643
Short name T39
Test name
Test status
Simulation time 189735627 ps
CPU time 0.9 seconds
Started Jun 11 01:22:59 PM PDT 24
Finished Jun 11 01:23:01 PM PDT 24
Peak memory 197836 kb
Host smart-02eba5bc-98db-4da5-93a7-60739c438a87
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601727643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.2601727643
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.913143170
Short name T836
Test name
Test status
Simulation time 108717235 ps
CPU time 0.85 seconds
Started Jun 11 01:22:59 PM PDT 24
Finished Jun 11 01:23:01 PM PDT 24
Peak memory 197972 kb
Host smart-4fb0951a-f09f-4ced-b6d5-cb491bc374dd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913143170 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.913143170
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.209985473
Short name T812
Test name
Test status
Simulation time 112228233 ps
CPU time 0.64 seconds
Started Jun 11 01:22:58 PM PDT 24
Finished Jun 11 01:22:59 PM PDT 24
Peak memory 194828 kb
Host smart-30874d5e-ab1f-4777-9da6-cda04db22658
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209985473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio
_csr_rw.209985473
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.625147111
Short name T735
Test name
Test status
Simulation time 21901489 ps
CPU time 0.61 seconds
Started Jun 11 01:23:00 PM PDT 24
Finished Jun 11 01:23:02 PM PDT 24
Peak memory 194360 kb
Host smart-3495bd56-7cd8-414f-8571-c2b6dad2fbc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625147111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.625147111
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.4277508455
Short name T77
Test name
Test status
Simulation time 17647898 ps
CPU time 0.72 seconds
Started Jun 11 01:23:00 PM PDT 24
Finished Jun 11 01:23:02 PM PDT 24
Peak memory 196028 kb
Host smart-ec1e7fc8-a413-4fc3-b708-9ea069e64aca
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277508455 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.4277508455
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1013725759
Short name T797
Test name
Test status
Simulation time 132440025 ps
CPU time 2.43 seconds
Started Jun 11 01:22:58 PM PDT 24
Finished Jun 11 01:23:01 PM PDT 24
Peak memory 197916 kb
Host smart-a8e282c4-3466-4971-a8f5-32d777954e8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013725759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.1013725759
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.259822542
Short name T38
Test name
Test status
Simulation time 116847275 ps
CPU time 1.48 seconds
Started Jun 11 01:23:00 PM PDT 24
Finished Jun 11 01:23:02 PM PDT 24
Peak memory 198048 kb
Host smart-0b8228cc-c67c-49b2-8b6c-0610d0882d98
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259822542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.gpio_tl_intg_err.259822542
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.3730893433
Short name T826
Test name
Test status
Simulation time 69387277 ps
CPU time 1.03 seconds
Started Jun 11 01:23:09 PM PDT 24
Finished Jun 11 01:23:10 PM PDT 24
Peak memory 197940 kb
Host smart-346e4078-2975-465e-afe4-c5d7af5704c2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730893433 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.3730893433
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3431820897
Short name T795
Test name
Test status
Simulation time 37816872 ps
CPU time 0.56 seconds
Started Jun 11 01:23:10 PM PDT 24
Finished Jun 11 01:23:12 PM PDT 24
Peak memory 193904 kb
Host smart-7f650dbb-28ba-4863-a5bf-aa8e4e10ae6a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431820897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.3431820897
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.2365506663
Short name T783
Test name
Test status
Simulation time 52392540 ps
CPU time 0.61 seconds
Started Jun 11 01:23:10 PM PDT 24
Finished Jun 11 01:23:11 PM PDT 24
Peak memory 193572 kb
Host smart-d7da423e-1f3e-4d40-b0f3-9a55f7e7c126
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365506663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.2365506663
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1248449623
Short name T819
Test name
Test status
Simulation time 60653399 ps
CPU time 0.69 seconds
Started Jun 11 01:23:11 PM PDT 24
Finished Jun 11 01:23:13 PM PDT 24
Peak memory 195132 kb
Host smart-6a46662e-e8ed-4a10-900c-a0115590bc7b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248449623 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.1248449623
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.2331077429
Short name T734
Test name
Test status
Simulation time 245214824 ps
CPU time 1.36 seconds
Started Jun 11 01:23:11 PM PDT 24
Finished Jun 11 01:23:14 PM PDT 24
Peak memory 197976 kb
Host smart-763f63e1-29dd-472c-b278-d5ffd0a3463b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331077429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.2331077429
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2470460339
Short name T50
Test name
Test status
Simulation time 89170852 ps
CPU time 0.86 seconds
Started Jun 11 01:23:13 PM PDT 24
Finished Jun 11 01:23:14 PM PDT 24
Peak memory 197252 kb
Host smart-1dd20a04-5aca-49a7-9029-c3e5e03dd06a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470460339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.2470460339
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.2723518956
Short name T780
Test name
Test status
Simulation time 37573063 ps
CPU time 0.91 seconds
Started Jun 11 01:23:09 PM PDT 24
Finished Jun 11 01:23:11 PM PDT 24
Peak memory 197988 kb
Host smart-0c6162a1-e181-46e8-8041-eded88bad553
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723518956 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.2723518956
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.3232208047
Short name T84
Test name
Test status
Simulation time 28351103 ps
CPU time 0.6 seconds
Started Jun 11 01:23:12 PM PDT 24
Finished Jun 11 01:23:13 PM PDT 24
Peak memory 194892 kb
Host smart-72518581-d891-4a28-a82c-3a3435952fed
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232208047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.3232208047
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.721023800
Short name T784
Test name
Test status
Simulation time 33201060 ps
CPU time 0.58 seconds
Started Jun 11 01:23:10 PM PDT 24
Finished Jun 11 01:23:12 PM PDT 24
Peak memory 193596 kb
Host smart-3e9b475d-802a-4d4b-8d3e-691967f17711
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721023800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.721023800
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.407863243
Short name T824
Test name
Test status
Simulation time 48607996 ps
CPU time 0.68 seconds
Started Jun 11 01:23:10 PM PDT 24
Finished Jun 11 01:23:11 PM PDT 24
Peak memory 194820 kb
Host smart-96f01f24-cdff-4d56-a850-31f3c8e96c2b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407863243 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 14.gpio_same_csr_outstanding.407863243
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2467698651
Short name T744
Test name
Test status
Simulation time 784253170 ps
CPU time 2.25 seconds
Started Jun 11 01:23:10 PM PDT 24
Finished Jun 11 01:23:13 PM PDT 24
Peak memory 197988 kb
Host smart-a8a4c2ee-c421-4a68-bcec-7b0783573e92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467698651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.2467698651
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.3076990992
Short name T112
Test name
Test status
Simulation time 128657250 ps
CPU time 1.16 seconds
Started Jun 11 01:23:12 PM PDT 24
Finished Jun 11 01:23:14 PM PDT 24
Peak memory 197972 kb
Host smart-e6af22c1-95cc-4937-99e9-9b0251c27f5f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076990992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.3076990992
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.3996587041
Short name T742
Test name
Test status
Simulation time 18765439 ps
CPU time 0.7 seconds
Started Jun 11 01:23:12 PM PDT 24
Finished Jun 11 01:23:14 PM PDT 24
Peak memory 197532 kb
Host smart-7f511401-e2f4-416d-8d1c-0a8feaf6ee13
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996587041 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.3996587041
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.331842218
Short name T790
Test name
Test status
Simulation time 13700593 ps
CPU time 0.63 seconds
Started Jun 11 01:23:11 PM PDT 24
Finished Jun 11 01:23:13 PM PDT 24
Peak memory 194340 kb
Host smart-caf825c3-e0df-418e-a696-218cd4602373
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331842218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.331842218
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.3054977825
Short name T80
Test name
Test status
Simulation time 20335392 ps
CPU time 0.83 seconds
Started Jun 11 01:23:11 PM PDT 24
Finished Jun 11 01:23:12 PM PDT 24
Peak memory 197004 kb
Host smart-c30a16ea-05b0-44dc-862b-1957d35e6d78
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054977825 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.3054977825
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.1334441445
Short name T757
Test name
Test status
Simulation time 272954612 ps
CPU time 2.51 seconds
Started Jun 11 01:23:09 PM PDT 24
Finished Jun 11 01:23:13 PM PDT 24
Peak memory 198072 kb
Host smart-e784a1b7-3235-47aa-b63f-d8055d1337c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334441445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.1334441445
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2390284523
Short name T51
Test name
Test status
Simulation time 119831933 ps
CPU time 1.52 seconds
Started Jun 11 01:23:12 PM PDT 24
Finished Jun 11 01:23:14 PM PDT 24
Peak memory 197948 kb
Host smart-2699caaf-4248-4d3d-88d0-389c2715e677
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390284523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.2390284523
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2218698594
Short name T769
Test name
Test status
Simulation time 562002782 ps
CPU time 0.84 seconds
Started Jun 11 01:23:10 PM PDT 24
Finished Jun 11 01:23:12 PM PDT 24
Peak memory 197828 kb
Host smart-7cd891dc-2813-4ff1-a09e-c38aca30a0b2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218698594 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.2218698594
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1688919999
Short name T93
Test name
Test status
Simulation time 14046707 ps
CPU time 0.61 seconds
Started Jun 11 01:23:11 PM PDT 24
Finished Jun 11 01:23:12 PM PDT 24
Peak memory 195744 kb
Host smart-c8e5dec2-fbdf-43a9-8b45-52c19bac4b9a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688919999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.1688919999
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.1520101391
Short name T776
Test name
Test status
Simulation time 17996311 ps
CPU time 0.63 seconds
Started Jun 11 01:23:27 PM PDT 24
Finished Jun 11 01:23:29 PM PDT 24
Peak memory 194568 kb
Host smart-dba3b295-87e5-4f5b-a744-468393212010
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520101391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.1520101391
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.861605103
Short name T828
Test name
Test status
Simulation time 15536862 ps
CPU time 0.67 seconds
Started Jun 11 01:23:12 PM PDT 24
Finished Jun 11 01:23:13 PM PDT 24
Peak memory 194772 kb
Host smart-0559506e-a956-4db5-9662-1d6405ef45aa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861605103 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 16.gpio_same_csr_outstanding.861605103
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.4000710547
Short name T715
Test name
Test status
Simulation time 536283051 ps
CPU time 2.9 seconds
Started Jun 11 01:23:11 PM PDT 24
Finished Jun 11 01:23:15 PM PDT 24
Peak memory 198048 kb
Host smart-d217fd61-7579-4e37-9c15-fa50261de5b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000710547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.4000710547
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.1744458292
Short name T814
Test name
Test status
Simulation time 552206134 ps
CPU time 1.4 seconds
Started Jun 11 01:23:12 PM PDT 24
Finished Jun 11 01:23:15 PM PDT 24
Peak memory 197976 kb
Host smart-c3df5363-d0c9-49f2-a6b9-ca57c3259af8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744458292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.1744458292
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.224561631
Short name T765
Test name
Test status
Simulation time 56639585 ps
CPU time 1.55 seconds
Started Jun 11 01:23:26 PM PDT 24
Finished Jun 11 01:23:28 PM PDT 24
Peak memory 198032 kb
Host smart-0c893402-58c3-4e1b-abb5-728d9fb34df6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224561631 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.224561631
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.1424438492
Short name T759
Test name
Test status
Simulation time 42761312 ps
CPU time 0.62 seconds
Started Jun 11 01:23:25 PM PDT 24
Finished Jun 11 01:23:26 PM PDT 24
Peak memory 195120 kb
Host smart-4bda8e84-6e4a-49f7-ad2c-02d722a2fbcf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424438492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.1424438492
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.1535389770
Short name T724
Test name
Test status
Simulation time 22170762 ps
CPU time 0.58 seconds
Started Jun 11 01:23:26 PM PDT 24
Finished Jun 11 01:23:27 PM PDT 24
Peak memory 193652 kb
Host smart-928f2c91-ce77-4f86-9643-65bdee4feec8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535389770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.1535389770
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3992951158
Short name T100
Test name
Test status
Simulation time 40016558 ps
CPU time 0.86 seconds
Started Jun 11 01:23:25 PM PDT 24
Finished Jun 11 01:23:27 PM PDT 24
Peak memory 196332 kb
Host smart-394dc0b0-bbd5-4a6d-b76b-b4052d82243f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992951158 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.3992951158
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1102893018
Short name T745
Test name
Test status
Simulation time 142933300 ps
CPU time 2.25 seconds
Started Jun 11 01:23:27 PM PDT 24
Finished Jun 11 01:23:30 PM PDT 24
Peak memory 197956 kb
Host smart-7a8fd901-5837-4172-82e3-cbb5ef3c7850
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102893018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.1102893018
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1424026968
Short name T810
Test name
Test status
Simulation time 353667282 ps
CPU time 0.89 seconds
Started Jun 11 01:23:25 PM PDT 24
Finished Jun 11 01:23:27 PM PDT 24
Peak memory 197224 kb
Host smart-46edcb32-1ddf-4cc7-84e4-9feccf0db444
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424026968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.1424026968
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3702628155
Short name T731
Test name
Test status
Simulation time 14173462 ps
CPU time 0.74 seconds
Started Jun 11 01:23:26 PM PDT 24
Finished Jun 11 01:23:28 PM PDT 24
Peak memory 197892 kb
Host smart-151c9fcc-af18-4665-9787-4c221cca1444
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702628155 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.3702628155
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3391100766
Short name T818
Test name
Test status
Simulation time 15589852 ps
CPU time 0.64 seconds
Started Jun 11 01:23:26 PM PDT 24
Finished Jun 11 01:23:28 PM PDT 24
Peak memory 195472 kb
Host smart-0070425a-e2c8-475d-9e15-434ae7b23d41
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391100766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.3391100766
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.147280094
Short name T777
Test name
Test status
Simulation time 14290694 ps
CPU time 0.63 seconds
Started Jun 11 01:23:27 PM PDT 24
Finished Jun 11 01:23:29 PM PDT 24
Peak memory 194252 kb
Host smart-60ad9e04-fd28-4c0c-ae81-bac3b4d90233
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147280094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.147280094
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3854411245
Short name T94
Test name
Test status
Simulation time 139301308 ps
CPU time 0.82 seconds
Started Jun 11 01:23:26 PM PDT 24
Finished Jun 11 01:23:28 PM PDT 24
Peak memory 196320 kb
Host smart-e588183b-f91e-4511-9d4f-f60d80a2d775
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854411245 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.3854411245
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3058855724
Short name T798
Test name
Test status
Simulation time 47489168 ps
CPU time 1.34 seconds
Started Jun 11 01:23:26 PM PDT 24
Finished Jun 11 01:23:28 PM PDT 24
Peak memory 198016 kb
Host smart-6cab37f7-20c6-4e7d-b9e0-197a902d4d40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058855724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.3058855724
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1910606255
Short name T800
Test name
Test status
Simulation time 83248813 ps
CPU time 1.18 seconds
Started Jun 11 01:23:27 PM PDT 24
Finished Jun 11 01:23:29 PM PDT 24
Peak memory 197992 kb
Host smart-a589a445-4ec8-409e-b3cf-e08a18848a29
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910606255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.1910606255
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.806149925
Short name T772
Test name
Test status
Simulation time 74193355 ps
CPU time 0.94 seconds
Started Jun 11 01:23:27 PM PDT 24
Finished Jun 11 01:23:29 PM PDT 24
Peak memory 197964 kb
Host smart-4c3a85bf-d8b8-478c-8ae0-5c4736e4e076
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806149925 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.806149925
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2660324269
Short name T91
Test name
Test status
Simulation time 24626984 ps
CPU time 0.59 seconds
Started Jun 11 01:23:28 PM PDT 24
Finished Jun 11 01:23:29 PM PDT 24
Peak memory 195316 kb
Host smart-e3a510bc-11dc-420c-8af9-e3f16eecaac9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660324269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.2660324269
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.3690720373
Short name T768
Test name
Test status
Simulation time 52314299 ps
CPU time 0.59 seconds
Started Jun 11 01:23:27 PM PDT 24
Finished Jun 11 01:23:28 PM PDT 24
Peak memory 193660 kb
Host smart-cd99978f-da74-415b-aba7-e676981ee201
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690720373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.3690720373
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3969944488
Short name T792
Test name
Test status
Simulation time 36794443 ps
CPU time 0.67 seconds
Started Jun 11 01:23:25 PM PDT 24
Finished Jun 11 01:23:27 PM PDT 24
Peak memory 195040 kb
Host smart-b2e28a20-50e5-45ee-839f-c31c4ecbe0a8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969944488 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.3969944488
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3436468641
Short name T717
Test name
Test status
Simulation time 54289967 ps
CPU time 1.46 seconds
Started Jun 11 01:23:26 PM PDT 24
Finished Jun 11 01:23:28 PM PDT 24
Peak memory 197980 kb
Host smart-368dea0b-97fa-4768-bf34-8fc72b6c81ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436468641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.3436468641
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.1419652196
Short name T111
Test name
Test status
Simulation time 315089680 ps
CPU time 1.42 seconds
Started Jun 11 01:23:27 PM PDT 24
Finished Jun 11 01:23:30 PM PDT 24
Peak memory 197992 kb
Host smart-9003c53e-8c7f-4b07-bc80-3437ee2a3277
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419652196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.1419652196
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2662625423
Short name T110
Test name
Test status
Simulation time 1180435619 ps
CPU time 3.32 seconds
Started Jun 11 01:22:24 PM PDT 24
Finished Jun 11 01:22:29 PM PDT 24
Peak memory 197100 kb
Host smart-ba4a2eb5-1577-4985-bc3e-3f2b7542c760
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662625423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.2662625423
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1162809517
Short name T737
Test name
Test status
Simulation time 15058876 ps
CPU time 0.62 seconds
Started Jun 11 01:22:26 PM PDT 24
Finished Jun 11 01:22:28 PM PDT 24
Peak memory 195292 kb
Host smart-448f6486-648c-44ac-839d-a15c9d02ee20
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162809517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.1162809517
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.3607841787
Short name T805
Test name
Test status
Simulation time 30496870 ps
CPU time 1.32 seconds
Started Jun 11 01:22:15 PM PDT 24
Finished Jun 11 01:22:18 PM PDT 24
Peak memory 198100 kb
Host smart-1ef72bfa-729c-4157-a4dc-10974c9acb5e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607841787 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.3607841787
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1138456604
Short name T779
Test name
Test status
Simulation time 41075119 ps
CPU time 0.61 seconds
Started Jun 11 01:22:14 PM PDT 24
Finished Jun 11 01:22:16 PM PDT 24
Peak memory 194664 kb
Host smart-249bfb26-3f66-4247-9db3-d4b9b657a5ea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138456604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.1138456604
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.3048672472
Short name T729
Test name
Test status
Simulation time 29285737 ps
CPU time 0.59 seconds
Started Jun 11 01:22:26 PM PDT 24
Finished Jun 11 01:22:27 PM PDT 24
Peak memory 194248 kb
Host smart-4f887376-0c66-4d37-a495-e949d236b61b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048672472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.3048672472
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2911430983
Short name T81
Test name
Test status
Simulation time 76619758 ps
CPU time 0.64 seconds
Started Jun 11 01:22:14 PM PDT 24
Finished Jun 11 01:22:16 PM PDT 24
Peak memory 195016 kb
Host smart-05d71161-dd38-4eea-80b5-ee0d7c4c547c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911430983 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.2911430983
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2481463671
Short name T738
Test name
Test status
Simulation time 478957153 ps
CPU time 2.76 seconds
Started Jun 11 01:22:25 PM PDT 24
Finished Jun 11 01:22:29 PM PDT 24
Peak memory 197972 kb
Host smart-b1108c7f-4888-4b9a-a80d-d0218be2fe4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481463671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.2481463671
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.1960195859
Short name T48
Test name
Test status
Simulation time 136384448 ps
CPU time 1.16 seconds
Started Jun 11 01:22:14 PM PDT 24
Finished Jun 11 01:22:16 PM PDT 24
Peak memory 197976 kb
Host smart-7eee1035-7760-414b-a53d-c2d00f324a53
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960195859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.1960195859
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.3244947901
Short name T834
Test name
Test status
Simulation time 18619824 ps
CPU time 0.63 seconds
Started Jun 11 01:23:29 PM PDT 24
Finished Jun 11 01:23:30 PM PDT 24
Peak memory 193752 kb
Host smart-11af6d77-70c8-41e8-bea8-f06834704283
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244947901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.3244947901
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.3669447092
Short name T773
Test name
Test status
Simulation time 13257395 ps
CPU time 0.59 seconds
Started Jun 11 01:23:25 PM PDT 24
Finished Jun 11 01:23:27 PM PDT 24
Peak memory 193716 kb
Host smart-c7173108-ca17-431c-b596-ce787f682bf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669447092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.3669447092
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.3174953294
Short name T725
Test name
Test status
Simulation time 12715701 ps
CPU time 0.59 seconds
Started Jun 11 01:23:28 PM PDT 24
Finished Jun 11 01:23:29 PM PDT 24
Peak memory 193664 kb
Host smart-ce21f126-ad13-4df3-b939-31d7d27e52c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174953294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.3174953294
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.4148851056
Short name T837
Test name
Test status
Simulation time 44260485 ps
CPU time 0.61 seconds
Started Jun 11 01:23:26 PM PDT 24
Finished Jun 11 01:23:28 PM PDT 24
Peak memory 193736 kb
Host smart-a2535371-7085-4351-ba4b-a43ac6539629
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148851056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.4148851056
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.3752252148
Short name T741
Test name
Test status
Simulation time 44595587 ps
CPU time 0.59 seconds
Started Jun 11 01:23:37 PM PDT 24
Finished Jun 11 01:23:39 PM PDT 24
Peak memory 193552 kb
Host smart-a679e65b-1956-4e18-8215-4c34b9172452
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752252148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.3752252148
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.2138444739
Short name T839
Test name
Test status
Simulation time 16191480 ps
CPU time 0.64 seconds
Started Jun 11 01:23:38 PM PDT 24
Finished Jun 11 01:23:40 PM PDT 24
Peak memory 193628 kb
Host smart-47537364-b802-4d51-b402-2308e73f2efd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138444739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.2138444739
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.4102216286
Short name T788
Test name
Test status
Simulation time 11487284 ps
CPU time 0.61 seconds
Started Jun 11 01:23:37 PM PDT 24
Finished Jun 11 01:23:39 PM PDT 24
Peak memory 193668 kb
Host smart-5b222f35-2256-473c-b821-24e2d9c3671b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102216286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.4102216286
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.3281016805
Short name T764
Test name
Test status
Simulation time 14596882 ps
CPU time 0.58 seconds
Started Jun 11 01:23:37 PM PDT 24
Finished Jun 11 01:23:39 PM PDT 24
Peak memory 194288 kb
Host smart-9bd164ce-69ae-431c-a208-a53231a4099b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281016805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.3281016805
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.535564201
Short name T823
Test name
Test status
Simulation time 23356707 ps
CPU time 0.57 seconds
Started Jun 11 01:23:39 PM PDT 24
Finished Jun 11 01:23:41 PM PDT 24
Peak memory 194276 kb
Host smart-11aace58-1bc4-4586-bbb5-9894efb88b69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535564201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.535564201
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.1996348680
Short name T816
Test name
Test status
Simulation time 41479578 ps
CPU time 0.58 seconds
Started Jun 11 01:23:35 PM PDT 24
Finished Jun 11 01:23:36 PM PDT 24
Peak memory 193596 kb
Host smart-0d03e0c7-036f-453b-84af-9a6c2cde0a23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996348680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.1996348680
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2627657078
Short name T87
Test name
Test status
Simulation time 22075120 ps
CPU time 0.83 seconds
Started Jun 11 01:22:27 PM PDT 24
Finished Jun 11 01:22:29 PM PDT 24
Peak memory 196024 kb
Host smart-286e2448-2167-4ff6-9396-68894e8dbf0a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627657078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.2627657078
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2901113023
Short name T92
Test name
Test status
Simulation time 260285334 ps
CPU time 2.61 seconds
Started Jun 11 01:22:25 PM PDT 24
Finished Jun 11 01:22:29 PM PDT 24
Peak memory 197028 kb
Host smart-216278f4-aa6a-499c-8c8d-7f0f7183fec3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901113023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.2901113023
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3048192405
Short name T76
Test name
Test status
Simulation time 31935856 ps
CPU time 0.63 seconds
Started Jun 11 01:22:25 PM PDT 24
Finished Jun 11 01:22:27 PM PDT 24
Peak memory 195160 kb
Host smart-8578c9a7-351f-4ae8-9f49-7d3435573c5d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048192405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.3048192405
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3482310101
Short name T789
Test name
Test status
Simulation time 51645466 ps
CPU time 1.07 seconds
Started Jun 11 01:22:26 PM PDT 24
Finished Jun 11 01:22:28 PM PDT 24
Peak memory 198000 kb
Host smart-816e938b-48f2-47c1-9b7c-8e5127a605b7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482310101 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.3482310101
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2874098825
Short name T804
Test name
Test status
Simulation time 14552096 ps
CPU time 0.6 seconds
Started Jun 11 01:22:26 PM PDT 24
Finished Jun 11 01:22:28 PM PDT 24
Peak memory 194496 kb
Host smart-2a6eda8f-bfc2-47f1-b49a-0b503b95bfbc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874098825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.2874098825
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.2994575067
Short name T754
Test name
Test status
Simulation time 34974837 ps
CPU time 0.61 seconds
Started Jun 11 01:22:26 PM PDT 24
Finished Jun 11 01:22:28 PM PDT 24
Peak memory 194304 kb
Host smart-d3c49d0a-d2cc-4775-b331-452ad3b641ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994575067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.2994575067
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3122687494
Short name T829
Test name
Test status
Simulation time 22471337 ps
CPU time 0.75 seconds
Started Jun 11 01:22:27 PM PDT 24
Finished Jun 11 01:22:29 PM PDT 24
Peak memory 195976 kb
Host smart-ea5c4c45-a4c0-495d-bb8e-6bc2d407ad7f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122687494 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.3122687494
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.2369023102
Short name T755
Test name
Test status
Simulation time 339946416 ps
CPU time 1.07 seconds
Started Jun 11 01:22:26 PM PDT 24
Finished Jun 11 01:22:28 PM PDT 24
Peak memory 197868 kb
Host smart-d451287e-ba5a-442e-b603-181cf17c191e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369023102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.2369023102
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.2907263408
Short name T748
Test name
Test status
Simulation time 14498332 ps
CPU time 0.63 seconds
Started Jun 11 01:23:36 PM PDT 24
Finished Jun 11 01:23:38 PM PDT 24
Peak memory 194328 kb
Host smart-8f9c77d1-13d9-4f9e-99ce-c2fbc3f59387
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907263408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.2907263408
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.2663701661
Short name T803
Test name
Test status
Simulation time 142097858 ps
CPU time 0.61 seconds
Started Jun 11 01:23:37 PM PDT 24
Finished Jun 11 01:23:38 PM PDT 24
Peak memory 194356 kb
Host smart-6bb18cbf-ccdf-4ed9-9a9d-71c55418262b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663701661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.2663701661
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.94439318
Short name T718
Test name
Test status
Simulation time 78510484 ps
CPU time 0.6 seconds
Started Jun 11 01:23:37 PM PDT 24
Finished Jun 11 01:23:38 PM PDT 24
Peak memory 193584 kb
Host smart-123a9472-c514-488f-82a7-2cb6d2e7c3db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94439318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.94439318
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.3978332163
Short name T794
Test name
Test status
Simulation time 14446332 ps
CPU time 0.6 seconds
Started Jun 11 01:23:36 PM PDT 24
Finished Jun 11 01:23:38 PM PDT 24
Peak memory 193632 kb
Host smart-4b45a7d8-c413-4014-9e84-4522c4373bab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978332163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.3978332163
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.2180715337
Short name T723
Test name
Test status
Simulation time 71686657 ps
CPU time 0.62 seconds
Started Jun 11 01:23:38 PM PDT 24
Finished Jun 11 01:23:40 PM PDT 24
Peak memory 193676 kb
Host smart-7ceeae56-028a-42be-a9a4-679242d955f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180715337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.2180715337
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.975090086
Short name T753
Test name
Test status
Simulation time 15610081 ps
CPU time 0.61 seconds
Started Jun 11 01:23:37 PM PDT 24
Finished Jun 11 01:23:39 PM PDT 24
Peak memory 193656 kb
Host smart-fcee4e60-0a77-41ac-a488-23ecf849ece4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975090086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.975090086
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.1019406409
Short name T730
Test name
Test status
Simulation time 38151076 ps
CPU time 0.6 seconds
Started Jun 11 01:23:37 PM PDT 24
Finished Jun 11 01:23:39 PM PDT 24
Peak memory 193688 kb
Host smart-846a7b73-a407-43d0-9db7-a9e094701297
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019406409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.1019406409
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.163375506
Short name T739
Test name
Test status
Simulation time 48581946 ps
CPU time 0.56 seconds
Started Jun 11 01:23:42 PM PDT 24
Finished Jun 11 01:23:43 PM PDT 24
Peak memory 193564 kb
Host smart-9efa095d-ce08-47e3-99b7-7fde2069537b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163375506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.163375506
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.1877985411
Short name T774
Test name
Test status
Simulation time 52941764 ps
CPU time 0.62 seconds
Started Jun 11 01:23:36 PM PDT 24
Finished Jun 11 01:23:37 PM PDT 24
Peak memory 193640 kb
Host smart-dd14bf27-3f58-4be9-8c04-11cf13c2dd8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877985411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.1877985411
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.1039844875
Short name T825
Test name
Test status
Simulation time 67320317 ps
CPU time 0.57 seconds
Started Jun 11 01:23:38 PM PDT 24
Finished Jun 11 01:23:40 PM PDT 24
Peak memory 194460 kb
Host smart-7914491a-7ed3-4205-a614-7f47cb7c016d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039844875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.1039844875
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2566844955
Short name T762
Test name
Test status
Simulation time 30726985 ps
CPU time 0.89 seconds
Started Jun 11 01:22:25 PM PDT 24
Finished Jun 11 01:22:28 PM PDT 24
Peak memory 196148 kb
Host smart-775255b3-60b3-41cc-8698-0a83a4284d66
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566844955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.2566844955
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2492817565
Short name T743
Test name
Test status
Simulation time 212735029 ps
CPU time 2.17 seconds
Started Jun 11 01:22:35 PM PDT 24
Finished Jun 11 01:22:38 PM PDT 24
Peak memory 196956 kb
Host smart-7b16212f-04a3-424f-adab-f79211ac7302
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492817565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.2492817565
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3703769663
Short name T770
Test name
Test status
Simulation time 15082241 ps
CPU time 0.62 seconds
Started Jun 11 01:22:37 PM PDT 24
Finished Jun 11 01:22:39 PM PDT 24
Peak memory 195208 kb
Host smart-04a8a99d-4aab-43c0-83e4-626a0fabd504
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703769663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.3703769663
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3052692831
Short name T727
Test name
Test status
Simulation time 90503647 ps
CPU time 0.85 seconds
Started Jun 11 01:22:25 PM PDT 24
Finished Jun 11 01:22:28 PM PDT 24
Peak memory 197888 kb
Host smart-9db6d9cf-e2e9-4c11-b8c1-fa06b6a7f11d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052692831 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.3052692831
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2534488344
Short name T83
Test name
Test status
Simulation time 19249216 ps
CPU time 0.61 seconds
Started Jun 11 01:22:25 PM PDT 24
Finished Jun 11 01:22:26 PM PDT 24
Peak memory 194836 kb
Host smart-3b00b232-74c2-47df-82e5-d431cd1abb6a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534488344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.2534488344
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.888275168
Short name T740
Test name
Test status
Simulation time 13299316 ps
CPU time 0.61 seconds
Started Jun 11 01:22:36 PM PDT 24
Finished Jun 11 01:22:37 PM PDT 24
Peak memory 193592 kb
Host smart-0a2f7df5-5d4b-419f-b62c-bdd87bfd9423
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888275168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.888275168
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2569809046
Short name T793
Test name
Test status
Simulation time 215034306 ps
CPU time 0.71 seconds
Started Jun 11 01:22:25 PM PDT 24
Finished Jun 11 01:22:27 PM PDT 24
Peak memory 195000 kb
Host smart-f8c73534-ac99-43cc-85ab-9b26c6a2b516
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569809046 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.2569809046
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1673449797
Short name T767
Test name
Test status
Simulation time 171556231 ps
CPU time 3.48 seconds
Started Jun 11 01:22:37 PM PDT 24
Finished Jun 11 01:22:41 PM PDT 24
Peak memory 197928 kb
Host smart-afc1f3aa-6be3-4a7d-a0be-8f7bf6df001f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673449797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.1673449797
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.4276802550
Short name T47
Test name
Test status
Simulation time 296182791 ps
CPU time 1.15 seconds
Started Jun 11 01:22:25 PM PDT 24
Finished Jun 11 01:22:27 PM PDT 24
Peak memory 197984 kb
Host smart-bfdb8975-ca1e-4474-927b-0b5478fa92aa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276802550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.4276802550
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.2892176438
Short name T716
Test name
Test status
Simulation time 16393225 ps
CPU time 0.58 seconds
Started Jun 11 01:23:36 PM PDT 24
Finished Jun 11 01:23:38 PM PDT 24
Peak memory 193652 kb
Host smart-33bd2aeb-6303-41ac-a244-5b647d8bb7e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892176438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.2892176438
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.1274003581
Short name T827
Test name
Test status
Simulation time 37772679 ps
CPU time 0.63 seconds
Started Jun 11 01:23:38 PM PDT 24
Finished Jun 11 01:23:40 PM PDT 24
Peak memory 193704 kb
Host smart-9dd287c7-dc7c-4d1b-9ec5-7b2c54388445
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274003581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.1274003581
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.3844675081
Short name T721
Test name
Test status
Simulation time 26247246 ps
CPU time 0.62 seconds
Started Jun 11 01:23:39 PM PDT 24
Finished Jun 11 01:23:41 PM PDT 24
Peak memory 193744 kb
Host smart-ded39c09-74c3-4ebd-b41a-e92ff23e6f86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844675081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.3844675081
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.1297228852
Short name T761
Test name
Test status
Simulation time 48466078 ps
CPU time 0.56 seconds
Started Jun 11 01:23:42 PM PDT 24
Finished Jun 11 01:23:43 PM PDT 24
Peak memory 194228 kb
Host smart-0b67167f-5cb0-431d-8940-df48bed58196
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297228852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.1297228852
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.3610865379
Short name T775
Test name
Test status
Simulation time 36206120 ps
CPU time 0.6 seconds
Started Jun 11 01:23:36 PM PDT 24
Finished Jun 11 01:23:37 PM PDT 24
Peak memory 194280 kb
Host smart-15394783-7f52-4c6c-b66e-e1c461da703e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610865379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.3610865379
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.2677847452
Short name T760
Test name
Test status
Simulation time 30098282 ps
CPU time 0.63 seconds
Started Jun 11 01:23:38 PM PDT 24
Finished Jun 11 01:23:40 PM PDT 24
Peak memory 193888 kb
Host smart-a25e9935-fd06-462e-9691-cfd0f4156365
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677847452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.2677847452
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.1895801629
Short name T820
Test name
Test status
Simulation time 38437809 ps
CPU time 0.58 seconds
Started Jun 11 01:23:38 PM PDT 24
Finished Jun 11 01:23:40 PM PDT 24
Peak memory 193676 kb
Host smart-98aef0f7-8213-430c-b583-d7894cdcf0c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895801629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.1895801629
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.521546971
Short name T732
Test name
Test status
Simulation time 24300950 ps
CPU time 0.59 seconds
Started Jun 11 01:23:37 PM PDT 24
Finished Jun 11 01:23:38 PM PDT 24
Peak memory 193648 kb
Host smart-66aafc02-d3e5-4dae-8789-fb2354976c40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521546971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.521546971
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.2930604329
Short name T821
Test name
Test status
Simulation time 55139970 ps
CPU time 0.6 seconds
Started Jun 11 01:23:38 PM PDT 24
Finished Jun 11 01:23:40 PM PDT 24
Peak memory 193676 kb
Host smart-64ac01d0-b8a9-46f2-94cb-1e1e962b5919
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930604329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.2930604329
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.1011485376
Short name T838
Test name
Test status
Simulation time 149087561 ps
CPU time 0.54 seconds
Started Jun 11 01:23:39 PM PDT 24
Finished Jun 11 01:23:41 PM PDT 24
Peak memory 193576 kb
Host smart-764a7546-0005-43c1-8187-05bb83ceb94b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011485376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.1011485376
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1021611031
Short name T801
Test name
Test status
Simulation time 34729652 ps
CPU time 0.96 seconds
Started Jun 11 01:22:37 PM PDT 24
Finished Jun 11 01:22:39 PM PDT 24
Peak memory 197932 kb
Host smart-6bfca25c-b763-48f9-9e37-89912708188a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021611031 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.1021611031
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1932326805
Short name T763
Test name
Test status
Simulation time 17164446 ps
CPU time 0.63 seconds
Started Jun 11 01:22:39 PM PDT 24
Finished Jun 11 01:22:40 PM PDT 24
Peak memory 194648 kb
Host smart-6c861883-34fa-42bf-b3eb-a01f1c5d6f76
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932326805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.1932326805
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.2912361065
Short name T807
Test name
Test status
Simulation time 13226023 ps
CPU time 0.67 seconds
Started Jun 11 01:22:37 PM PDT 24
Finished Jun 11 01:22:38 PM PDT 24
Peak memory 193712 kb
Host smart-f2a6ea71-00ff-4978-95ae-03e8cb8ef666
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912361065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.2912361065
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2192140298
Short name T98
Test name
Test status
Simulation time 42830072 ps
CPU time 0.81 seconds
Started Jun 11 01:22:36 PM PDT 24
Finished Jun 11 01:22:38 PM PDT 24
Peak memory 196252 kb
Host smart-7a477f3f-b0b8-4934-96c5-13c44838cdc3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192140298 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.2192140298
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.1150272556
Short name T752
Test name
Test status
Simulation time 282320946 ps
CPU time 1.5 seconds
Started Jun 11 01:22:36 PM PDT 24
Finished Jun 11 01:22:38 PM PDT 24
Peak memory 198000 kb
Host smart-2aed7656-cf6a-4328-aa62-05528cee898d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150272556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.1150272556
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3720671432
Short name T830
Test name
Test status
Simulation time 49681173 ps
CPU time 0.87 seconds
Started Jun 11 01:22:38 PM PDT 24
Finished Jun 11 01:22:39 PM PDT 24
Peak memory 196976 kb
Host smart-43e40e6b-ad15-4893-9b2b-12038324f1a3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720671432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.3720671432
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.3682132773
Short name T726
Test name
Test status
Simulation time 43839442 ps
CPU time 1.06 seconds
Started Jun 11 01:22:46 PM PDT 24
Finished Jun 11 01:22:47 PM PDT 24
Peak memory 198040 kb
Host smart-9377cbf1-eaf5-460e-a33d-c462efc3940c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682132773 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.3682132773
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1532098012
Short name T75
Test name
Test status
Simulation time 34370439 ps
CPU time 0.58 seconds
Started Jun 11 01:22:37 PM PDT 24
Finished Jun 11 01:22:39 PM PDT 24
Peak memory 193668 kb
Host smart-af86ff00-388a-4cc4-b351-ec9f6e6cadfe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532098012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.1532098012
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.767479929
Short name T751
Test name
Test status
Simulation time 25187080 ps
CPU time 0.61 seconds
Started Jun 11 01:22:47 PM PDT 24
Finished Jun 11 01:22:49 PM PDT 24
Peak memory 193692 kb
Host smart-6cfd53a2-0a39-4671-9afb-1bc8b4076265
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767479929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.767479929
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3068437813
Short name T822
Test name
Test status
Simulation time 20602072 ps
CPU time 0.66 seconds
Started Jun 11 01:22:48 PM PDT 24
Finished Jun 11 01:22:50 PM PDT 24
Peak memory 194400 kb
Host smart-1bee391d-2598-4f44-b4b6-5c6e16022079
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068437813 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.3068437813
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2100328722
Short name T746
Test name
Test status
Simulation time 69692712 ps
CPU time 1.35 seconds
Started Jun 11 01:22:49 PM PDT 24
Finished Jun 11 01:22:51 PM PDT 24
Peak memory 198004 kb
Host smart-1b5f2e84-ff0b-4204-a8c0-1012815455a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100328722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.2100328722
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1376387685
Short name T771
Test name
Test status
Simulation time 103748928 ps
CPU time 1.39 seconds
Started Jun 11 01:22:48 PM PDT 24
Finished Jun 11 01:22:51 PM PDT 24
Peak memory 198012 kb
Host smart-ed2dee09-2b29-4906-be3a-5e20d6feec14
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376387685 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.1376387685
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.242458882
Short name T82
Test name
Test status
Simulation time 12263845 ps
CPU time 0.59 seconds
Started Jun 11 01:22:47 PM PDT 24
Finished Jun 11 01:22:49 PM PDT 24
Peak memory 193844 kb
Host smart-328f81f6-b304-4807-95b8-8951a8d490ef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242458882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_
csr_rw.242458882
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.857152490
Short name T720
Test name
Test status
Simulation time 41502566 ps
CPU time 0.62 seconds
Started Jun 11 01:22:47 PM PDT 24
Finished Jun 11 01:22:49 PM PDT 24
Peak memory 194352 kb
Host smart-a7d3ae95-db70-4823-be8a-8180238d9cd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857152490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.857152490
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3000839558
Short name T97
Test name
Test status
Simulation time 42591767 ps
CPU time 0.91 seconds
Started Jun 11 01:22:47 PM PDT 24
Finished Jun 11 01:22:50 PM PDT 24
Peak memory 196224 kb
Host smart-54f0ce24-8927-4994-9d6d-29381e105a50
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000839558 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.3000839558
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.4102598287
Short name T766
Test name
Test status
Simulation time 214839111 ps
CPU time 2.29 seconds
Started Jun 11 01:22:48 PM PDT 24
Finished Jun 11 01:22:51 PM PDT 24
Peak memory 197968 kb
Host smart-cc349838-5a34-480b-8d94-02adde4f74ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102598287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.4102598287
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1597786769
Short name T832
Test name
Test status
Simulation time 770745789 ps
CPU time 1.5 seconds
Started Jun 11 01:22:47 PM PDT 24
Finished Jun 11 01:22:50 PM PDT 24
Peak memory 197992 kb
Host smart-b0d7ad38-2103-47a8-9a12-d39fb4ad9a27
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597786769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.1597786769
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.431886559
Short name T728
Test name
Test status
Simulation time 265274482 ps
CPU time 1.81 seconds
Started Jun 11 01:22:47 PM PDT 24
Finished Jun 11 01:22:49 PM PDT 24
Peak memory 198108 kb
Host smart-e2ad75e4-b2ca-4e14-bbd8-0d88e9b98f2a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431886559 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.431886559
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2330662400
Short name T733
Test name
Test status
Simulation time 15062700 ps
CPU time 0.61 seconds
Started Jun 11 01:22:47 PM PDT 24
Finished Jun 11 01:22:48 PM PDT 24
Peak memory 194688 kb
Host smart-bad25c60-8e0c-473a-9cd4-8ab045d54df9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330662400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.2330662400
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.2435454977
Short name T719
Test name
Test status
Simulation time 92270909 ps
CPU time 0.55 seconds
Started Jun 11 01:22:47 PM PDT 24
Finished Jun 11 01:22:49 PM PDT 24
Peak memory 193812 kb
Host smart-f63f9c19-8bdd-43ef-9b61-76ff5b8d2fd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435454977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.2435454977
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1767844264
Short name T785
Test name
Test status
Simulation time 26671997 ps
CPU time 0.78 seconds
Started Jun 11 01:22:49 PM PDT 24
Finished Jun 11 01:22:51 PM PDT 24
Peak memory 196436 kb
Host smart-a5e844cf-721f-48d7-bf4e-32b6b30f63c1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767844264 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.1767844264
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1391175005
Short name T722
Test name
Test status
Simulation time 115795918 ps
CPU time 2.55 seconds
Started Jun 11 01:22:48 PM PDT 24
Finished Jun 11 01:22:52 PM PDT 24
Peak memory 197972 kb
Host smart-4b9d9b62-0d3d-40d2-8440-038530e46273
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391175005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.1391175005
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2063736759
Short name T736
Test name
Test status
Simulation time 48419751 ps
CPU time 0.9 seconds
Started Jun 11 01:22:48 PM PDT 24
Finished Jun 11 01:22:51 PM PDT 24
Peak memory 197276 kb
Host smart-3654a5a2-77b3-4c59-b3c6-31984361e1fd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063736759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.2063736759
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.2506256770
Short name T813
Test name
Test status
Simulation time 112709729 ps
CPU time 1.51 seconds
Started Jun 11 01:22:48 PM PDT 24
Finished Jun 11 01:22:51 PM PDT 24
Peak memory 198036 kb
Host smart-bda583ea-dce1-4e04-94dc-ec7cc25c7278
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506256770 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.2506256770
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.4219340949
Short name T90
Test name
Test status
Simulation time 133068863 ps
CPU time 0.62 seconds
Started Jun 11 01:22:48 PM PDT 24
Finished Jun 11 01:22:50 PM PDT 24
Peak memory 194612 kb
Host smart-48271e96-b0ea-453f-aaf3-46de5c31210b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219340949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.4219340949
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.2078772132
Short name T815
Test name
Test status
Simulation time 47966070 ps
CPU time 0.58 seconds
Started Jun 11 01:22:58 PM PDT 24
Finished Jun 11 01:23:00 PM PDT 24
Peak memory 193624 kb
Host smart-204448ab-7fee-4c00-87d7-adadecf4d92f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078772132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.2078772132
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.1213770838
Short name T99
Test name
Test status
Simulation time 221095447 ps
CPU time 0.77 seconds
Started Jun 11 01:22:47 PM PDT 24
Finished Jun 11 01:22:49 PM PDT 24
Peak memory 196164 kb
Host smart-f7c4567f-9e90-46aa-80ba-3123647f8a1e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213770838 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.1213770838
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1160235771
Short name T791
Test name
Test status
Simulation time 136543644 ps
CPU time 1.96 seconds
Started Jun 11 01:22:47 PM PDT 24
Finished Jun 11 01:22:50 PM PDT 24
Peak memory 198008 kb
Host smart-1bda3e90-3392-4cd6-b11a-39751db7ba6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160235771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.1160235771
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1778876171
Short name T41
Test name
Test status
Simulation time 191094038 ps
CPU time 1.38 seconds
Started Jun 11 01:22:47 PM PDT 24
Finished Jun 11 01:22:50 PM PDT 24
Peak memory 197712 kb
Host smart-62ba1698-55dc-4543-ab3e-778e3681ee80
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778876171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.1778876171
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.1511956517
Short name T603
Test name
Test status
Simulation time 12407949 ps
CPU time 0.56 seconds
Started Jun 11 12:27:09 PM PDT 24
Finished Jun 11 12:27:11 PM PDT 24
Peak memory 194460 kb
Host smart-3b821756-92e4-41f7-86f9-93736cb62862
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511956517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.1511956517
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.101222523
Short name T713
Test name
Test status
Simulation time 25069134 ps
CPU time 0.8 seconds
Started Jun 11 12:26:59 PM PDT 24
Finished Jun 11 12:27:02 PM PDT 24
Peak memory 196136 kb
Host smart-2a0edf63-ce27-4797-b19c-ba88e7d38855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101222523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.101222523
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.1692590215
Short name T163
Test name
Test status
Simulation time 1806240853 ps
CPU time 12.96 seconds
Started Jun 11 12:27:10 PM PDT 24
Finished Jun 11 12:27:26 PM PDT 24
Peak memory 195472 kb
Host smart-32743f9a-b706-4aa1-951a-76ebd645aee7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692590215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.1692590215
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.1318346302
Short name T554
Test name
Test status
Simulation time 42833681 ps
CPU time 0.82 seconds
Started Jun 11 12:27:10 PM PDT 24
Finished Jun 11 12:27:14 PM PDT 24
Peak memory 196068 kb
Host smart-408d1a6e-7f1d-45d9-b2f8-c21b6d57a84d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318346302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.1318346302
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.1455711675
Short name T589
Test name
Test status
Simulation time 51029568 ps
CPU time 0.91 seconds
Started Jun 11 12:26:59 PM PDT 24
Finished Jun 11 12:27:02 PM PDT 24
Peak memory 197312 kb
Host smart-17c53e1f-5761-48ae-b2b1-2a8709b5bb1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455711675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.1455711675
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.1059380943
Short name T630
Test name
Test status
Simulation time 32811635 ps
CPU time 1.25 seconds
Started Jun 11 12:27:09 PM PDT 24
Finished Jun 11 12:27:12 PM PDT 24
Peak memory 197928 kb
Host smart-7fffb2cc-e645-44f0-9971-75c35ae7f513
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059380943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.1059380943
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.1008935347
Short name T613
Test name
Test status
Simulation time 252573235 ps
CPU time 2.46 seconds
Started Jun 11 12:27:01 PM PDT 24
Finished Jun 11 12:27:05 PM PDT 24
Peak memory 196416 kb
Host smart-30e6f440-fa39-4c4f-9287-9e50dab20597
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008935347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
1008935347
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.1052833388
Short name T566
Test name
Test status
Simulation time 139196043 ps
CPU time 0.9 seconds
Started Jun 11 12:26:59 PM PDT 24
Finished Jun 11 12:27:02 PM PDT 24
Peak memory 196324 kb
Host smart-86df7b51-a12b-4c57-b76d-1ba279f05a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052833388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.1052833388
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.450067444
Short name T464
Test name
Test status
Simulation time 165123861 ps
CPU time 0.96 seconds
Started Jun 11 12:27:01 PM PDT 24
Finished Jun 11 12:27:03 PM PDT 24
Peak memory 195864 kb
Host smart-253f0e45-2955-4c90-965e-497e9c0baf05
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450067444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup_
pulldown.450067444
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.3009937080
Short name T335
Test name
Test status
Simulation time 645868473 ps
CPU time 2.88 seconds
Started Jun 11 12:27:10 PM PDT 24
Finished Jun 11 12:27:16 PM PDT 24
Peak memory 197964 kb
Host smart-048c3f4d-0846-432c-b8ec-cbea219a6870
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009937080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.3009937080
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.2103274105
Short name T53
Test name
Test status
Simulation time 83946113 ps
CPU time 0.93 seconds
Started Jun 11 12:27:09 PM PDT 24
Finished Jun 11 12:27:12 PM PDT 24
Peak memory 214884 kb
Host smart-901c9fd7-4214-472d-8786-0bc370b4d14e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103274105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.2103274105
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.1795613794
Short name T237
Test name
Test status
Simulation time 262796787 ps
CPU time 1.41 seconds
Started Jun 11 12:27:01 PM PDT 24
Finished Jun 11 12:27:04 PM PDT 24
Peak memory 196616 kb
Host smart-516c0bcd-ff98-439d-bdb2-e21a8491d3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795613794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.1795613794
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.1707517509
Short name T68
Test name
Test status
Simulation time 54946889 ps
CPU time 1.06 seconds
Started Jun 11 12:26:58 PM PDT 24
Finished Jun 11 12:27:01 PM PDT 24
Peak memory 196216 kb
Host smart-c48055be-ace0-46e4-963d-443619167a78
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707517509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.1707517509
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.1271056955
Short name T488
Test name
Test status
Simulation time 71856778279 ps
CPU time 212.5 seconds
Started Jun 11 12:27:10 PM PDT 24
Finished Jun 11 12:30:45 PM PDT 24
Peak memory 198044 kb
Host smart-927e218f-3e9c-4a81-8085-f2f839af52f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271056955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.1271056955
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.2065662975
Short name T709
Test name
Test status
Simulation time 12216824 ps
CPU time 0.58 seconds
Started Jun 11 12:27:13 PM PDT 24
Finished Jun 11 12:27:16 PM PDT 24
Peak memory 193392 kb
Host smart-b162e78c-2337-44b3-baad-6e1f76eecfe6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065662975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.2065662975
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.1826502
Short name T588
Test name
Test status
Simulation time 17984315 ps
CPU time 0.66 seconds
Started Jun 11 12:27:13 PM PDT 24
Finished Jun 11 12:27:16 PM PDT 24
Peak memory 194000 kb
Host smart-b2d41b46-a833-4ecf-98d9-5bdabe793c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.1826502
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.2365130428
Short name T308
Test name
Test status
Simulation time 764536950 ps
CPU time 20.7 seconds
Started Jun 11 12:27:13 PM PDT 24
Finished Jun 11 12:27:36 PM PDT 24
Peak memory 196536 kb
Host smart-69ebb26b-459c-4c79-bcac-f763f3ff0141
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365130428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.2365130428
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.4132410924
Short name T136
Test name
Test status
Simulation time 43262932 ps
CPU time 0.74 seconds
Started Jun 11 12:27:12 PM PDT 24
Finished Jun 11 12:27:16 PM PDT 24
Peak memory 194652 kb
Host smart-56b1f9c7-4153-4ce9-9fff-cfbb4551f0be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132410924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.4132410924
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.1950654195
Short name T377
Test name
Test status
Simulation time 25266599 ps
CPU time 0.65 seconds
Started Jun 11 12:27:11 PM PDT 24
Finished Jun 11 12:27:15 PM PDT 24
Peak memory 194128 kb
Host smart-6e731547-719f-454d-955d-227c88f2beef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950654195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.1950654195
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.4104587888
Short name T366
Test name
Test status
Simulation time 70682775 ps
CPU time 1.56 seconds
Started Jun 11 12:27:09 PM PDT 24
Finished Jun 11 12:27:12 PM PDT 24
Peak memory 196516 kb
Host smart-5d2c7e94-79c8-4184-a6ea-a50bd0001b9b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104587888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.4104587888
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.3247604010
Short name T634
Test name
Test status
Simulation time 2120717134 ps
CPU time 2.76 seconds
Started Jun 11 12:27:11 PM PDT 24
Finished Jun 11 12:27:17 PM PDT 24
Peak memory 197120 kb
Host smart-bda58013-ebf9-421f-8563-3106f1199643
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247604010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
3247604010
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.250835570
Short name T567
Test name
Test status
Simulation time 24593139 ps
CPU time 0.93 seconds
Started Jun 11 12:27:09 PM PDT 24
Finished Jun 11 12:27:12 PM PDT 24
Peak memory 195784 kb
Host smart-85a77f3f-3b09-463a-bfee-d8f81e9ed90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250835570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.250835570
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.1697129243
Short name T456
Test name
Test status
Simulation time 18226622 ps
CPU time 0.79 seconds
Started Jun 11 12:27:10 PM PDT 24
Finished Jun 11 12:27:14 PM PDT 24
Peak memory 196232 kb
Host smart-deb42401-9fa4-4580-a551-7a6b2fae73d7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697129243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.1697129243
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.2347153209
Short name T472
Test name
Test status
Simulation time 366222014 ps
CPU time 1.83 seconds
Started Jun 11 12:27:11 PM PDT 24
Finished Jun 11 12:27:15 PM PDT 24
Peak memory 197768 kb
Host smart-b2b91381-7c68-44e1-9450-12ff0ff48771
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347153209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.2347153209
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.2533387091
Short name T52
Test name
Test status
Simulation time 131516014 ps
CPU time 0.77 seconds
Started Jun 11 12:27:10 PM PDT 24
Finished Jun 11 12:27:14 PM PDT 24
Peak memory 213716 kb
Host smart-db6f93d0-7ee9-4d5e-b9f7-3fb148f9f179
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533387091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.2533387091
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.1810927665
Short name T565
Test name
Test status
Simulation time 142295660 ps
CPU time 1.11 seconds
Started Jun 11 12:27:10 PM PDT 24
Finished Jun 11 12:27:13 PM PDT 24
Peak memory 196412 kb
Host smart-1f7c8d39-2d7a-4ddc-8874-ba68619293cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810927665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.1810927665
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.124104210
Short name T13
Test name
Test status
Simulation time 148042231 ps
CPU time 1.19 seconds
Started Jun 11 12:27:09 PM PDT 24
Finished Jun 11 12:27:12 PM PDT 24
Peak memory 196560 kb
Host smart-ee5bfcc0-7e58-40f9-ad6f-8eafeea4cb60
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124104210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.124104210
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.2962457756
Short name T703
Test name
Test status
Simulation time 2599868145 ps
CPU time 62.32 seconds
Started Jun 11 12:27:10 PM PDT 24
Finished Jun 11 12:28:15 PM PDT 24
Peak memory 198168 kb
Host smart-8f61f410-594b-4fcc-a810-c35c1ed2034d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962457756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.2962457756
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.2132580099
Short name T385
Test name
Test status
Simulation time 85913565 ps
CPU time 0.57 seconds
Started Jun 11 12:27:36 PM PDT 24
Finished Jun 11 12:27:42 PM PDT 24
Peak memory 194440 kb
Host smart-8c1beb31-3bae-437e-97c1-e44889a36865
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132580099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.2132580099
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.3195294256
Short name T218
Test name
Test status
Simulation time 22649329 ps
CPU time 0.64 seconds
Started Jun 11 12:27:28 PM PDT 24
Finished Jun 11 12:27:34 PM PDT 24
Peak memory 194016 kb
Host smart-1eb89b9f-86b2-43b8-a7b4-3ce0a82cc350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195294256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.3195294256
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.1406471813
Short name T268
Test name
Test status
Simulation time 507962601 ps
CPU time 13.39 seconds
Started Jun 11 12:27:26 PM PDT 24
Finished Jun 11 12:27:46 PM PDT 24
Peak memory 197884 kb
Host smart-ba1bf86c-51e8-46aa-851e-a5dd85ef9007
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406471813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.1406471813
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.49659590
Short name T198
Test name
Test status
Simulation time 105552890 ps
CPU time 0.62 seconds
Started Jun 11 12:27:33 PM PDT 24
Finished Jun 11 12:27:40 PM PDT 24
Peak memory 194100 kb
Host smart-36a9ced6-16a9-4978-9eaf-825b96c9be63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49659590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.49659590
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.2057502834
Short name T276
Test name
Test status
Simulation time 347773948 ps
CPU time 1.25 seconds
Started Jun 11 12:27:26 PM PDT 24
Finished Jun 11 12:27:33 PM PDT 24
Peak memory 195656 kb
Host smart-4556f78d-d88b-4de1-a1dc-53f58d563ea7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057502834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.2057502834
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.3877886667
Short name T708
Test name
Test status
Simulation time 81902293 ps
CPU time 1.73 seconds
Started Jun 11 12:27:28 PM PDT 24
Finished Jun 11 12:27:36 PM PDT 24
Peak memory 196520 kb
Host smart-480293e8-3bdd-4772-aff9-dfcdc3faf22c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877886667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.3877886667
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.3374752175
Short name T571
Test name
Test status
Simulation time 120296769 ps
CPU time 2.37 seconds
Started Jun 11 12:27:28 PM PDT 24
Finished Jun 11 12:27:36 PM PDT 24
Peak memory 195652 kb
Host smart-196e671f-7e74-4c9f-874d-edc1df54f5a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374752175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.3374752175
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.3332876021
Short name T463
Test name
Test status
Simulation time 32058636 ps
CPU time 0.8 seconds
Started Jun 11 12:27:29 PM PDT 24
Finished Jun 11 12:27:36 PM PDT 24
Peak memory 195328 kb
Host smart-a2a4cfb9-cdfd-49b3-8528-e6bf5d8635b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332876021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.3332876021
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.3122628505
Short name T179
Test name
Test status
Simulation time 285953639 ps
CPU time 1.29 seconds
Started Jun 11 12:27:26 PM PDT 24
Finished Jun 11 12:27:33 PM PDT 24
Peak memory 196776 kb
Host smart-1060a84d-b407-48a4-a78b-fdbab96766b1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122628505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.3122628505
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.2736561330
Short name T529
Test name
Test status
Simulation time 105824761 ps
CPU time 2.18 seconds
Started Jun 11 12:27:26 PM PDT 24
Finished Jun 11 12:27:34 PM PDT 24
Peak memory 197844 kb
Host smart-d1ce4433-da7c-4d9a-9d7a-88d0a9c2f31d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736561330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.2736561330
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.4147793891
Short name T109
Test name
Test status
Simulation time 78568680 ps
CPU time 0.9 seconds
Started Jun 11 12:27:29 PM PDT 24
Finished Jun 11 12:27:36 PM PDT 24
Peak memory 195524 kb
Host smart-af204499-c41d-44e4-8f1d-6bcde6c22c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147793891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.4147793891
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.2939748273
Short name T230
Test name
Test status
Simulation time 455006914 ps
CPU time 0.79 seconds
Started Jun 11 12:27:23 PM PDT 24
Finished Jun 11 12:27:29 PM PDT 24
Peak memory 195092 kb
Host smart-27be0113-cd0f-48cb-a024-8a3f4eedabec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939748273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.2939748273
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.3805815555
Short name T531
Test name
Test status
Simulation time 74132308734 ps
CPU time 190 seconds
Started Jun 11 12:27:33 PM PDT 24
Finished Jun 11 12:30:49 PM PDT 24
Peak memory 198140 kb
Host smart-cea86169-3426-4c22-8dd3-39e65225ed1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805815555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.3805815555
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.3260552119
Short name T448
Test name
Test status
Simulation time 49368022637 ps
CPU time 1127.58 seconds
Started Jun 11 12:27:35 PM PDT 24
Finished Jun 11 12:46:28 PM PDT 24
Peak memory 198128 kb
Host smart-54c2114d-6e2c-43f3-8a69-e700823b64b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3260552119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.3260552119
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.3160231057
Short name T693
Test name
Test status
Simulation time 24124133 ps
CPU time 0.55 seconds
Started Jun 11 12:27:34 PM PDT 24
Finished Jun 11 12:27:40 PM PDT 24
Peak memory 193828 kb
Host smart-a6de4996-1a71-4684-9373-738bdb164819
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160231057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.3160231057
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.1178598187
Short name T391
Test name
Test status
Simulation time 18651069 ps
CPU time 0.63 seconds
Started Jun 11 12:27:34 PM PDT 24
Finished Jun 11 12:27:40 PM PDT 24
Peak memory 194032 kb
Host smart-788d8893-865a-4042-b135-6a4185fff7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178598187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.1178598187
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.1446282119
Short name T265
Test name
Test status
Simulation time 2655735282 ps
CPU time 26.16 seconds
Started Jun 11 12:27:33 PM PDT 24
Finished Jun 11 12:28:05 PM PDT 24
Peak memory 196832 kb
Host smart-c3df86ac-3a83-4802-a887-7458f4d70f3c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446282119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.1446282119
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.3420136337
Short name T669
Test name
Test status
Simulation time 92156755 ps
CPU time 1.05 seconds
Started Jun 11 12:27:37 PM PDT 24
Finished Jun 11 12:27:43 PM PDT 24
Peak memory 196420 kb
Host smart-5612653e-751c-4819-be95-2f95c667b6ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420136337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.3420136337
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.249910829
Short name T503
Test name
Test status
Simulation time 41828502 ps
CPU time 1.14 seconds
Started Jun 11 12:27:35 PM PDT 24
Finished Jun 11 12:27:42 PM PDT 24
Peak memory 196168 kb
Host smart-2e032dd2-7a4d-4280-b9f4-5c01fce49946
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249910829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.249910829
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.589234810
Short name T582
Test name
Test status
Simulation time 218014797 ps
CPU time 2.43 seconds
Started Jun 11 12:27:33 PM PDT 24
Finished Jun 11 12:27:42 PM PDT 24
Peak memory 196356 kb
Host smart-360e045a-9c27-47bc-90dc-5fddc0726ef5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589234810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.gpio_intr_with_filter_rand_intr_event.589234810
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.3801183517
Short name T210
Test name
Test status
Simulation time 29502103 ps
CPU time 0.9 seconds
Started Jun 11 12:27:34 PM PDT 24
Finished Jun 11 12:27:41 PM PDT 24
Peak memory 195476 kb
Host smart-f7927400-7995-4480-9fb2-2437a93bb04b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801183517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.3801183517
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.1206367821
Short name T506
Test name
Test status
Simulation time 18827025 ps
CPU time 0.8 seconds
Started Jun 11 12:27:36 PM PDT 24
Finished Jun 11 12:27:42 PM PDT 24
Peak memory 195484 kb
Host smart-502a0b04-010c-45ae-8a59-3d004c4e85fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206367821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.1206367821
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.2135582074
Short name T244
Test name
Test status
Simulation time 56101655 ps
CPU time 0.83 seconds
Started Jun 11 12:27:34 PM PDT 24
Finished Jun 11 12:27:41 PM PDT 24
Peak memory 196616 kb
Host smart-ec765f0f-ddf7-4921-b32e-1d65f882e828
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135582074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.2135582074
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.3997958624
Short name T140
Test name
Test status
Simulation time 536343380 ps
CPU time 4.55 seconds
Started Jun 11 12:27:36 PM PDT 24
Finished Jun 11 12:27:46 PM PDT 24
Peak memory 197856 kb
Host smart-fda25978-7786-4899-b330-a12461710cfd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997958624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.3997958624
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.3677096622
Short name T115
Test name
Test status
Simulation time 310054926 ps
CPU time 1.4 seconds
Started Jun 11 12:27:32 PM PDT 24
Finished Jun 11 12:27:40 PM PDT 24
Peak memory 196528 kb
Host smart-4df9db6a-6424-4759-bad5-bc35d666dc1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677096622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.3677096622
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.1110465905
Short name T656
Test name
Test status
Simulation time 49055379 ps
CPU time 0.91 seconds
Started Jun 11 12:27:33 PM PDT 24
Finished Jun 11 12:27:40 PM PDT 24
Peak memory 195520 kb
Host smart-b2b6b187-a1bb-4c0b-9dc1-66205e1554f8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110465905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.1110465905
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.4109101726
Short name T383
Test name
Test status
Simulation time 13271207803 ps
CPU time 179.18 seconds
Started Jun 11 12:27:36 PM PDT 24
Finished Jun 11 12:30:40 PM PDT 24
Peak memory 198040 kb
Host smart-888ef92d-39d1-4786-9365-bd1f14ea62e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109101726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.4109101726
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.4175302925
Short name T441
Test name
Test status
Simulation time 34410341764 ps
CPU time 963.59 seconds
Started Jun 11 12:27:36 PM PDT 24
Finished Jun 11 12:43:44 PM PDT 24
Peak memory 198140 kb
Host smart-3c089afe-4328-4e97-a3f2-66fea18b6efd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4175302925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.4175302925
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.3212842421
Short name T219
Test name
Test status
Simulation time 10976220 ps
CPU time 0.6 seconds
Started Jun 11 12:27:34 PM PDT 24
Finished Jun 11 12:27:40 PM PDT 24
Peak memory 194496 kb
Host smart-583872f0-e91f-4065-a668-0f8fc4d48ef3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212842421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.3212842421
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.2410075125
Short name T122
Test name
Test status
Simulation time 42481782 ps
CPU time 0.67 seconds
Started Jun 11 12:27:35 PM PDT 24
Finished Jun 11 12:27:41 PM PDT 24
Peak memory 194912 kb
Host smart-db452e95-86f5-478f-b241-181568e9366d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410075125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.2410075125
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.493356692
Short name T413
Test name
Test status
Simulation time 1965219185 ps
CPU time 20.9 seconds
Started Jun 11 12:27:34 PM PDT 24
Finished Jun 11 12:28:00 PM PDT 24
Peak memory 196188 kb
Host smart-ffb8fb20-da23-4d0d-a900-5a9a50f02233
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493356692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stres
s.493356692
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.4238250246
Short name T695
Test name
Test status
Simulation time 55123961 ps
CPU time 0.82 seconds
Started Jun 11 12:27:33 PM PDT 24
Finished Jun 11 12:27:40 PM PDT 24
Peak memory 196384 kb
Host smart-f120ab72-835e-4625-901a-0d72393c7870
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238250246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.4238250246
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.3356786185
Short name T233
Test name
Test status
Simulation time 63111154 ps
CPU time 0.99 seconds
Started Jun 11 12:27:33 PM PDT 24
Finished Jun 11 12:27:40 PM PDT 24
Peak memory 195904 kb
Host smart-739af71b-eaf6-41e2-82f4-c30f1c0040c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356786185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.3356786185
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.687475393
Short name T224
Test name
Test status
Simulation time 243658955 ps
CPU time 2.58 seconds
Started Jun 11 12:27:32 PM PDT 24
Finished Jun 11 12:27:40 PM PDT 24
Peak memory 198020 kb
Host smart-9d372cb9-5a31-4b7c-bfcb-0f877adaa251
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687475393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.gpio_intr_with_filter_rand_intr_event.687475393
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.3405528725
Short name T521
Test name
Test status
Simulation time 125727393 ps
CPU time 2.57 seconds
Started Jun 11 12:27:35 PM PDT 24
Finished Jun 11 12:27:43 PM PDT 24
Peak memory 196456 kb
Host smart-8d70fe54-fd06-4b65-a3c4-dffb9476d06f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405528725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.3405528725
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.2929023736
Short name T705
Test name
Test status
Simulation time 76996375 ps
CPU time 0.82 seconds
Started Jun 11 12:27:35 PM PDT 24
Finished Jun 11 12:27:41 PM PDT 24
Peak memory 197088 kb
Host smart-63d059cc-90ee-490b-bee7-4fc072f950ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929023736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.2929023736
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.635154455
Short name T130
Test name
Test status
Simulation time 734835204 ps
CPU time 1.2 seconds
Started Jun 11 12:27:37 PM PDT 24
Finished Jun 11 12:27:44 PM PDT 24
Peak memory 195744 kb
Host smart-4a7f89f7-c37d-46b0-8779-52ed2fb61a20
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635154455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullup
_pulldown.635154455
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.1825395643
Short name T182
Test name
Test status
Simulation time 273744910 ps
CPU time 3.02 seconds
Started Jun 11 12:27:33 PM PDT 24
Finished Jun 11 12:27:42 PM PDT 24
Peak memory 197836 kb
Host smart-35e686e2-b746-4376-8b81-0f3f54660f5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825395643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.1825395643
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.3519708116
Short name T129
Test name
Test status
Simulation time 75450047 ps
CPU time 1.23 seconds
Started Jun 11 12:27:33 PM PDT 24
Finished Jun 11 12:27:40 PM PDT 24
Peak memory 197008 kb
Host smart-b10a3732-6250-4382-b14f-d1032f5c5206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519708116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.3519708116
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.3353756976
Short name T537
Test name
Test status
Simulation time 231191473 ps
CPU time 1.2 seconds
Started Jun 11 12:27:34 PM PDT 24
Finished Jun 11 12:27:41 PM PDT 24
Peak memory 196636 kb
Host smart-21b300bd-cbd3-4854-9a89-3dbd6b21a36f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353756976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.3353756976
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.772296151
Short name T213
Test name
Test status
Simulation time 52339778204 ps
CPU time 168.44 seconds
Started Jun 11 12:27:33 PM PDT 24
Finished Jun 11 12:30:27 PM PDT 24
Peak memory 198092 kb
Host smart-a7670561-6597-41e3-ac33-80f197cf516d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772296151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.g
pio_stress_all.772296151
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.2217641882
Short name T211
Test name
Test status
Simulation time 83740613 ps
CPU time 0.57 seconds
Started Jun 11 12:27:36 PM PDT 24
Finished Jun 11 12:27:41 PM PDT 24
Peak memory 193732 kb
Host smart-8151ab5a-c9a8-4bb3-80c8-8c28fa3ab533
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217641882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.2217641882
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.1938082493
Short name T121
Test name
Test status
Simulation time 221662159 ps
CPU time 0.66 seconds
Started Jun 11 12:27:33 PM PDT 24
Finished Jun 11 12:27:40 PM PDT 24
Peak memory 194448 kb
Host smart-43dd25d1-70e9-469d-bbf7-7f0a815e9a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938082493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.1938082493
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.3516827788
Short name T373
Test name
Test status
Simulation time 409190515 ps
CPU time 12.81 seconds
Started Jun 11 12:27:36 PM PDT 24
Finished Jun 11 12:27:54 PM PDT 24
Peak memory 197892 kb
Host smart-b0673c89-f1e4-435e-bc71-4b8a61d3f79e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516827788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.3516827788
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.4242834011
Short name T690
Test name
Test status
Simulation time 802430623 ps
CPU time 0.89 seconds
Started Jun 11 12:27:36 PM PDT 24
Finished Jun 11 12:27:42 PM PDT 24
Peak memory 197224 kb
Host smart-e93f31c1-6302-4bd8-9443-9d113b277a9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242834011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.4242834011
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.3879192951
Short name T141
Test name
Test status
Simulation time 81750810 ps
CPU time 1.32 seconds
Started Jun 11 12:27:35 PM PDT 24
Finished Jun 11 12:27:42 PM PDT 24
Peak memory 197016 kb
Host smart-c750243c-ee5c-4648-a826-95fe4c588c65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879192951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.3879192951
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.1614018064
Short name T330
Test name
Test status
Simulation time 99318105 ps
CPU time 2.69 seconds
Started Jun 11 12:27:35 PM PDT 24
Finished Jun 11 12:27:43 PM PDT 24
Peak memory 197988 kb
Host smart-ed4d5b2e-346d-4b3a-895a-a9a0ad637d9a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614018064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.1614018064
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.1634354506
Short name T664
Test name
Test status
Simulation time 81014893 ps
CPU time 2.22 seconds
Started Jun 11 12:27:35 PM PDT 24
Finished Jun 11 12:27:43 PM PDT 24
Peak memory 196916 kb
Host smart-2fe17a7c-caa6-4155-b2d7-58683c0058e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634354506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.1634354506
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.1883175888
Short name T593
Test name
Test status
Simulation time 25977985 ps
CPU time 0.92 seconds
Started Jun 11 12:27:38 PM PDT 24
Finished Jun 11 12:27:44 PM PDT 24
Peak memory 195956 kb
Host smart-b1f1367f-d755-4fd0-9a60-6c696064ecc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883175888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.1883175888
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.998995152
Short name T592
Test name
Test status
Simulation time 94373155 ps
CPU time 0.7 seconds
Started Jun 11 12:27:37 PM PDT 24
Finished Jun 11 12:27:43 PM PDT 24
Peak memory 194316 kb
Host smart-1b41b732-10d3-4957-98b0-62b464b29820
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998995152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullup
_pulldown.998995152
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.2472778929
Short name T513
Test name
Test status
Simulation time 191297953 ps
CPU time 1.39 seconds
Started Jun 11 12:27:34 PM PDT 24
Finished Jun 11 12:27:41 PM PDT 24
Peak memory 197852 kb
Host smart-04c5de5a-022a-4b6a-9c5b-cf2709c775fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472778929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.2472778929
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.859862714
Short name T152
Test name
Test status
Simulation time 326507592 ps
CPU time 1.23 seconds
Started Jun 11 12:27:34 PM PDT 24
Finished Jun 11 12:27:41 PM PDT 24
Peak memory 196388 kb
Host smart-d7112542-bdb4-4d9b-b0b2-c3ba17908018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859862714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.859862714
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.3582356887
Short name T202
Test name
Test status
Simulation time 116085465 ps
CPU time 1.01 seconds
Started Jun 11 12:27:36 PM PDT 24
Finished Jun 11 12:27:42 PM PDT 24
Peak memory 195660 kb
Host smart-fb5294a9-9608-4b30-8241-dae7394511cb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582356887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.3582356887
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.4018920850
Short name T6
Test name
Test status
Simulation time 7796235960 ps
CPU time 81.34 seconds
Started Jun 11 12:27:37 PM PDT 24
Finished Jun 11 12:29:04 PM PDT 24
Peak memory 198080 kb
Host smart-38b1639c-28a7-4311-9f40-c8a319c107d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018920850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.4018920850
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.442125498
Short name T37
Test name
Test status
Simulation time 418725199341 ps
CPU time 2055.95 seconds
Started Jun 11 12:27:36 PM PDT 24
Finished Jun 11 01:01:57 PM PDT 24
Peak memory 198180 kb
Host smart-9fccc69a-88ad-4a8f-a69b-ea40d5923093
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=442125498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.442125498
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.826145505
Short name T404
Test name
Test status
Simulation time 119400725 ps
CPU time 0.72 seconds
Started Jun 11 12:27:37 PM PDT 24
Finished Jun 11 12:27:43 PM PDT 24
Peak memory 195172 kb
Host smart-8e27e632-5042-4b83-8f5f-b3c083a5c9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826145505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.826145505
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.1895453725
Short name T204
Test name
Test status
Simulation time 859079304 ps
CPU time 10.32 seconds
Started Jun 11 12:27:40 PM PDT 24
Finished Jun 11 12:27:54 PM PDT 24
Peak memory 196088 kb
Host smart-d2695ff2-3e6d-49ee-88dd-3677f9c705c3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895453725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.1895453725
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.1272464655
Short name T133
Test name
Test status
Simulation time 68459817 ps
CPU time 0.74 seconds
Started Jun 11 12:27:39 PM PDT 24
Finished Jun 11 12:27:44 PM PDT 24
Peak memory 195336 kb
Host smart-0d443421-33d1-4309-964d-0fdab4489e6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272464655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.1272464655
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.2922527061
Short name T557
Test name
Test status
Simulation time 20116767 ps
CPU time 0.69 seconds
Started Jun 11 12:27:34 PM PDT 24
Finished Jun 11 12:27:40 PM PDT 24
Peak memory 194348 kb
Host smart-258c6f66-6b2f-465b-b160-18db1453e109
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922527061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.2922527061
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.613257106
Short name T668
Test name
Test status
Simulation time 180338201 ps
CPU time 3.62 seconds
Started Jun 11 12:27:42 PM PDT 24
Finished Jun 11 12:27:48 PM PDT 24
Peak memory 198008 kb
Host smart-23cabc93-68a1-418d-b1e4-139be1cceaac
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613257106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.gpio_intr_with_filter_rand_intr_event.613257106
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.4248281276
Short name T259
Test name
Test status
Simulation time 112196505 ps
CPU time 1.09 seconds
Started Jun 11 12:27:42 PM PDT 24
Finished Jun 11 12:27:46 PM PDT 24
Peak memory 196552 kb
Host smart-59448088-3305-4355-aee2-d2a01f9050fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248281276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.4248281276
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.847279347
Short name T642
Test name
Test status
Simulation time 68992184 ps
CPU time 0.95 seconds
Started Jun 11 12:27:36 PM PDT 24
Finished Jun 11 12:27:42 PM PDT 24
Peak memory 195580 kb
Host smart-7036dd59-b49d-46fa-bae4-233466ca06b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847279347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.847279347
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.2842067555
Short name T207
Test name
Test status
Simulation time 78185675 ps
CPU time 0.87 seconds
Started Jun 11 12:27:34 PM PDT 24
Finished Jun 11 12:27:40 PM PDT 24
Peak memory 196652 kb
Host smart-996d586e-7b88-4b2c-a244-8b7f0e33a653
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842067555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.2842067555
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.4034098152
Short name T550
Test name
Test status
Simulation time 1920999560 ps
CPU time 2.76 seconds
Started Jun 11 12:27:36 PM PDT 24
Finished Jun 11 12:27:44 PM PDT 24
Peak memory 197780 kb
Host smart-ead87962-90ae-4802-89e2-a721f2b2da36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034098152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.4034098152
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.298432646
Short name T511
Test name
Test status
Simulation time 70421671 ps
CPU time 0.92 seconds
Started Jun 11 12:27:35 PM PDT 24
Finished Jun 11 12:27:41 PM PDT 24
Peak memory 195756 kb
Host smart-9599b639-bd10-4f36-9191-3addef114a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298432646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.298432646
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.1839649418
Short name T54
Test name
Test status
Simulation time 49610004 ps
CPU time 1.23 seconds
Started Jun 11 12:27:39 PM PDT 24
Finished Jun 11 12:27:45 PM PDT 24
Peak memory 196768 kb
Host smart-f8eb12fb-09ea-4176-b6f6-67c5f944a3a6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839649418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.1839649418
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.639696799
Short name T339
Test name
Test status
Simulation time 30635841506 ps
CPU time 198.4 seconds
Started Jun 11 12:27:40 PM PDT 24
Finished Jun 11 12:31:03 PM PDT 24
Peak memory 197980 kb
Host smart-28774792-d2fb-419d-b1ae-2d7166b21212
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639696799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.g
pio_stress_all.639696799
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.3104030510
Short name T657
Test name
Test status
Simulation time 192018298719 ps
CPU time 771.74 seconds
Started Jun 11 12:27:37 PM PDT 24
Finished Jun 11 12:40:34 PM PDT 24
Peak memory 198192 kb
Host smart-ff981bf6-6367-4af9-8ddb-d0ed85b05a5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3104030510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.3104030510
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.598401403
Short name T561
Test name
Test status
Simulation time 22934530 ps
CPU time 0.57 seconds
Started Jun 11 12:27:38 PM PDT 24
Finished Jun 11 12:27:44 PM PDT 24
Peak memory 193748 kb
Host smart-8706b843-baf6-40fe-aa10-a6801b702b5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598401403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.598401403
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.3047621974
Short name T299
Test name
Test status
Simulation time 75416041 ps
CPU time 0.88 seconds
Started Jun 11 12:27:42 PM PDT 24
Finished Jun 11 12:27:46 PM PDT 24
Peak memory 195728 kb
Host smart-6580b124-2498-4f36-b9a3-386690a43cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047621974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.3047621974
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.3744109886
Short name T627
Test name
Test status
Simulation time 377878588 ps
CPU time 12.71 seconds
Started Jun 11 12:27:38 PM PDT 24
Finished Jun 11 12:27:56 PM PDT 24
Peak memory 197944 kb
Host smart-dd1e039b-af32-44cf-8c0c-058c84f81c32
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744109886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.3744109886
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.1610512805
Short name T624
Test name
Test status
Simulation time 207728388 ps
CPU time 0.8 seconds
Started Jun 11 12:27:34 PM PDT 24
Finished Jun 11 12:27:41 PM PDT 24
Peak memory 195936 kb
Host smart-ded73976-ed1a-47de-a791-008c7cf4a0e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610512805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.1610512805
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.3281805756
Short name T601
Test name
Test status
Simulation time 102669055 ps
CPU time 1.34 seconds
Started Jun 11 12:27:36 PM PDT 24
Finished Jun 11 12:27:42 PM PDT 24
Peak memory 195736 kb
Host smart-d6cab145-51d8-45e8-b18c-04c84658e71a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281805756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.3281805756
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.4255636003
Short name T291
Test name
Test status
Simulation time 81647751 ps
CPU time 2.41 seconds
Started Jun 11 12:27:37 PM PDT 24
Finished Jun 11 12:27:44 PM PDT 24
Peak memory 197956 kb
Host smart-3b1401a1-7915-4882-9ba9-685b5d9c36de
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255636003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.4255636003
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.4152949697
Short name T545
Test name
Test status
Simulation time 358764330 ps
CPU time 2.05 seconds
Started Jun 11 12:27:36 PM PDT 24
Finished Jun 11 12:27:44 PM PDT 24
Peak memory 197196 kb
Host smart-39957746-16a9-4fda-9db1-0bd5f9bee497
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152949697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.4152949697
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.3991465038
Short name T206
Test name
Test status
Simulation time 43872437 ps
CPU time 1.01 seconds
Started Jun 11 12:27:35 PM PDT 24
Finished Jun 11 12:27:42 PM PDT 24
Peak memory 195644 kb
Host smart-8e26fd7d-34bb-452d-93bc-45eac208ef20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991465038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.3991465038
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3282227238
Short name T423
Test name
Test status
Simulation time 55505997 ps
CPU time 0.75 seconds
Started Jun 11 12:27:34 PM PDT 24
Finished Jun 11 12:27:41 PM PDT 24
Peak memory 196192 kb
Host smart-a265887b-3744-4a3f-b057-3960d60fedb7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282227238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3282227238
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.366893002
Short name T393
Test name
Test status
Simulation time 1659860449 ps
CPU time 5.41 seconds
Started Jun 11 12:27:38 PM PDT 24
Finished Jun 11 12:27:48 PM PDT 24
Peak memory 197584 kb
Host smart-9e5c71cf-2e16-46cf-b12f-7811646ccd56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366893002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ran
dom_long_reg_writes_reg_reads.366893002
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.3794219817
Short name T409
Test name
Test status
Simulation time 125563617 ps
CPU time 1.24 seconds
Started Jun 11 12:27:39 PM PDT 24
Finished Jun 11 12:27:45 PM PDT 24
Peak memory 196428 kb
Host smart-b48d693c-4d5e-4e97-a405-3c4a2f079661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794219817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.3794219817
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.3874253456
Short name T497
Test name
Test status
Simulation time 49739182 ps
CPU time 1.06 seconds
Started Jun 11 12:27:39 PM PDT 24
Finished Jun 11 12:27:45 PM PDT 24
Peak memory 195688 kb
Host smart-812bf6c2-cbdf-4a3f-b44c-18131ef305d1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874253456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.3874253456
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.1857376743
Short name T671
Test name
Test status
Simulation time 8266728780 ps
CPU time 210.72 seconds
Started Jun 11 12:27:38 PM PDT 24
Finished Jun 11 12:31:13 PM PDT 24
Peak memory 198148 kb
Host smart-6239ef0e-eb72-433e-8e66-a165b1552990
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857376743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.1857376743
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.2962309246
Short name T167
Test name
Test status
Simulation time 12034811 ps
CPU time 0.55 seconds
Started Jun 11 12:27:45 PM PDT 24
Finished Jun 11 12:27:46 PM PDT 24
Peak memory 193780 kb
Host smart-0de29ab3-9cb0-4cd6-9d65-a6baf7372a48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962309246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.2962309246
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.3545502334
Short name T569
Test name
Test status
Simulation time 23690829 ps
CPU time 0.7 seconds
Started Jun 11 12:27:36 PM PDT 24
Finished Jun 11 12:27:41 PM PDT 24
Peak memory 194144 kb
Host smart-6ded8d26-40e4-4dee-a78a-51717506fb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545502334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.3545502334
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.2675608645
Short name T573
Test name
Test status
Simulation time 363829524 ps
CPU time 19.02 seconds
Started Jun 11 12:27:35 PM PDT 24
Finished Jun 11 12:28:00 PM PDT 24
Peak memory 195440 kb
Host smart-b47c159f-a5c6-49fe-8627-88e42f4a18bf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675608645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.2675608645
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.4195339962
Short name T568
Test name
Test status
Simulation time 484649787 ps
CPU time 0.81 seconds
Started Jun 11 12:27:45 PM PDT 24
Finished Jun 11 12:27:48 PM PDT 24
Peak memory 196024 kb
Host smart-37b993ac-d063-4eb7-aa5a-2498689d9615
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195339962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.4195339962
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.1435241906
Short name T266
Test name
Test status
Simulation time 100298319 ps
CPU time 0.74 seconds
Started Jun 11 12:27:37 PM PDT 24
Finished Jun 11 12:27:43 PM PDT 24
Peak memory 195988 kb
Host smart-b4cacf19-f22f-4543-9cca-2a95b159bfe4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435241906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.1435241906
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.320866834
Short name T444
Test name
Test status
Simulation time 623965911 ps
CPU time 2.6 seconds
Started Jun 11 12:27:40 PM PDT 24
Finished Jun 11 12:27:47 PM PDT 24
Peak memory 197856 kb
Host smart-babf8987-71a9-4e8a-830d-3041d514fcc2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320866834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.gpio_intr_with_filter_rand_intr_event.320866834
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.2033309079
Short name T516
Test name
Test status
Simulation time 186718814 ps
CPU time 1.28 seconds
Started Jun 11 12:27:38 PM PDT 24
Finished Jun 11 12:27:44 PM PDT 24
Peak memory 197240 kb
Host smart-06bff151-52e6-4222-81ac-7ecf3fa027bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033309079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.2033309079
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.907879677
Short name T403
Test name
Test status
Simulation time 62783336 ps
CPU time 1.27 seconds
Started Jun 11 12:27:40 PM PDT 24
Finished Jun 11 12:27:45 PM PDT 24
Peak memory 197920 kb
Host smart-76378c1f-a065-4560-9c79-32dff3c8e7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907879677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.907879677
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.2704019348
Short name T585
Test name
Test status
Simulation time 44564710 ps
CPU time 1.05 seconds
Started Jun 11 12:27:36 PM PDT 24
Finished Jun 11 12:27:42 PM PDT 24
Peak memory 195992 kb
Host smart-0e31a621-e200-4f46-bb65-b34b093975f6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704019348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.2704019348
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.241621700
Short name T396
Test name
Test status
Simulation time 265713347 ps
CPU time 4.02 seconds
Started Jun 11 12:27:40 PM PDT 24
Finished Jun 11 12:27:48 PM PDT 24
Peak memory 197868 kb
Host smart-9f810cd8-630b-467a-b738-877a80804922
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241621700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ran
dom_long_reg_writes_reg_reads.241621700
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.916346172
Short name T58
Test name
Test status
Simulation time 86799958 ps
CPU time 1.37 seconds
Started Jun 11 12:27:40 PM PDT 24
Finished Jun 11 12:27:45 PM PDT 24
Peak memory 196700 kb
Host smart-71703dab-2135-4d9b-b0fd-758c331b4dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916346172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.916346172
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.825451225
Short name T264
Test name
Test status
Simulation time 92368318 ps
CPU time 0.7 seconds
Started Jun 11 12:27:39 PM PDT 24
Finished Jun 11 12:27:45 PM PDT 24
Peak memory 195060 kb
Host smart-07a107d3-1a92-4e87-a43f-d8ff32e9049a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825451225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.825451225
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.2606704479
Short name T384
Test name
Test status
Simulation time 3513831934 ps
CPU time 81.54 seconds
Started Jun 11 12:27:50 PM PDT 24
Finished Jun 11 12:29:13 PM PDT 24
Peak memory 192004 kb
Host smart-2da49c14-c445-4e0c-8273-417e82255a55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606704479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.2606704479
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.949385776
Short name T193
Test name
Test status
Simulation time 13124114 ps
CPU time 0.57 seconds
Started Jun 11 12:27:51 PM PDT 24
Finished Jun 11 12:27:53 PM PDT 24
Peak memory 193836 kb
Host smart-482027e8-92e5-4624-9000-dbfa57a4948c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949385776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.949385776
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.2909543861
Short name T300
Test name
Test status
Simulation time 162485817 ps
CPU time 0.72 seconds
Started Jun 11 12:27:52 PM PDT 24
Finished Jun 11 12:27:55 PM PDT 24
Peak memory 195148 kb
Host smart-9df9e5a4-3648-41f9-9ea0-4b53db821b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909543861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.2909543861
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.1247035939
Short name T663
Test name
Test status
Simulation time 150057107 ps
CPU time 6.93 seconds
Started Jun 11 12:27:53 PM PDT 24
Finished Jun 11 12:28:02 PM PDT 24
Peak memory 196832 kb
Host smart-0af4ccdc-0c60-4903-af67-66ebf573c89a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247035939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.1247035939
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.922448373
Short name T236
Test name
Test status
Simulation time 1263068482 ps
CPU time 1.1 seconds
Started Jun 11 12:27:52 PM PDT 24
Finished Jun 11 12:27:55 PM PDT 24
Peak memory 197660 kb
Host smart-7a1718dd-3210-43f5-a23c-6d3d12b208a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922448373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.922448373
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.3536989624
Short name T120
Test name
Test status
Simulation time 32474876 ps
CPU time 0.88 seconds
Started Jun 11 12:27:53 PM PDT 24
Finished Jun 11 12:27:55 PM PDT 24
Peak memory 196456 kb
Host smart-25c57f57-d671-4164-bb9e-4f4fbeccb44a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536989624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.3536989624
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.1373208365
Short name T576
Test name
Test status
Simulation time 281034277 ps
CPU time 1.61 seconds
Started Jun 11 12:27:50 PM PDT 24
Finished Jun 11 12:27:54 PM PDT 24
Peak memory 197924 kb
Host smart-dd3d52e3-e7ff-498d-9f99-9e9cde0b246c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373208365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.1373208365
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.1775675052
Short name T439
Test name
Test status
Simulation time 372758256 ps
CPU time 3.23 seconds
Started Jun 11 12:27:48 PM PDT 24
Finished Jun 11 12:27:53 PM PDT 24
Peak memory 195724 kb
Host smart-06bd8387-cd08-406b-96ba-b6989b5289df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775675052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.1775675052
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.3952019702
Short name T66
Test name
Test status
Simulation time 73879839 ps
CPU time 0.95 seconds
Started Jun 11 12:27:50 PM PDT 24
Finished Jun 11 12:27:52 PM PDT 24
Peak memory 195704 kb
Host smart-cbccadd9-874e-413c-8b43-dcdcc7f38ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952019702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.3952019702
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.1212485612
Short name T414
Test name
Test status
Simulation time 19299611 ps
CPU time 0.7 seconds
Started Jun 11 12:27:47 PM PDT 24
Finished Jun 11 12:27:49 PM PDT 24
Peak memory 195264 kb
Host smart-b23eb13d-5d48-440d-89c9-16c81bc97514
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212485612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.1212485612
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_smoke.2794492204
Short name T563
Test name
Test status
Simulation time 90821348 ps
CPU time 0.9 seconds
Started Jun 11 12:27:52 PM PDT 24
Finished Jun 11 12:27:55 PM PDT 24
Peak memory 196156 kb
Host smart-b5512303-c0e9-4090-9510-6bca63feb9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794492204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.2794492204
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.4109054902
Short name T686
Test name
Test status
Simulation time 111648787 ps
CPU time 1.01 seconds
Started Jun 11 12:27:50 PM PDT 24
Finished Jun 11 12:27:52 PM PDT 24
Peak memory 195780 kb
Host smart-53e6f256-752b-4b1a-af08-ced6bb68a56d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109054902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.4109054902
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.1596679027
Short name T321
Test name
Test status
Simulation time 13797540096 ps
CPU time 102.79 seconds
Started Jun 11 12:28:01 PM PDT 24
Finished Jun 11 12:29:45 PM PDT 24
Peak memory 198024 kb
Host smart-3bb3731f-fd0c-43aa-9be8-2ea1e241c93c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596679027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.1596679027
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.3794400675
Short name T608
Test name
Test status
Simulation time 13738560 ps
CPU time 0.56 seconds
Started Jun 11 12:27:55 PM PDT 24
Finished Jun 11 12:27:57 PM PDT 24
Peak memory 193860 kb
Host smart-6c21a09b-b673-48a4-a6e8-c11614e06b5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794400675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.3794400675
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.737464491
Short name T24
Test name
Test status
Simulation time 56970096 ps
CPU time 0.85 seconds
Started Jun 11 12:27:57 PM PDT 24
Finished Jun 11 12:27:59 PM PDT 24
Peak memory 197140 kb
Host smart-3d9fb256-afbc-4a8d-a298-3dafe048173b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737464491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.737464491
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.1889360578
Short name T653
Test name
Test status
Simulation time 454628381 ps
CPU time 7.88 seconds
Started Jun 11 12:27:55 PM PDT 24
Finished Jun 11 12:28:04 PM PDT 24
Peak memory 195472 kb
Host smart-04755248-29ab-41aa-9762-0460f9275944
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889360578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.1889360578
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.1254535182
Short name T238
Test name
Test status
Simulation time 143570390 ps
CPU time 0.64 seconds
Started Jun 11 12:27:48 PM PDT 24
Finished Jun 11 12:27:50 PM PDT 24
Peak memory 194496 kb
Host smart-25551569-e61c-4d7c-b841-d75064b9791c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254535182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.1254535182
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.1247793148
Short name T252
Test name
Test status
Simulation time 32427707 ps
CPU time 0.97 seconds
Started Jun 11 12:27:50 PM PDT 24
Finished Jun 11 12:27:53 PM PDT 24
Peak memory 195700 kb
Host smart-ad02dcc1-80a4-4f1e-9611-969173d076cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247793148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.1247793148
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.2278729065
Short name T674
Test name
Test status
Simulation time 700879349 ps
CPU time 3.43 seconds
Started Jun 11 12:27:48 PM PDT 24
Finished Jun 11 12:27:53 PM PDT 24
Peak memory 197928 kb
Host smart-fa6766d2-95af-47a5-b3d8-44e5fe9108da
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278729065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.2278729065
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3481257565
Short name T307
Test name
Test status
Simulation time 135706365 ps
CPU time 2.62 seconds
Started Jun 11 12:27:45 PM PDT 24
Finished Jun 11 12:27:50 PM PDT 24
Peak memory 198028 kb
Host smart-34fe8aab-f17f-4404-af16-4ce110170fe9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481257565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3481257565
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.1514524569
Short name T153
Test name
Test status
Simulation time 248243945 ps
CPU time 0.81 seconds
Started Jun 11 12:27:46 PM PDT 24
Finished Jun 11 12:27:49 PM PDT 24
Peak memory 196624 kb
Host smart-4b81fae0-3dd8-47f8-8315-c3466b9cec89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514524569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.1514524569
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.3802886196
Short name T286
Test name
Test status
Simulation time 140023445 ps
CPU time 0.66 seconds
Started Jun 11 12:27:53 PM PDT 24
Finished Jun 11 12:27:55 PM PDT 24
Peak memory 194988 kb
Host smart-b0f9077e-60bd-45e2-bded-a587fa0f82fb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802886196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.3802886196
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.2101301437
Short name T476
Test name
Test status
Simulation time 54380921 ps
CPU time 1.31 seconds
Started Jun 11 12:27:53 PM PDT 24
Finished Jun 11 12:27:56 PM PDT 24
Peak memory 197924 kb
Host smart-86dca402-857e-42af-8b1c-cb6d80a3acab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101301437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.2101301437
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.473730400
Short name T424
Test name
Test status
Simulation time 140942660 ps
CPU time 0.79 seconds
Started Jun 11 12:27:45 PM PDT 24
Finished Jun 11 12:27:47 PM PDT 24
Peak memory 195984 kb
Host smart-65854151-140a-4322-bcf1-c1e6bc834896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473730400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.473730400
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.4015054943
Short name T633
Test name
Test status
Simulation time 59961074 ps
CPU time 0.79 seconds
Started Jun 11 12:27:51 PM PDT 24
Finished Jun 11 12:27:53 PM PDT 24
Peak memory 195880 kb
Host smart-a0e5ed07-0045-4482-af13-c59e17af1e38
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015054943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.4015054943
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.584569061
Short name T672
Test name
Test status
Simulation time 29918776188 ps
CPU time 206.85 seconds
Started Jun 11 12:27:49 PM PDT 24
Finished Jun 11 12:31:18 PM PDT 24
Peak memory 198204 kb
Host smart-a2608324-5ef6-466e-a6a5-b30c88a3feb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584569061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.g
pio_stress_all.584569061
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.1679638363
Short name T549
Test name
Test status
Simulation time 198725337432 ps
CPU time 1474.52 seconds
Started Jun 11 12:27:48 PM PDT 24
Finished Jun 11 12:52:24 PM PDT 24
Peak memory 198128 kb
Host smart-63dcdc1d-4982-42d4-bbaa-4c036732ab66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1679638363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.1679638363
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.3953952867
Short name T641
Test name
Test status
Simulation time 12154303 ps
CPU time 0.57 seconds
Started Jun 11 12:27:49 PM PDT 24
Finished Jun 11 12:27:51 PM PDT 24
Peak memory 193848 kb
Host smart-93814d28-9d52-4da8-8201-7af74e736518
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953952867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.3953952867
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.3573883112
Short name T298
Test name
Test status
Simulation time 67824068 ps
CPU time 0.68 seconds
Started Jun 11 12:27:47 PM PDT 24
Finished Jun 11 12:27:49 PM PDT 24
Peak memory 194100 kb
Host smart-551287e0-330b-44cd-b919-76c9764d73dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573883112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.3573883112
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.4135225410
Short name T652
Test name
Test status
Simulation time 2116971122 ps
CPU time 27.42 seconds
Started Jun 11 12:27:52 PM PDT 24
Finished Jun 11 12:28:21 PM PDT 24
Peak memory 196816 kb
Host smart-3a3bb25d-18a3-4806-8300-cdaaff662735
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135225410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.4135225410
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.2269145691
Short name T527
Test name
Test status
Simulation time 91772016 ps
CPU time 1.01 seconds
Started Jun 11 12:27:51 PM PDT 24
Finished Jun 11 12:27:53 PM PDT 24
Peak memory 196524 kb
Host smart-c84ac06c-6807-42a3-9b78-b330b2ea5021
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269145691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.2269145691
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.2653648070
Short name T698
Test name
Test status
Simulation time 514841490 ps
CPU time 1.05 seconds
Started Jun 11 12:27:47 PM PDT 24
Finished Jun 11 12:27:49 PM PDT 24
Peak memory 196560 kb
Host smart-1a85c1ee-4633-427a-b375-3b53feed49d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653648070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.2653648070
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.2455510631
Short name T475
Test name
Test status
Simulation time 35288690 ps
CPU time 1.41 seconds
Started Jun 11 12:27:49 PM PDT 24
Finished Jun 11 12:27:52 PM PDT 24
Peak memory 197000 kb
Host smart-cb83dd74-8a28-4758-bf74-9724b7c10f43
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455510631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.2455510631
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.3307441173
Short name T572
Test name
Test status
Simulation time 67958517 ps
CPU time 1.48 seconds
Started Jun 11 12:27:50 PM PDT 24
Finished Jun 11 12:27:53 PM PDT 24
Peak memory 196104 kb
Host smart-16a62b66-5040-4881-8490-b2fbc5ca1866
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307441173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.3307441173
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.4251088881
Short name T160
Test name
Test status
Simulation time 18884829 ps
CPU time 0.73 seconds
Started Jun 11 12:27:54 PM PDT 24
Finished Jun 11 12:27:56 PM PDT 24
Peak memory 195336 kb
Host smart-a9d0260c-8b50-4e65-81f7-268ddfb5765a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251088881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.4251088881
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.850290440
Short name T356
Test name
Test status
Simulation time 24094212 ps
CPU time 0.71 seconds
Started Jun 11 12:27:50 PM PDT 24
Finished Jun 11 12:27:52 PM PDT 24
Peak memory 195028 kb
Host smart-e019bdf4-2b2c-42ac-ad67-ac73bb6ac774
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850290440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullup
_pulldown.850290440
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.2204627122
Short name T556
Test name
Test status
Simulation time 76115787 ps
CPU time 3.44 seconds
Started Jun 11 12:27:48 PM PDT 24
Finished Jun 11 12:27:53 PM PDT 24
Peak memory 197856 kb
Host smart-d6b503dd-5ea7-4e4c-ae52-d65f3dce6f32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204627122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.2204627122
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.269835326
Short name T19
Test name
Test status
Simulation time 35887318 ps
CPU time 1.01 seconds
Started Jun 11 12:27:49 PM PDT 24
Finished Jun 11 12:27:52 PM PDT 24
Peak memory 196404 kb
Host smart-caece1d1-66b6-4b8c-993c-692afbd2558e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269835326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.269835326
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.222664894
Short name T272
Test name
Test status
Simulation time 54554521 ps
CPU time 1.21 seconds
Started Jun 11 12:27:53 PM PDT 24
Finished Jun 11 12:27:56 PM PDT 24
Peak memory 195652 kb
Host smart-0b026d88-0faa-4753-9cac-ef6221fb09f7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222664894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.222664894
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.3547939945
Short name T375
Test name
Test status
Simulation time 8364280789 ps
CPU time 84.87 seconds
Started Jun 11 12:27:45 PM PDT 24
Finished Jun 11 12:29:12 PM PDT 24
Peak memory 192084 kb
Host smart-27237bef-c5ff-4779-a879-fa1b2015c048
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547939945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.3547939945
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.2482766689
Short name T214
Test name
Test status
Simulation time 35948634 ps
CPU time 0.56 seconds
Started Jun 11 12:27:11 PM PDT 24
Finished Jun 11 12:27:15 PM PDT 24
Peak memory 193928 kb
Host smart-666c677b-85fd-4096-92be-01198ea6cf8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482766689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.2482766689
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.1084968642
Short name T539
Test name
Test status
Simulation time 14666879 ps
CPU time 0.62 seconds
Started Jun 11 12:27:09 PM PDT 24
Finished Jun 11 12:27:12 PM PDT 24
Peak memory 194676 kb
Host smart-f7cbfd40-cc58-460d-be55-2014be18856d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084968642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.1084968642
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.2853660895
Short name T450
Test name
Test status
Simulation time 199093331 ps
CPU time 5.64 seconds
Started Jun 11 12:27:13 PM PDT 24
Finished Jun 11 12:27:21 PM PDT 24
Peak memory 196724 kb
Host smart-19cb6577-531f-473c-a5c1-dc2078ca1eef
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853660895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.2853660895
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.1059681628
Short name T706
Test name
Test status
Simulation time 640764586 ps
CPU time 0.98 seconds
Started Jun 11 12:27:10 PM PDT 24
Finished Jun 11 12:27:13 PM PDT 24
Peak memory 196272 kb
Host smart-93fd960e-1646-40bd-a79f-c6af5e490d27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059681628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.1059681628
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.1639875049
Short name T277
Test name
Test status
Simulation time 87813547 ps
CPU time 1.1 seconds
Started Jun 11 12:27:11 PM PDT 24
Finished Jun 11 12:27:15 PM PDT 24
Peak memory 195696 kb
Host smart-ec180837-6666-48e8-b7be-2292c136e678
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639875049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.1639875049
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.795952529
Short name T113
Test name
Test status
Simulation time 91305495 ps
CPU time 2.54 seconds
Started Jun 11 12:27:12 PM PDT 24
Finished Jun 11 12:27:17 PM PDT 24
Peak memory 196240 kb
Host smart-6a3afdd7-bf66-43de-b60a-613262ddc330
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795952529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.gpio_intr_with_filter_rand_intr_event.795952529
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.2526538369
Short name T466
Test name
Test status
Simulation time 299525836 ps
CPU time 1.53 seconds
Started Jun 11 12:27:09 PM PDT 24
Finished Jun 11 12:27:12 PM PDT 24
Peak memory 196136 kb
Host smart-b8c7b674-adb4-4052-874c-8a4cd287a3e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526538369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
2526538369
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.2435220890
Short name T670
Test name
Test status
Simulation time 37467153 ps
CPU time 1.21 seconds
Started Jun 11 12:27:12 PM PDT 24
Finished Jun 11 12:27:16 PM PDT 24
Peak memory 196820 kb
Host smart-99604e38-47f9-47db-a5b7-9058f9f90c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435220890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.2435220890
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.2791933135
Short name T461
Test name
Test status
Simulation time 783383068 ps
CPU time 1.12 seconds
Started Jun 11 12:27:13 PM PDT 24
Finished Jun 11 12:27:17 PM PDT 24
Peak memory 196872 kb
Host smart-bca3f923-bdc1-48f0-b6e8-91be31825abf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791933135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.2791933135
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.341939241
Short name T604
Test name
Test status
Simulation time 159022783 ps
CPU time 3.39 seconds
Started Jun 11 12:27:12 PM PDT 24
Finished Jun 11 12:27:18 PM PDT 24
Peak memory 197936 kb
Host smart-0da58bde-1f63-4f1c-8f82-879d3cbfd8db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341939241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand
om_long_reg_writes_reg_reads.341939241
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_smoke.1439531217
Short name T12
Test name
Test status
Simulation time 48019587 ps
CPU time 1.31 seconds
Started Jun 11 12:27:13 PM PDT 24
Finished Jun 11 12:27:17 PM PDT 24
Peak memory 195436 kb
Host smart-7bd5b54d-8fff-4185-a80f-9b26bb6f1aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439531217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.1439531217
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.725117796
Short name T711
Test name
Test status
Simulation time 142105963 ps
CPU time 0.99 seconds
Started Jun 11 12:27:08 PM PDT 24
Finished Jun 11 12:27:11 PM PDT 24
Peak memory 195432 kb
Host smart-75e0d022-c903-471a-aa38-f7c982b54a26
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725117796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.725117796
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.3597892897
Short name T696
Test name
Test status
Simulation time 1445388668 ps
CPU time 33.28 seconds
Started Jun 11 12:27:10 PM PDT 24
Finished Jun 11 12:27:46 PM PDT 24
Peak memory 191564 kb
Host smart-f114540c-56dd-4a3d-a0f5-da8012334f6e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597892897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.3597892897
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.4684208
Short name T194
Test name
Test status
Simulation time 33102383 ps
CPU time 0.58 seconds
Started Jun 11 12:27:53 PM PDT 24
Finished Jun 11 12:27:55 PM PDT 24
Peak memory 193416 kb
Host smart-6f423bc2-8b0f-45bd-a6b0-5d8c7c0fb8fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4684208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.4684208
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.130970773
Short name T125
Test name
Test status
Simulation time 136248920 ps
CPU time 0.83 seconds
Started Jun 11 12:27:49 PM PDT 24
Finished Jun 11 12:27:51 PM PDT 24
Peak memory 195156 kb
Host smart-e4c6caac-26f6-4a91-9325-7d3801b098f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130970773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.130970773
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.4097997206
Short name T376
Test name
Test status
Simulation time 165469439 ps
CPU time 4.39 seconds
Started Jun 11 12:28:03 PM PDT 24
Finished Jun 11 12:28:09 PM PDT 24
Peak memory 195864 kb
Host smart-98bdd7c8-ef67-40bb-8d27-62b9f06c15fd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097997206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.4097997206
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.3561465896
Short name T555
Test name
Test status
Simulation time 232671259 ps
CPU time 0.91 seconds
Started Jun 11 12:27:47 PM PDT 24
Finished Jun 11 12:27:49 PM PDT 24
Peak memory 196632 kb
Host smart-bf21fd44-d3db-4ac9-ae2f-7b3e3923e580
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561465896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.3561465896
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.1249132903
Short name T173
Test name
Test status
Simulation time 118339179 ps
CPU time 1.1 seconds
Started Jun 11 12:27:50 PM PDT 24
Finished Jun 11 12:27:53 PM PDT 24
Peak memory 195800 kb
Host smart-8d96eeeb-8d19-4706-8ca8-a34be86606c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249132903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.1249132903
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.4291775625
Short name T398
Test name
Test status
Simulation time 667178542 ps
CPU time 3.24 seconds
Started Jun 11 12:27:50 PM PDT 24
Finished Jun 11 12:27:55 PM PDT 24
Peak memory 197988 kb
Host smart-d86a296c-66a7-4d04-9251-ed595d89f68c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291775625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.4291775625
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.2428664602
Short name T401
Test name
Test status
Simulation time 133745284 ps
CPU time 1.21 seconds
Started Jun 11 12:28:14 PM PDT 24
Finished Jun 11 12:28:17 PM PDT 24
Peak memory 197468 kb
Host smart-7fdf7e99-3f5a-40fb-aa1d-0050f91497fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428664602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.2428664602
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.2752909470
Short name T271
Test name
Test status
Simulation time 76619827 ps
CPU time 0.91 seconds
Started Jun 11 12:27:51 PM PDT 24
Finished Jun 11 12:27:53 PM PDT 24
Peak memory 196464 kb
Host smart-bc0c8a29-126c-4713-8790-95955591bc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752909470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.2752909470
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.2716727577
Short name T188
Test name
Test status
Simulation time 38732681 ps
CPU time 0.68 seconds
Started Jun 11 12:27:48 PM PDT 24
Finished Jun 11 12:27:50 PM PDT 24
Peak memory 194884 kb
Host smart-46d31e89-c163-4c18-8db4-129c58e5ef3b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716727577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.2716727577
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.1416016219
Short name T73
Test name
Test status
Simulation time 196827254 ps
CPU time 2.43 seconds
Started Jun 11 12:27:49 PM PDT 24
Finished Jun 11 12:27:53 PM PDT 24
Peak memory 197828 kb
Host smart-38a16bf2-8964-467c-bba9-2c86724eb77e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416016219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.1416016219
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.1024804943
Short name T305
Test name
Test status
Simulation time 180014621 ps
CPU time 1.01 seconds
Started Jun 11 12:27:50 PM PDT 24
Finished Jun 11 12:27:52 PM PDT 24
Peak memory 195572 kb
Host smart-c17ea0f5-aba6-41f2-aa23-90cf49074f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024804943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.1024804943
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.1844292171
Short name T505
Test name
Test status
Simulation time 117999788 ps
CPU time 1.13 seconds
Started Jun 11 12:27:56 PM PDT 24
Finished Jun 11 12:27:58 PM PDT 24
Peak memory 195436 kb
Host smart-86181b1b-70de-4bff-9c9b-d4e95f63f118
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844292171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.1844292171
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.358185627
Short name T499
Test name
Test status
Simulation time 25460587881 ps
CPU time 185.73 seconds
Started Jun 11 12:27:46 PM PDT 24
Finished Jun 11 12:30:53 PM PDT 24
Peak memory 198064 kb
Host smart-eb1ba3ef-b049-4846-b86a-a7976f1f74cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358185627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.g
pio_stress_all.358185627
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.4165747473
Short name T64
Test name
Test status
Simulation time 52815785104 ps
CPU time 195.27 seconds
Started Jun 11 12:27:47 PM PDT 24
Finished Jun 11 12:31:04 PM PDT 24
Peak memory 198088 kb
Host smart-7344e2bf-71d0-4703-807f-8d51136c3a5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4165747473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.4165747473
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.3675563764
Short name T45
Test name
Test status
Simulation time 13387742 ps
CPU time 0.6 seconds
Started Jun 11 12:27:54 PM PDT 24
Finished Jun 11 12:27:56 PM PDT 24
Peak memory 193772 kb
Host smart-1a703538-2bd7-44c3-a8b1-d794be5c6c00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675563764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.3675563764
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.2891138244
Short name T235
Test name
Test status
Simulation time 102086962 ps
CPU time 0.65 seconds
Started Jun 11 12:27:51 PM PDT 24
Finished Jun 11 12:27:54 PM PDT 24
Peak memory 194052 kb
Host smart-080634e2-0710-4a47-b35c-b64f50eaceda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891138244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.2891138244
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.2025444126
Short name T610
Test name
Test status
Simulation time 1085775634 ps
CPU time 8.58 seconds
Started Jun 11 12:27:53 PM PDT 24
Finished Jun 11 12:28:03 PM PDT 24
Peak memory 197828 kb
Host smart-2efd5b07-a817-4e84-b333-69c1c1d9fd80
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025444126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.2025444126
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.213837668
Short name T278
Test name
Test status
Simulation time 57775487 ps
CPU time 0.7 seconds
Started Jun 11 12:27:52 PM PDT 24
Finished Jun 11 12:27:55 PM PDT 24
Peak memory 194544 kb
Host smart-bf9aaade-202b-4810-ad94-6aeb5dc3ed02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213837668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.213837668
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.1473293575
Short name T119
Test name
Test status
Simulation time 95439943 ps
CPU time 0.7 seconds
Started Jun 11 12:27:53 PM PDT 24
Finished Jun 11 12:27:55 PM PDT 24
Peak memory 195984 kb
Host smart-9115fb55-fa3e-4f79-aff3-71847585405b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473293575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.1473293575
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.3845373872
Short name T609
Test name
Test status
Simulation time 74041247 ps
CPU time 2.77 seconds
Started Jun 11 12:27:51 PM PDT 24
Finished Jun 11 12:27:55 PM PDT 24
Peak memory 197824 kb
Host smart-57fd864a-ac1b-41d9-a9cf-38b6708dce27
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845373872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.3845373872
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.1725388974
Short name T495
Test name
Test status
Simulation time 47802827 ps
CPU time 1.58 seconds
Started Jun 11 12:27:48 PM PDT 24
Finished Jun 11 12:27:51 PM PDT 24
Peak memory 195904 kb
Host smart-96f03d36-a25d-49f5-8949-0af0aa1432fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725388974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.1725388974
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.3368008323
Short name T285
Test name
Test status
Simulation time 46295027 ps
CPU time 1.06 seconds
Started Jun 11 12:27:57 PM PDT 24
Finished Jun 11 12:27:59 PM PDT 24
Peak memory 196624 kb
Host smart-06fec6f7-c82b-4293-84e5-d5617c6707d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368008323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.3368008323
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.3005312683
Short name T699
Test name
Test status
Simulation time 46272735 ps
CPU time 0.87 seconds
Started Jun 11 12:27:46 PM PDT 24
Finished Jun 11 12:27:48 PM PDT 24
Peak memory 195312 kb
Host smart-1e18a2c3-7564-475b-80c3-6e9f7777c235
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005312683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.3005312683
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.2548896409
Short name T220
Test name
Test status
Simulation time 1667306309 ps
CPU time 6.05 seconds
Started Jun 11 12:27:49 PM PDT 24
Finished Jun 11 12:27:57 PM PDT 24
Peak memory 197836 kb
Host smart-339fae1c-8624-4609-87e7-567648a28b18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548896409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.2548896409
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.203073103
Short name T216
Test name
Test status
Simulation time 31123500 ps
CPU time 0.83 seconds
Started Jun 11 12:27:45 PM PDT 24
Finished Jun 11 12:27:47 PM PDT 24
Peak memory 196328 kb
Host smart-fbaa96a1-3725-4ec4-b665-3fce2be53df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203073103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.203073103
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.916706319
Short name T301
Test name
Test status
Simulation time 78371239 ps
CPU time 0.88 seconds
Started Jun 11 12:28:04 PM PDT 24
Finished Jun 11 12:28:06 PM PDT 24
Peak memory 195864 kb
Host smart-84d4488b-74d3-4146-940a-73f67da84855
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916706319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.916706319
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.1920072311
Short name T578
Test name
Test status
Simulation time 7777331694 ps
CPU time 19.88 seconds
Started Jun 11 12:27:54 PM PDT 24
Finished Jun 11 12:28:16 PM PDT 24
Peak memory 192000 kb
Host smart-cdae392f-f3c9-43c6-a6f8-e50fde7a90ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920072311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.1920072311
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.151369726
Short name T44
Test name
Test status
Simulation time 16961670 ps
CPU time 0.57 seconds
Started Jun 11 12:28:07 PM PDT 24
Finished Jun 11 12:28:11 PM PDT 24
Peak memory 194004 kb
Host smart-f4d3d4d6-7243-40c0-8640-fb67946cf5bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151369726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.151369726
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.216124914
Short name T357
Test name
Test status
Simulation time 623235761 ps
CPU time 0.83 seconds
Started Jun 11 12:27:47 PM PDT 24
Finished Jun 11 12:27:50 PM PDT 24
Peak memory 195944 kb
Host smart-2ac1bebb-9c41-485d-98aa-4138e3608820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216124914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.216124914
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.711157033
Short name T149
Test name
Test status
Simulation time 1888249861 ps
CPU time 14.7 seconds
Started Jun 11 12:27:54 PM PDT 24
Finished Jun 11 12:28:10 PM PDT 24
Peak memory 197884 kb
Host smart-a15e45a1-b601-4676-8616-5bbb4ea36a0d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711157033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stres
s.711157033
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.195347242
Short name T325
Test name
Test status
Simulation time 87809646 ps
CPU time 0.84 seconds
Started Jun 11 12:27:54 PM PDT 24
Finished Jun 11 12:27:56 PM PDT 24
Peak memory 195964 kb
Host smart-21e706d0-21f9-42aa-9e11-d5d7af17846e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195347242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.195347242
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.3726917857
Short name T347
Test name
Test status
Simulation time 82400029 ps
CPU time 1.16 seconds
Started Jun 11 12:27:51 PM PDT 24
Finished Jun 11 12:27:54 PM PDT 24
Peak memory 196848 kb
Host smart-7bb1e26f-9105-4db1-b116-b51605263732
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726917857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.3726917857
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.2625362620
Short name T159
Test name
Test status
Simulation time 325487609 ps
CPU time 2.33 seconds
Started Jun 11 12:27:54 PM PDT 24
Finished Jun 11 12:27:58 PM PDT 24
Peak memory 196900 kb
Host smart-cfa53e24-3ae0-4e81-a45d-2c85db45d1b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625362620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.2625362620
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.3262323512
Short name T369
Test name
Test status
Simulation time 75494273 ps
CPU time 1.28 seconds
Started Jun 11 12:27:54 PM PDT 24
Finished Jun 11 12:27:57 PM PDT 24
Peak memory 196904 kb
Host smart-c27cfa51-5823-4bf3-a412-f6ab27b24e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262323512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.3262323512
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.2267935083
Short name T355
Test name
Test status
Simulation time 88766349 ps
CPU time 0.99 seconds
Started Jun 11 12:27:50 PM PDT 24
Finished Jun 11 12:27:53 PM PDT 24
Peak memory 196588 kb
Host smart-ca76f2f7-d112-40e4-94ed-28ff9f7f178d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267935083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.2267935083
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.3595165475
Short name T5
Test name
Test status
Simulation time 537944631 ps
CPU time 3.28 seconds
Started Jun 11 12:27:52 PM PDT 24
Finished Jun 11 12:27:57 PM PDT 24
Peak memory 197880 kb
Host smart-c0229e1e-3fd6-42d6-9eab-332452acf526
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595165475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.3595165475
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.563918161
Short name T322
Test name
Test status
Simulation time 74212293 ps
CPU time 1.33 seconds
Started Jun 11 12:27:55 PM PDT 24
Finished Jun 11 12:27:58 PM PDT 24
Peak memory 196744 kb
Host smart-6c502410-1770-4809-8c7a-3548f3596b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563918161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.563918161
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.377645310
Short name T336
Test name
Test status
Simulation time 40233008 ps
CPU time 1.11 seconds
Started Jun 11 12:27:54 PM PDT 24
Finished Jun 11 12:27:56 PM PDT 24
Peak memory 195484 kb
Host smart-50461894-b611-4244-b3a4-73e314213740
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377645310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.377645310
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.4213370141
Short name T616
Test name
Test status
Simulation time 3069608791 ps
CPU time 18.36 seconds
Started Jun 11 12:27:53 PM PDT 24
Finished Jun 11 12:28:13 PM PDT 24
Peak memory 198072 kb
Host smart-a77ba317-9b87-437f-9422-f5c014dbff1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213370141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.4213370141
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.1485574221
Short name T478
Test name
Test status
Simulation time 213312994627 ps
CPU time 686.81 seconds
Started Jun 11 12:27:56 PM PDT 24
Finished Jun 11 12:39:24 PM PDT 24
Peak memory 198168 kb
Host smart-b88e23c7-bef8-477f-b328-468134248545
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1485574221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.1485574221
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.1020989035
Short name T611
Test name
Test status
Simulation time 94038183 ps
CPU time 0.55 seconds
Started Jun 11 12:27:59 PM PDT 24
Finished Jun 11 12:28:01 PM PDT 24
Peak memory 193828 kb
Host smart-38e3f2ff-de20-428d-a7ee-4a064d7306a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020989035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.1020989035
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.1780602835
Short name T469
Test name
Test status
Simulation time 167853912 ps
CPU time 0.61 seconds
Started Jun 11 12:28:06 PM PDT 24
Finished Jun 11 12:28:09 PM PDT 24
Peak memory 193720 kb
Host smart-1cf89831-5030-4c2c-88ff-da61dd55c8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780602835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.1780602835
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.3452929446
Short name T528
Test name
Test status
Simulation time 553730010 ps
CPU time 17.56 seconds
Started Jun 11 12:28:05 PM PDT 24
Finished Jun 11 12:28:25 PM PDT 24
Peak memory 196620 kb
Host smart-060c5528-9d3c-4fba-ad19-bb2e2b620dc7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452929446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.3452929446
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.176336428
Short name T682
Test name
Test status
Simulation time 32131155 ps
CPU time 0.7 seconds
Started Jun 11 12:28:05 PM PDT 24
Finished Jun 11 12:28:08 PM PDT 24
Peak memory 195288 kb
Host smart-5ef4b4ff-62c6-4e76-8aed-8abd1f70bac7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176336428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.176336428
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.4023235139
Short name T394
Test name
Test status
Simulation time 42162784 ps
CPU time 0.9 seconds
Started Jun 11 12:28:00 PM PDT 24
Finished Jun 11 12:28:02 PM PDT 24
Peak memory 197292 kb
Host smart-4db0f581-da93-4b48-9d73-8d61d0427fb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023235139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.4023235139
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.3949896174
Short name T390
Test name
Test status
Simulation time 128821605 ps
CPU time 1.5 seconds
Started Jun 11 12:28:05 PM PDT 24
Finished Jun 11 12:28:09 PM PDT 24
Peak memory 197920 kb
Host smart-b6fd2952-3aa5-4a8e-91be-88d153a5966a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949896174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.3949896174
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.2873492294
Short name T269
Test name
Test status
Simulation time 40871881 ps
CPU time 1.34 seconds
Started Jun 11 12:28:01 PM PDT 24
Finished Jun 11 12:28:03 PM PDT 24
Peak memory 195780 kb
Host smart-855fe771-a644-4f27-b011-7d30c1ec41fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873492294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.2873492294
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.1612326902
Short name T57
Test name
Test status
Simulation time 25415754 ps
CPU time 0.66 seconds
Started Jun 11 12:28:03 PM PDT 24
Finished Jun 11 12:28:05 PM PDT 24
Peak memory 194128 kb
Host smart-f10df95f-6f55-4d61-af65-14115452b164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612326902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.1612326902
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.469693933
Short name T415
Test name
Test status
Simulation time 94186496 ps
CPU time 0.97 seconds
Started Jun 11 12:27:59 PM PDT 24
Finished Jun 11 12:28:01 PM PDT 24
Peak memory 195732 kb
Host smart-98f4a47b-152f-4e86-9c9d-b9cd17df17a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469693933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullup
_pulldown.469693933
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.3124891207
Short name T654
Test name
Test status
Simulation time 470090953 ps
CPU time 5.38 seconds
Started Jun 11 12:28:05 PM PDT 24
Finished Jun 11 12:28:13 PM PDT 24
Peak memory 197896 kb
Host smart-39e08df3-1768-4e20-9f8a-ce73a5d3959c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124891207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.3124891207
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.3989242718
Short name T150
Test name
Test status
Simulation time 45390585 ps
CPU time 0.93 seconds
Started Jun 11 12:28:11 PM PDT 24
Finished Jun 11 12:28:14 PM PDT 24
Peak memory 196300 kb
Host smart-7d11c7d8-1272-4279-8c91-fd67a24b28b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989242718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.3989242718
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.658989552
Short name T55
Test name
Test status
Simulation time 480906923 ps
CPU time 0.96 seconds
Started Jun 11 12:28:00 PM PDT 24
Finished Jun 11 12:28:02 PM PDT 24
Peak memory 196504 kb
Host smart-5442374e-e65e-470b-bed2-a9e424994a00
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658989552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.658989552
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.4057605575
Short name T681
Test name
Test status
Simulation time 55512645273 ps
CPU time 193.76 seconds
Started Jun 11 12:28:11 PM PDT 24
Finished Jun 11 12:31:27 PM PDT 24
Peak memory 198116 kb
Host smart-bc892781-2316-4e04-b15a-9bcfb75c5449
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057605575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.4057605575
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.597720152
Short name T295
Test name
Test status
Simulation time 16009344 ps
CPU time 0.56 seconds
Started Jun 11 12:28:07 PM PDT 24
Finished Jun 11 12:28:11 PM PDT 24
Peak memory 193832 kb
Host smart-d3789104-d3ff-44f5-9925-785782ff2de3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597720152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.597720152
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.1037917115
Short name T103
Test name
Test status
Simulation time 16924705 ps
CPU time 0.6 seconds
Started Jun 11 12:28:12 PM PDT 24
Finished Jun 11 12:28:15 PM PDT 24
Peak memory 194576 kb
Host smart-8508462f-ec99-491d-a461-36b275d70d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037917115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.1037917115
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.1437258729
Short name T621
Test name
Test status
Simulation time 461216658 ps
CPU time 5.74 seconds
Started Jun 11 12:28:07 PM PDT 24
Finished Jun 11 12:28:15 PM PDT 24
Peak memory 196552 kb
Host smart-7b5a7c73-0e67-4847-b156-5cb9edf5fef5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437258729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.1437258729
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.4190528177
Short name T504
Test name
Test status
Simulation time 59166146 ps
CPU time 0.97 seconds
Started Jun 11 12:28:14 PM PDT 24
Finished Jun 11 12:28:17 PM PDT 24
Peak memory 196572 kb
Host smart-6cbf2b77-c67a-4e43-84ea-0ed1d099a1d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190528177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.4190528177
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.961706160
Short name T239
Test name
Test status
Simulation time 52326107 ps
CPU time 1.31 seconds
Started Jun 11 12:28:00 PM PDT 24
Finished Jun 11 12:28:02 PM PDT 24
Peak memory 197128 kb
Host smart-4f26b430-bf4d-4488-9d0a-81c9a3e0b2ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961706160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.961706160
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.2936857408
Short name T428
Test name
Test status
Simulation time 22571418 ps
CPU time 1.02 seconds
Started Jun 11 12:28:06 PM PDT 24
Finished Jun 11 12:28:09 PM PDT 24
Peak memory 196352 kb
Host smart-e9c6971e-9091-49a8-9b14-0038b4deba3c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936857408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.2936857408
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.1102059608
Short name T18
Test name
Test status
Simulation time 60795406 ps
CPU time 1.3 seconds
Started Jun 11 12:28:01 PM PDT 24
Finished Jun 11 12:28:04 PM PDT 24
Peak memory 196668 kb
Host smart-49e670cc-713e-425c-bded-ba0f8ba0fe73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102059608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.1102059608
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.466550915
Short name T69
Test name
Test status
Simulation time 214274519 ps
CPU time 0.77 seconds
Started Jun 11 12:28:05 PM PDT 24
Finished Jun 11 12:28:07 PM PDT 24
Peak memory 195184 kb
Host smart-bb38dfb2-56ee-4eac-96f1-8799180aa2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466550915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.466550915
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.3382784917
Short name T625
Test name
Test status
Simulation time 60008900 ps
CPU time 1.25 seconds
Started Jun 11 12:28:04 PM PDT 24
Finished Jun 11 12:28:06 PM PDT 24
Peak memory 196680 kb
Host smart-874c51f6-a17d-4b0e-9ed8-d6fa0fe5492d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382784917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.3382784917
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.1724699245
Short name T131
Test name
Test status
Simulation time 1209921090 ps
CPU time 4.3 seconds
Started Jun 11 12:28:10 PM PDT 24
Finished Jun 11 12:28:16 PM PDT 24
Peak memory 197832 kb
Host smart-a1d2e41a-9159-4fb8-9c66-16d5c5c0079e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724699245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.1724699245
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.632105061
Short name T132
Test name
Test status
Simulation time 225861932 ps
CPU time 0.97 seconds
Started Jun 11 12:28:04 PM PDT 24
Finished Jun 11 12:28:07 PM PDT 24
Peak memory 195808 kb
Host smart-34cb040f-f34d-4775-be95-a7af4b07ca9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632105061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.632105061
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.2441226847
Short name T223
Test name
Test status
Simulation time 144641442 ps
CPU time 1.2 seconds
Started Jun 11 12:28:03 PM PDT 24
Finished Jun 11 12:28:05 PM PDT 24
Peak memory 195728 kb
Host smart-cec30f11-66d2-4964-8e96-eb97262328f0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441226847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.2441226847
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.3185054840
Short name T229
Test name
Test status
Simulation time 4984806611 ps
CPU time 117.57 seconds
Started Jun 11 12:28:16 PM PDT 24
Finished Jun 11 12:30:15 PM PDT 24
Peak memory 198424 kb
Host smart-22fb270c-e98c-457a-a676-eff20d8984ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185054840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.3185054840
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.2169283609
Short name T59
Test name
Test status
Simulation time 865538829081 ps
CPU time 1749.7 seconds
Started Jun 11 12:27:59 PM PDT 24
Finished Jun 11 12:57:10 PM PDT 24
Peak memory 198204 kb
Host smart-03ef8db1-e534-44a9-b037-a5a6905ac235
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2169283609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.2169283609
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.3113869187
Short name T697
Test name
Test status
Simulation time 15889701 ps
CPU time 0.59 seconds
Started Jun 11 12:28:16 PM PDT 24
Finished Jun 11 12:28:18 PM PDT 24
Peak memory 194592 kb
Host smart-9720d080-746c-442e-b5a9-8861b0c584b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113869187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.3113869187
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.4030238158
Short name T231
Test name
Test status
Simulation time 64818939 ps
CPU time 0.75 seconds
Started Jun 11 12:28:01 PM PDT 24
Finished Jun 11 12:28:03 PM PDT 24
Peak memory 195260 kb
Host smart-6c6b9234-111c-44bd-9900-6810c7eaeebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030238158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.4030238158
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.4109607160
Short name T178
Test name
Test status
Simulation time 2471020782 ps
CPU time 19.34 seconds
Started Jun 11 12:28:17 PM PDT 24
Finished Jun 11 12:28:39 PM PDT 24
Peak memory 197384 kb
Host smart-47e363ef-2231-4fca-8e77-0a217843777b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109607160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.4109607160
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.3571322436
Short name T482
Test name
Test status
Simulation time 36221019 ps
CPU time 0.59 seconds
Started Jun 11 12:28:03 PM PDT 24
Finished Jun 11 12:28:05 PM PDT 24
Peak memory 194944 kb
Host smart-377fbd33-d10c-44d0-8150-5eb09a8bffc9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571322436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.3571322436
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.2085730498
Short name T455
Test name
Test status
Simulation time 38297467 ps
CPU time 1.03 seconds
Started Jun 11 12:28:13 PM PDT 24
Finished Jun 11 12:28:16 PM PDT 24
Peak memory 196112 kb
Host smart-2bd7f065-2752-4c3c-8756-863011bd050b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085730498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.2085730498
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.4024411040
Short name T458
Test name
Test status
Simulation time 105795595 ps
CPU time 2.38 seconds
Started Jun 11 12:28:04 PM PDT 24
Finished Jun 11 12:28:08 PM PDT 24
Peak memory 198240 kb
Host smart-598cec23-6015-499d-bd0c-3dc218b13ac1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024411040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.4024411040
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.2476720237
Short name T422
Test name
Test status
Simulation time 92127342 ps
CPU time 1.5 seconds
Started Jun 11 12:28:09 PM PDT 24
Finished Jun 11 12:28:13 PM PDT 24
Peak memory 196692 kb
Host smart-f81ec751-a65a-4918-921e-1dc16be77077
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476720237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.2476720237
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.1512959249
Short name T694
Test name
Test status
Simulation time 53307828 ps
CPU time 1.1 seconds
Started Jun 11 12:28:06 PM PDT 24
Finished Jun 11 12:28:09 PM PDT 24
Peak memory 195908 kb
Host smart-a098b6c9-3216-464f-9045-e245550f3e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512959249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.1512959249
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.851854003
Short name T378
Test name
Test status
Simulation time 64893347 ps
CPU time 0.61 seconds
Started Jun 11 12:28:11 PM PDT 24
Finished Jun 11 12:28:14 PM PDT 24
Peak memory 194056 kb
Host smart-3b1c33de-e31c-4969-8d68-4b2f3cbe62b5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851854003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullup
_pulldown.851854003
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.2422554152
Short name T628
Test name
Test status
Simulation time 54606043 ps
CPU time 2.5 seconds
Started Jun 11 12:28:04 PM PDT 24
Finished Jun 11 12:28:08 PM PDT 24
Peak memory 197728 kb
Host smart-3e870b8a-c17e-4c3d-b288-eb5a7868a36d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422554152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.2422554152
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.2190571013
Short name T407
Test name
Test status
Simulation time 40821742 ps
CPU time 1.07 seconds
Started Jun 11 12:28:16 PM PDT 24
Finished Jun 11 12:28:19 PM PDT 24
Peak memory 195616 kb
Host smart-8a94a3ce-9aa1-4613-a2f0-a715398df032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190571013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.2190571013
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.1898623359
Short name T124
Test name
Test status
Simulation time 64917731 ps
CPU time 1.21 seconds
Started Jun 11 12:28:18 PM PDT 24
Finished Jun 11 12:28:21 PM PDT 24
Peak memory 195756 kb
Host smart-a620e075-18d7-49d9-862d-d99551b3fae0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898623359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.1898623359
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.3958053779
Short name T126
Test name
Test status
Simulation time 5316153104 ps
CPU time 77.45 seconds
Started Jun 11 12:28:05 PM PDT 24
Finished Jun 11 12:29:24 PM PDT 24
Peak memory 198176 kb
Host smart-105fbbd8-448c-459b-8d16-2e94f300da92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958053779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.3958053779
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.996044212
Short name T62
Test name
Test status
Simulation time 30136268868 ps
CPU time 107.05 seconds
Started Jun 11 12:28:19 PM PDT 24
Finished Jun 11 12:30:08 PM PDT 24
Peak memory 206360 kb
Host smart-98daedb3-faf6-47b2-8325-ef390a7da9d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=996044212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.996044212
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.3300910329
Short name T655
Test name
Test status
Simulation time 23692135 ps
CPU time 0.57 seconds
Started Jun 11 12:28:18 PM PDT 24
Finished Jun 11 12:28:22 PM PDT 24
Peak memory 193788 kb
Host smart-8fd196fd-7633-4d81-acba-50ef7fa9f4a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300910329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.3300910329
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.425702696
Short name T143
Test name
Test status
Simulation time 250521270 ps
CPU time 0.73 seconds
Started Jun 11 12:28:05 PM PDT 24
Finished Jun 11 12:28:08 PM PDT 24
Peak memory 195236 kb
Host smart-dea238b4-ad9f-4f3c-bd0f-6a2bf94daf66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425702696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.425702696
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.3605878817
Short name T598
Test name
Test status
Simulation time 496727311 ps
CPU time 6.05 seconds
Started Jun 11 12:28:18 PM PDT 24
Finished Jun 11 12:28:27 PM PDT 24
Peak memory 195416 kb
Host smart-d29e5019-384f-4154-bcba-a0f4e446269b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605878817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.3605878817
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.206708937
Short name T599
Test name
Test status
Simulation time 133923585 ps
CPU time 0.76 seconds
Started Jun 11 12:28:16 PM PDT 24
Finished Jun 11 12:28:19 PM PDT 24
Peak memory 195884 kb
Host smart-339465a2-11dc-4001-9e46-1cb74448f610
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206708937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.206708937
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.1146219747
Short name T534
Test name
Test status
Simulation time 154342339 ps
CPU time 1.33 seconds
Started Jun 11 12:28:11 PM PDT 24
Finished Jun 11 12:28:14 PM PDT 24
Peak memory 196756 kb
Host smart-4d72522e-49d0-4180-bdfd-d67fdcea3612
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146219747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.1146219747
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.2853297416
Short name T543
Test name
Test status
Simulation time 59136326 ps
CPU time 1.43 seconds
Started Jun 11 12:28:05 PM PDT 24
Finished Jun 11 12:28:09 PM PDT 24
Peak memory 196552 kb
Host smart-465a35a9-3285-4ff2-b1f0-347e77165214
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853297416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.2853297416
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.2603803860
Short name T473
Test name
Test status
Simulation time 129605387 ps
CPU time 1.9 seconds
Started Jun 11 12:28:23 PM PDT 24
Finished Jun 11 12:28:29 PM PDT 24
Peak memory 196140 kb
Host smart-714ea85d-b164-4444-9b70-aa3cbfcff32e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603803860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.2603803860
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.2566328913
Short name T429
Test name
Test status
Simulation time 22977306 ps
CPU time 0.72 seconds
Started Jun 11 12:28:14 PM PDT 24
Finished Jun 11 12:28:17 PM PDT 24
Peak memory 195964 kb
Host smart-3b0b8839-f53d-4045-b28d-c1418b9447bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566328913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2566328913
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.2782135361
Short name T180
Test name
Test status
Simulation time 39143072 ps
CPU time 0.73 seconds
Started Jun 11 12:28:04 PM PDT 24
Finished Jun 11 12:28:06 PM PDT 24
Peak memory 196072 kb
Host smart-998b1227-02fd-4086-a4c9-cab0a3e6bacd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782135361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.2782135361
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.3119778665
Short name T2
Test name
Test status
Simulation time 1081337914 ps
CPU time 3.52 seconds
Started Jun 11 12:28:05 PM PDT 24
Finished Jun 11 12:28:10 PM PDT 24
Peak memory 197780 kb
Host smart-d33dc3b6-dac4-4408-89ad-94c8f1f7d37c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119778665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.3119778665
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.123624049
Short name T251
Test name
Test status
Simulation time 96111837 ps
CPU time 0.83 seconds
Started Jun 11 12:28:10 PM PDT 24
Finished Jun 11 12:28:12 PM PDT 24
Peak memory 195320 kb
Host smart-24ab210a-51e0-4032-b4bc-3491b6162922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123624049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.123624049
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.3556061534
Short name T465
Test name
Test status
Simulation time 78304953 ps
CPU time 0.81 seconds
Started Jun 11 12:28:00 PM PDT 24
Finished Jun 11 12:28:02 PM PDT 24
Peak memory 196848 kb
Host smart-9f9adda3-e3a5-404e-a1bb-ce196e1f7833
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556061534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.3556061534
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.3361191487
Short name T33
Test name
Test status
Simulation time 14691639356 ps
CPU time 193.45 seconds
Started Jun 11 12:28:12 PM PDT 24
Finished Jun 11 12:31:28 PM PDT 24
Peak memory 198072 kb
Host smart-d0a1c12b-1b19-4d68-8cbb-4ba144e150af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361191487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.3361191487
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.3846727321
Short name T468
Test name
Test status
Simulation time 23161349 ps
CPU time 0.55 seconds
Started Jun 11 12:28:16 PM PDT 24
Finished Jun 11 12:28:18 PM PDT 24
Peak memory 193912 kb
Host smart-170b44bc-1c24-45ca-b420-a99c3f2b7589
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846727321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.3846727321
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.2364734480
Short name T171
Test name
Test status
Simulation time 113133476 ps
CPU time 0.75 seconds
Started Jun 11 12:28:16 PM PDT 24
Finished Jun 11 12:28:19 PM PDT 24
Peak memory 195184 kb
Host smart-c2498289-f81e-442f-911e-6b4bb27ab96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364734480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.2364734480
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.1283099402
Short name T281
Test name
Test status
Simulation time 128594627 ps
CPU time 6.56 seconds
Started Jun 11 12:28:20 PM PDT 24
Finished Jun 11 12:28:29 PM PDT 24
Peak memory 196904 kb
Host smart-926d3ac3-96a7-4812-9485-53d2a1d1d19b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283099402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.1283099402
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.3824982322
Short name T460
Test name
Test status
Simulation time 79134638 ps
CPU time 0.87 seconds
Started Jun 11 12:28:15 PM PDT 24
Finished Jun 11 12:28:18 PM PDT 24
Peak memory 196044 kb
Host smart-e00488eb-12bb-468e-a897-b3fffe7f760d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824982322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.3824982322
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.2524249055
Short name T620
Test name
Test status
Simulation time 48825287 ps
CPU time 1.29 seconds
Started Jun 11 12:28:07 PM PDT 24
Finished Jun 11 12:28:11 PM PDT 24
Peak memory 196528 kb
Host smart-5a2b5bbb-6ce3-47e8-9c01-993306ab7b4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524249055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.2524249055
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.3824771317
Short name T538
Test name
Test status
Simulation time 366328071 ps
CPU time 3.45 seconds
Started Jun 11 12:28:15 PM PDT 24
Finished Jun 11 12:28:20 PM PDT 24
Peak memory 197992 kb
Host smart-63c41223-1046-447d-9093-917cda6b71de
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824771317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.3824771317
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.3554439618
Short name T662
Test name
Test status
Simulation time 120907728 ps
CPU time 3.12 seconds
Started Jun 11 12:28:06 PM PDT 24
Finished Jun 11 12:28:12 PM PDT 24
Peak memory 195712 kb
Host smart-2600d3d8-bba0-44f9-a2f6-3a6569730cc1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554439618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.3554439618
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.2843993659
Short name T212
Test name
Test status
Simulation time 227161811 ps
CPU time 1.12 seconds
Started Jun 11 12:28:12 PM PDT 24
Finished Jun 11 12:28:16 PM PDT 24
Peak memory 195884 kb
Host smart-36dfb1ce-e8af-48e6-b307-bd920f4a3b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843993659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.2843993659
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.386207850
Short name T365
Test name
Test status
Simulation time 99258832 ps
CPU time 0.74 seconds
Started Jun 11 12:28:16 PM PDT 24
Finished Jun 11 12:28:19 PM PDT 24
Peak memory 196188 kb
Host smart-f419b87e-e808-4d0e-a302-bc9789138f4a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386207850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullup
_pulldown.386207850
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.3580446810
Short name T8
Test name
Test status
Simulation time 149049748 ps
CPU time 2 seconds
Started Jun 11 12:28:08 PM PDT 24
Finished Jun 11 12:28:12 PM PDT 24
Peak memory 197904 kb
Host smart-65ce8565-69fe-44fd-97ea-577aaca0bc97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580446810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.3580446810
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.2285689647
Short name T710
Test name
Test status
Simulation time 57657935 ps
CPU time 1.07 seconds
Started Jun 11 12:28:06 PM PDT 24
Finished Jun 11 12:28:09 PM PDT 24
Peak memory 195632 kb
Host smart-7dbf46db-b97a-4e6f-acd1-a47345756776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285689647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.2285689647
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.3972277141
Short name T492
Test name
Test status
Simulation time 111166987 ps
CPU time 0.78 seconds
Started Jun 11 12:28:07 PM PDT 24
Finished Jun 11 12:28:11 PM PDT 24
Peak memory 195288 kb
Host smart-3c43e31c-f0f4-42cc-8f91-dd5e54956601
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972277141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.3972277141
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.1698561673
Short name T659
Test name
Test status
Simulation time 6565700729 ps
CPU time 162.23 seconds
Started Jun 11 12:28:15 PM PDT 24
Finished Jun 11 12:31:00 PM PDT 24
Peak memory 198140 kb
Host smart-19303990-e127-4618-aecb-4631ca773e78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698561673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.1698561673
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.2055773355
Short name T501
Test name
Test status
Simulation time 17193484 ps
CPU time 0.56 seconds
Started Jun 11 12:28:04 PM PDT 24
Finished Jun 11 12:28:05 PM PDT 24
Peak memory 193932 kb
Host smart-a869b7ae-68ca-44ff-95b9-51e1ad28d9e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055773355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.2055773355
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.2565456984
Short name T474
Test name
Test status
Simulation time 62689482 ps
CPU time 0.66 seconds
Started Jun 11 12:28:07 PM PDT 24
Finished Jun 11 12:28:10 PM PDT 24
Peak memory 194100 kb
Host smart-8c771d53-d457-4c60-a421-f9bea80559fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565456984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.2565456984
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.3927305468
Short name T379
Test name
Test status
Simulation time 696395919 ps
CPU time 20.06 seconds
Started Jun 11 12:28:06 PM PDT 24
Finished Jun 11 12:28:28 PM PDT 24
Peak memory 196672 kb
Host smart-b93e9353-2258-4eb9-9d10-7abe144337be
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927305468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.3927305468
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.370800785
Short name T254
Test name
Test status
Simulation time 1756671430 ps
CPU time 1.01 seconds
Started Jun 11 12:28:18 PM PDT 24
Finished Jun 11 12:28:21 PM PDT 24
Peak memory 196592 kb
Host smart-7708fa96-0520-4abc-89ac-fd640ebabe53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370800785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.370800785
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.1190490266
Short name T607
Test name
Test status
Simulation time 49191600 ps
CPU time 1.19 seconds
Started Jun 11 12:28:07 PM PDT 24
Finished Jun 11 12:28:10 PM PDT 24
Peak memory 196996 kb
Host smart-c6650f08-95d1-4680-afa1-525fa7b21a19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190490266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.1190490266
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.508457963
Short name T638
Test name
Test status
Simulation time 79019043 ps
CPU time 2.85 seconds
Started Jun 11 12:28:03 PM PDT 24
Finished Jun 11 12:28:07 PM PDT 24
Peak memory 197876 kb
Host smart-cc415b69-3de9-4d27-92f1-805e78b9ea7b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508457963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.gpio_intr_with_filter_rand_intr_event.508457963
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.597889860
Short name T156
Test name
Test status
Simulation time 214293044 ps
CPU time 1.72 seconds
Started Jun 11 12:28:07 PM PDT 24
Finished Jun 11 12:28:12 PM PDT 24
Peak memory 196168 kb
Host smart-d77a62b1-7da1-4494-a9fe-39e7b7199b1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597889860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger.
597889860
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.1747359446
Short name T510
Test name
Test status
Simulation time 205334509 ps
CPU time 1.07 seconds
Started Jun 11 12:28:22 PM PDT 24
Finished Jun 11 12:28:27 PM PDT 24
Peak memory 195784 kb
Host smart-a782f438-5977-4753-820e-67343b3f4b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747359446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.1747359446
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.3255945769
Short name T661
Test name
Test status
Simulation time 17443788 ps
CPU time 0.64 seconds
Started Jun 11 12:28:07 PM PDT 24
Finished Jun 11 12:28:10 PM PDT 24
Peak memory 194304 kb
Host smart-8bb967da-4633-4766-a667-1243ad1095e3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255945769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.3255945769
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.184557505
Short name T651
Test name
Test status
Simulation time 754095025 ps
CPU time 3.33 seconds
Started Jun 11 12:28:18 PM PDT 24
Finished Jun 11 12:28:24 PM PDT 24
Peak memory 197812 kb
Host smart-12e9fa1e-65b5-4eef-9fb2-9a68cdd8719a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184557505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ran
dom_long_reg_writes_reg_reads.184557505
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.2433659490
Short name T558
Test name
Test status
Simulation time 72719799 ps
CPU time 1.11 seconds
Started Jun 11 12:28:07 PM PDT 24
Finished Jun 11 12:28:10 PM PDT 24
Peak memory 195456 kb
Host smart-8391542a-2551-4430-813c-82fbdac638e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433659490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.2433659490
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.484117019
Short name T714
Test name
Test status
Simulation time 43352170 ps
CPU time 0.74 seconds
Started Jun 11 12:28:03 PM PDT 24
Finished Jun 11 12:28:05 PM PDT 24
Peak memory 195128 kb
Host smart-f52818b5-ba92-4cc2-9a79-1b9eaec87538
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484117019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.484117019
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.271271862
Short name T331
Test name
Test status
Simulation time 7264835077 ps
CPU time 173.66 seconds
Started Jun 11 12:28:27 PM PDT 24
Finished Jun 11 12:31:23 PM PDT 24
Peak memory 198072 kb
Host smart-5a29d0f9-faba-4dfb-a44d-bb67ce17b1af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271271862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.g
pio_stress_all.271271862
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.2490115342
Short name T185
Test name
Test status
Simulation time 14224408 ps
CPU time 0.6 seconds
Started Jun 11 12:28:06 PM PDT 24
Finished Jun 11 12:28:09 PM PDT 24
Peak memory 193816 kb
Host smart-05f0e8d3-7089-4c64-b935-d2d81d72ead8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490115342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.2490115342
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.2591544689
Short name T524
Test name
Test status
Simulation time 201313669 ps
CPU time 0.88 seconds
Started Jun 11 12:28:17 PM PDT 24
Finished Jun 11 12:28:20 PM PDT 24
Peak memory 196600 kb
Host smart-dc524d08-10bd-4b38-9180-93de80472b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591544689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.2591544689
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.2007279300
Short name T192
Test name
Test status
Simulation time 3164514963 ps
CPU time 26.68 seconds
Started Jun 11 12:28:07 PM PDT 24
Finished Jun 11 12:28:36 PM PDT 24
Peak memory 197428 kb
Host smart-1dbca77d-6528-4436-a59c-80014bbc1576
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007279300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.2007279300
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.3083006038
Short name T408
Test name
Test status
Simulation time 65984880 ps
CPU time 0.87 seconds
Started Jun 11 12:28:07 PM PDT 24
Finished Jun 11 12:28:10 PM PDT 24
Peak memory 196032 kb
Host smart-ce075cd4-f868-4890-9713-48bd1e416a6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083006038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.3083006038
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.1714272508
Short name T536
Test name
Test status
Simulation time 33257054 ps
CPU time 0.95 seconds
Started Jun 11 12:28:16 PM PDT 24
Finished Jun 11 12:28:19 PM PDT 24
Peak memory 195680 kb
Host smart-0090dcc7-28b0-4177-b61a-7bc9d178c163
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714272508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.1714272508
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.1523973002
Short name T462
Test name
Test status
Simulation time 151363818 ps
CPU time 2.8 seconds
Started Jun 11 12:28:07 PM PDT 24
Finished Jun 11 12:28:12 PM PDT 24
Peak memory 197960 kb
Host smart-959135aa-32af-49fb-8c1b-c1b17a6fef4f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523973002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.1523973002
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.1690848178
Short name T208
Test name
Test status
Simulation time 81530477 ps
CPU time 2.22 seconds
Started Jun 11 12:28:08 PM PDT 24
Finished Jun 11 12:28:13 PM PDT 24
Peak memory 197988 kb
Host smart-97a9ef1a-8cb2-4f40-b3d2-e1febf9d4185
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690848178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.1690848178
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.3320360581
Short name T412
Test name
Test status
Simulation time 18564051 ps
CPU time 0.69 seconds
Started Jun 11 12:28:17 PM PDT 24
Finished Jun 11 12:28:19 PM PDT 24
Peak memory 194156 kb
Host smart-89552da2-5456-45b2-a919-977dc2930e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320360581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.3320360581
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.4199886627
Short name T605
Test name
Test status
Simulation time 93211321 ps
CPU time 1.04 seconds
Started Jun 11 12:28:07 PM PDT 24
Finished Jun 11 12:28:11 PM PDT 24
Peak memory 196672 kb
Host smart-ca05bb82-1856-4fec-910f-c2c9951e9691
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199886627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.4199886627
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.2064846466
Short name T507
Test name
Test status
Simulation time 246170556 ps
CPU time 5.4 seconds
Started Jun 11 12:28:18 PM PDT 24
Finished Jun 11 12:28:25 PM PDT 24
Peak memory 197896 kb
Host smart-b6c96b69-a84e-47c7-b66a-16ba7f6b1d62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064846466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.2064846466
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.4290658176
Short name T309
Test name
Test status
Simulation time 47730753 ps
CPU time 0.89 seconds
Started Jun 11 12:28:08 PM PDT 24
Finished Jun 11 12:28:11 PM PDT 24
Peak memory 195452 kb
Host smart-611806a1-5ef0-4194-be82-8a9bce20a074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290658176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.4290658176
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.2855381791
Short name T619
Test name
Test status
Simulation time 84924812 ps
CPU time 0.93 seconds
Started Jun 11 12:28:17 PM PDT 24
Finished Jun 11 12:28:20 PM PDT 24
Peak memory 196328 kb
Host smart-c2062117-857f-487b-b9e9-b8ffab968237
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855381791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.2855381791
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.3760676324
Short name T643
Test name
Test status
Simulation time 10110884399 ps
CPU time 142.06 seconds
Started Jun 11 12:28:11 PM PDT 24
Finished Jun 11 12:30:35 PM PDT 24
Peak memory 198132 kb
Host smart-766db8bd-ad27-4331-b0d8-9bb7278cf3e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760676324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.3760676324
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.2583475946
Short name T649
Test name
Test status
Simulation time 12381596 ps
CPU time 0.55 seconds
Started Jun 11 12:27:12 PM PDT 24
Finished Jun 11 12:27:16 PM PDT 24
Peak memory 193704 kb
Host smart-7feb2348-2b02-4213-927f-e14ed769af69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583475946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.2583475946
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.3343962398
Short name T162
Test name
Test status
Simulation time 21645928 ps
CPU time 0.58 seconds
Started Jun 11 12:27:13 PM PDT 24
Finished Jun 11 12:27:16 PM PDT 24
Peak memory 193804 kb
Host smart-954baadd-4c0c-49e7-bc22-6e750c18db91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343962398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.3343962398
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.152087609
Short name T425
Test name
Test status
Simulation time 211235868 ps
CPU time 10.26 seconds
Started Jun 11 12:27:10 PM PDT 24
Finished Jun 11 12:27:22 PM PDT 24
Peak memory 197924 kb
Host smart-db9c5948-ec86-4fee-8df7-135caff105b4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152087609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stress
.152087609
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.4092517122
Short name T7
Test name
Test status
Simulation time 82455546 ps
CPU time 0.99 seconds
Started Jun 11 12:27:09 PM PDT 24
Finished Jun 11 12:27:12 PM PDT 24
Peak memory 196560 kb
Host smart-8abae7bb-3c11-42d4-a80c-508d97bd21d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092517122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.4092517122
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.2570012568
Short name T584
Test name
Test status
Simulation time 233815347 ps
CPU time 1.08 seconds
Started Jun 11 12:27:15 PM PDT 24
Finished Jun 11 12:27:18 PM PDT 24
Peak memory 195784 kb
Host smart-9910dd1e-d7c0-4528-9932-d4769da3e926
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570012568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.2570012568
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.3601979373
Short name T535
Test name
Test status
Simulation time 69690780 ps
CPU time 1.5 seconds
Started Jun 11 12:27:15 PM PDT 24
Finished Jun 11 12:27:18 PM PDT 24
Peak memory 196572 kb
Host smart-08f9a741-a796-4cc3-a634-964676917777
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601979373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.3601979373
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.2300810090
Short name T101
Test name
Test status
Simulation time 633099879 ps
CPU time 2.33 seconds
Started Jun 11 12:27:13 PM PDT 24
Finished Jun 11 12:27:18 PM PDT 24
Peak memory 195252 kb
Host smart-4288db6c-0ff8-4c02-85b9-ebb2cbbc21b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300810090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
2300810090
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.2464259719
Short name T190
Test name
Test status
Simulation time 78054097 ps
CPU time 0.89 seconds
Started Jun 11 12:27:10 PM PDT 24
Finished Jun 11 12:27:14 PM PDT 24
Peak memory 195736 kb
Host smart-252ba6f9-d9d0-41ad-a61f-d5e29c6462bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464259719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.2464259719
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.375070140
Short name T116
Test name
Test status
Simulation time 116678149 ps
CPU time 0.86 seconds
Started Jun 11 12:27:09 PM PDT 24
Finished Jun 11 12:27:12 PM PDT 24
Peak memory 196604 kb
Host smart-ed171951-0fc9-4b53-b816-dc1df9c7f563
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375070140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup_
pulldown.375070140
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.2146636678
Short name T586
Test name
Test status
Simulation time 201482272 ps
CPU time 3.31 seconds
Started Jun 11 12:27:14 PM PDT 24
Finished Jun 11 12:27:20 PM PDT 24
Peak memory 197828 kb
Host smart-c463cdc6-5737-4762-bbbc-68bfedda7211
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146636678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.2146636678
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.1671516378
Short name T42
Test name
Test status
Simulation time 147530569 ps
CPU time 0.86 seconds
Started Jun 11 12:27:11 PM PDT 24
Finished Jun 11 12:27:15 PM PDT 24
Peak memory 213840 kb
Host smart-1b046bda-6580-4350-8ef5-280ca140525b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671516378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.1671516378
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.2546667777
Short name T217
Test name
Test status
Simulation time 259088659 ps
CPU time 1.13 seconds
Started Jun 11 12:27:16 PM PDT 24
Finished Jun 11 12:27:19 PM PDT 24
Peak memory 195592 kb
Host smart-3ab13fb5-f851-4a5e-a225-acd4464f1650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546667777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.2546667777
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.2485991108
Short name T261
Test name
Test status
Simulation time 67608479 ps
CPU time 1.15 seconds
Started Jun 11 12:27:12 PM PDT 24
Finished Jun 11 12:27:16 PM PDT 24
Peak memory 195752 kb
Host smart-8242cd31-9f63-4770-9972-22dc731287a1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485991108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.2485991108
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.1986644979
Short name T10
Test name
Test status
Simulation time 40061494259 ps
CPU time 49.06 seconds
Started Jun 11 12:27:11 PM PDT 24
Finished Jun 11 12:28:03 PM PDT 24
Peak memory 198088 kb
Host smart-e357fa7f-ba69-4a58-98b8-254c71f373a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986644979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.1986644979
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.1119339626
Short name T36
Test name
Test status
Simulation time 26610361509 ps
CPU time 416.52 seconds
Started Jun 11 12:27:13 PM PDT 24
Finished Jun 11 12:34:12 PM PDT 24
Peak memory 198432 kb
Host smart-850af512-63ea-496f-b212-ebde6dd4b204
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1119339626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.1119339626
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.3143972722
Short name T195
Test name
Test status
Simulation time 13549865 ps
CPU time 0.55 seconds
Started Jun 11 12:28:10 PM PDT 24
Finished Jun 11 12:28:13 PM PDT 24
Peak memory 194508 kb
Host smart-9e322b8f-e864-42ff-88ca-548a952efa01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143972722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.3143972722
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.1469804507
Short name T399
Test name
Test status
Simulation time 134390404 ps
CPU time 0.84 seconds
Started Jun 11 12:28:04 PM PDT 24
Finished Jun 11 12:28:06 PM PDT 24
Peak memory 195876 kb
Host smart-3ebe8571-ec76-4a69-9a1a-e248778cbd11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469804507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.1469804507
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.1949234264
Short name T626
Test name
Test status
Simulation time 155588606 ps
CPU time 7.68 seconds
Started Jun 11 12:28:16 PM PDT 24
Finished Jun 11 12:28:26 PM PDT 24
Peak memory 196776 kb
Host smart-63fbd017-73c5-447c-8b58-f9b2510a69e2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949234264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.1949234264
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.761632856
Short name T420
Test name
Test status
Simulation time 123190968 ps
CPU time 0.83 seconds
Started Jun 11 12:28:07 PM PDT 24
Finished Jun 11 12:28:10 PM PDT 24
Peak memory 195944 kb
Host smart-194e51e0-1000-4d0e-8807-1724905d7247
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761632856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.761632856
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.18702496
Short name T199
Test name
Test status
Simulation time 87405460 ps
CPU time 1.26 seconds
Started Jun 11 12:28:11 PM PDT 24
Finished Jun 11 12:28:14 PM PDT 24
Peak memory 196028 kb
Host smart-bf2709c8-a108-48a7-bc28-f4b14a4df2ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18702496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.18702496
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.1547727547
Short name T362
Test name
Test status
Simulation time 174123811 ps
CPU time 1.84 seconds
Started Jun 11 12:28:06 PM PDT 24
Finished Jun 11 12:28:09 PM PDT 24
Peak memory 197948 kb
Host smart-12bbb58b-61c4-4128-95bc-93ca9f62a736
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547727547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.1547727547
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.4202333974
Short name T226
Test name
Test status
Simulation time 193397812 ps
CPU time 2.16 seconds
Started Jun 11 12:28:04 PM PDT 24
Finished Jun 11 12:28:07 PM PDT 24
Peak memory 196896 kb
Host smart-59f0b8da-bcfd-467d-ade2-560d69ce7891
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202333974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.4202333974
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.3472408723
Short name T359
Test name
Test status
Simulation time 23612012 ps
CPU time 0.69 seconds
Started Jun 11 12:28:06 PM PDT 24
Finished Jun 11 12:28:08 PM PDT 24
Peak memory 196036 kb
Host smart-33eb620f-30b1-4c12-820e-633ae93e8aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472408723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.3472408723
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.79425265
Short name T107
Test name
Test status
Simulation time 88571497 ps
CPU time 1.05 seconds
Started Jun 11 12:28:05 PM PDT 24
Finished Jun 11 12:28:08 PM PDT 24
Peak memory 195816 kb
Host smart-4559668f-86c0-4712-9965-a45998bce846
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79425265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullup_
pulldown.79425265
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.1278829667
Short name T225
Test name
Test status
Simulation time 332410669 ps
CPU time 2.61 seconds
Started Jun 11 12:28:07 PM PDT 24
Finished Jun 11 12:28:16 PM PDT 24
Peak memory 197824 kb
Host smart-d431196a-07b2-44c7-9ff9-1d0e68229576
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278829667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.1278829667
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.1849342850
Short name T438
Test name
Test status
Simulation time 345651513 ps
CPU time 1.46 seconds
Started Jun 11 12:28:27 PM PDT 24
Finished Jun 11 12:28:31 PM PDT 24
Peak memory 196564 kb
Host smart-ac16b6b7-64a2-4b3f-917f-012de885c4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849342850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.1849342850
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.4237164855
Short name T242
Test name
Test status
Simulation time 124222683 ps
CPU time 1.39 seconds
Started Jun 11 12:28:04 PM PDT 24
Finished Jun 11 12:28:07 PM PDT 24
Peak memory 197880 kb
Host smart-1344d3c0-1994-4e96-adec-d51d91a930d7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237164855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.4237164855
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.1117381076
Short name T447
Test name
Test status
Simulation time 126540009791 ps
CPU time 190.14 seconds
Started Jun 11 12:28:19 PM PDT 24
Finished Jun 11 12:31:31 PM PDT 24
Peak memory 198084 kb
Host smart-79b0f45e-66a8-4935-ad4b-0c7cc7c9e262
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117381076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.1117381076
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.2920136267
Short name T353
Test name
Test status
Simulation time 41962963 ps
CPU time 0.56 seconds
Started Jun 11 12:28:23 PM PDT 24
Finished Jun 11 12:28:27 PM PDT 24
Peak memory 193780 kb
Host smart-609805f7-766a-4ebf-9bb9-b23cea133946
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920136267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.2920136267
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.4020983256
Short name T548
Test name
Test status
Simulation time 56500725 ps
CPU time 0.86 seconds
Started Jun 11 12:28:19 PM PDT 24
Finished Jun 11 12:28:23 PM PDT 24
Peak memory 195940 kb
Host smart-169b69ad-90f7-42ec-bc70-28c92463235f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020983256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.4020983256
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.2264748567
Short name T574
Test name
Test status
Simulation time 450059836 ps
CPU time 8.01 seconds
Started Jun 11 12:28:23 PM PDT 24
Finished Jun 11 12:28:34 PM PDT 24
Peak memory 196928 kb
Host smart-5f6dcc12-8753-4455-9a81-708e50f6823d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264748567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.2264748567
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.546033728
Short name T410
Test name
Test status
Simulation time 164513224 ps
CPU time 0.81 seconds
Started Jun 11 12:28:26 PM PDT 24
Finished Jun 11 12:28:30 PM PDT 24
Peak memory 195932 kb
Host smart-7881d013-8220-46d4-ba80-d6f78e357837
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546033728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.546033728
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.1716296629
Short name T411
Test name
Test status
Simulation time 77423496 ps
CPU time 1.33 seconds
Started Jun 11 12:28:03 PM PDT 24
Finished Jun 11 12:28:06 PM PDT 24
Peak memory 196492 kb
Host smart-de966be6-da22-48c4-a632-1501cdb8a0dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716296629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.1716296629
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.3690977772
Short name T315
Test name
Test status
Simulation time 90836015 ps
CPU time 3.32 seconds
Started Jun 11 12:28:22 PM PDT 24
Finished Jun 11 12:28:33 PM PDT 24
Peak memory 197852 kb
Host smart-5b91b854-3cfd-4b61-b761-a13bbcfbf941
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690977772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.3690977772
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.3821401866
Short name T684
Test name
Test status
Simulation time 260518227 ps
CPU time 2.78 seconds
Started Jun 11 12:28:18 PM PDT 24
Finished Jun 11 12:28:23 PM PDT 24
Peak memory 197092 kb
Host smart-f8f30fb4-0a82-4c15-897c-69d1f437f3a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821401866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.3821401866
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.3187953403
Short name T541
Test name
Test status
Simulation time 195602978 ps
CPU time 1.12 seconds
Started Jun 11 12:28:11 PM PDT 24
Finished Jun 11 12:28:14 PM PDT 24
Peak memory 196720 kb
Host smart-35eaa63a-bf73-4798-9b9d-0c0eca1000c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187953403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.3187953403
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.448020603
Short name T257
Test name
Test status
Simulation time 30168106 ps
CPU time 0.79 seconds
Started Jun 11 12:28:10 PM PDT 24
Finished Jun 11 12:28:13 PM PDT 24
Peak memory 195520 kb
Host smart-810bd7fd-736b-4d23-a3b0-b629d56900f3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448020603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullup
_pulldown.448020603
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.76622465
Short name T677
Test name
Test status
Simulation time 261002906 ps
CPU time 1.17 seconds
Started Jun 11 12:28:13 PM PDT 24
Finished Jun 11 12:28:16 PM PDT 24
Peak memory 197844 kb
Host smart-465366bc-fb09-4c27-8965-6abca32401d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76622465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand
om_long_reg_writes_reg_reads.76622465
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.488810485
Short name T617
Test name
Test status
Simulation time 179572916 ps
CPU time 0.93 seconds
Started Jun 11 12:28:13 PM PDT 24
Finished Jun 11 12:28:16 PM PDT 24
Peak memory 195792 kb
Host smart-704d04ec-d51b-400e-98a6-98875f35aa4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488810485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.488810485
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2374296018
Short name T241
Test name
Test status
Simulation time 115299730 ps
CPU time 1.1 seconds
Started Jun 11 12:28:14 PM PDT 24
Finished Jun 11 12:28:18 PM PDT 24
Peak memory 195700 kb
Host smart-1ba6993a-8d94-4e66-a016-37290afcd94b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374296018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.2374296018
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.1736698197
Short name T583
Test name
Test status
Simulation time 1951779056 ps
CPU time 26.35 seconds
Started Jun 11 12:28:24 PM PDT 24
Finished Jun 11 12:28:54 PM PDT 24
Peak memory 198016 kb
Host smart-3f005a70-8135-4775-b9fc-e89461d0ce16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736698197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.1736698197
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.922240531
Short name T389
Test name
Test status
Simulation time 32712496097 ps
CPU time 697.32 seconds
Started Jun 11 12:28:21 PM PDT 24
Finished Jun 11 12:40:02 PM PDT 24
Peak memory 198124 kb
Host smart-8329fc3c-73c0-4780-8816-e68b084146a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=922240531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.922240531
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.1244706877
Short name T333
Test name
Test status
Simulation time 41115540 ps
CPU time 0.57 seconds
Started Jun 11 12:28:18 PM PDT 24
Finished Jun 11 12:28:21 PM PDT 24
Peak memory 194516 kb
Host smart-02525b6c-8fbc-41d3-9503-4e2fe52d1cb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244706877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.1244706877
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.745583245
Short name T525
Test name
Test status
Simulation time 41480736 ps
CPU time 0.81 seconds
Started Jun 11 12:28:20 PM PDT 24
Finished Jun 11 12:28:24 PM PDT 24
Peak memory 195348 kb
Host smart-a215b8cb-bcd5-45e1-9fee-2f80c593dd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745583245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.745583245
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.1786164388
Short name T577
Test name
Test status
Simulation time 3270223732 ps
CPU time 23.44 seconds
Started Jun 11 12:28:10 PM PDT 24
Finished Jun 11 12:28:36 PM PDT 24
Peak memory 197984 kb
Host smart-ee163513-044f-49e9-9766-7490bc6b37eb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786164388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.1786164388
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.2728121287
Short name T104
Test name
Test status
Simulation time 164498852 ps
CPU time 0.7 seconds
Started Jun 11 12:28:25 PM PDT 24
Finished Jun 11 12:28:29 PM PDT 24
Peak memory 195840 kb
Host smart-3457e740-5b8d-4730-9155-7471ea8c0399
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728121287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.2728121287
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.2648036826
Short name T334
Test name
Test status
Simulation time 81228241 ps
CPU time 1.1 seconds
Started Jun 11 12:28:12 PM PDT 24
Finished Jun 11 12:28:15 PM PDT 24
Peak memory 195644 kb
Host smart-6ab1eb38-739f-4f28-94e6-edd6651896b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648036826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.2648036826
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.2732418187
Short name T701
Test name
Test status
Simulation time 347910074 ps
CPU time 2.43 seconds
Started Jun 11 12:28:21 PM PDT 24
Finished Jun 11 12:28:27 PM PDT 24
Peak memory 196256 kb
Host smart-24d4528a-d787-45da-8438-bd9df3941775
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732418187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.2732418187
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.12690262
Short name T580
Test name
Test status
Simulation time 233080655 ps
CPU time 1.76 seconds
Started Jun 11 12:28:20 PM PDT 24
Finished Jun 11 12:28:25 PM PDT 24
Peak memory 196132 kb
Host smart-06e2b75f-3440-406a-a909-bd5e77d4873c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12690262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger.12690262
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.3305182176
Short name T494
Test name
Test status
Simulation time 276270836 ps
CPU time 1.28 seconds
Started Jun 11 12:28:14 PM PDT 24
Finished Jun 11 12:28:17 PM PDT 24
Peak memory 196960 kb
Host smart-f120beea-6949-4a38-9611-8c63464f6bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305182176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.3305182176
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.863131381
Short name T319
Test name
Test status
Simulation time 134081528 ps
CPU time 0.9 seconds
Started Jun 11 12:28:26 PM PDT 24
Finished Jun 11 12:28:30 PM PDT 24
Peak memory 195700 kb
Host smart-b86a589d-4299-4629-b96f-12a375a3b298
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863131381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullup
_pulldown.863131381
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.2776686632
Short name T3
Test name
Test status
Simulation time 500573708 ps
CPU time 3.02 seconds
Started Jun 11 12:28:18 PM PDT 24
Finished Jun 11 12:28:23 PM PDT 24
Peak memory 197908 kb
Host smart-bc77a348-7ab9-4add-bbb0-8b67da419814
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776686632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.2776686632
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.2630494811
Short name T205
Test name
Test status
Simulation time 56708252 ps
CPU time 1.02 seconds
Started Jun 11 12:28:19 PM PDT 24
Finished Jun 11 12:28:22 PM PDT 24
Peak memory 195364 kb
Host smart-4e916513-ce39-4b67-be35-7f2a9fbbf2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630494811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.2630494811
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.4129216471
Short name T502
Test name
Test status
Simulation time 241742185 ps
CPU time 1.06 seconds
Started Jun 11 12:28:13 PM PDT 24
Finished Jun 11 12:28:16 PM PDT 24
Peak memory 195684 kb
Host smart-f6e0ab06-4340-45fd-8bb5-d5920dfe0163
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129216471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.4129216471
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.120252931
Short name T21
Test name
Test status
Simulation time 38398821582 ps
CPU time 105.26 seconds
Started Jun 11 12:28:14 PM PDT 24
Finished Jun 11 12:30:01 PM PDT 24
Peak memory 198032 kb
Host smart-732d2b67-b6e6-4abf-9e2b-a705edeb10c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120252931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.g
pio_stress_all.120252931
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.3698683497
Short name T405
Test name
Test status
Simulation time 123818700149 ps
CPU time 2449.95 seconds
Started Jun 11 12:28:14 PM PDT 24
Finished Jun 11 01:09:06 PM PDT 24
Peak memory 198120 kb
Host smart-2131f261-dd67-43ad-9aa5-1a4f0fa221ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3698683497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.3698683497
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.1166055802
Short name T533
Test name
Test status
Simulation time 12407638 ps
CPU time 0.62 seconds
Started Jun 11 12:28:44 PM PDT 24
Finished Jun 11 12:28:46 PM PDT 24
Peak memory 194536 kb
Host smart-ea8b52a3-3de0-487a-9c50-1ec794625e75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166055802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.1166055802
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.2223328670
Short name T487
Test name
Test status
Simulation time 74827135 ps
CPU time 0.86 seconds
Started Jun 11 12:28:14 PM PDT 24
Finished Jun 11 12:28:17 PM PDT 24
Peak memory 196296 kb
Host smart-13623f8b-8c2d-46f0-9616-1c5b7aeac384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223328670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.2223328670
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.3927927853
Short name T127
Test name
Test status
Simulation time 733433373 ps
CPU time 19.38 seconds
Started Jun 11 12:28:21 PM PDT 24
Finished Jun 11 12:28:43 PM PDT 24
Peak memory 195448 kb
Host smart-66ab5250-caf9-495a-9179-4da717a3e2a8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927927853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.3927927853
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.1915789039
Short name T522
Test name
Test status
Simulation time 221399252 ps
CPU time 0.91 seconds
Started Jun 11 12:28:33 PM PDT 24
Finished Jun 11 12:28:34 PM PDT 24
Peak memory 197056 kb
Host smart-794c1f13-767f-4c9b-bd42-22b8a17c519d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915789039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.1915789039
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.675563908
Short name T432
Test name
Test status
Simulation time 582525844 ps
CPU time 1.37 seconds
Started Jun 11 12:28:14 PM PDT 24
Finished Jun 11 12:28:17 PM PDT 24
Peak memory 198012 kb
Host smart-5f4a6537-eede-4a0f-931c-2a38d7746796
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675563908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.675563908
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.1568536145
Short name T479
Test name
Test status
Simulation time 90848176 ps
CPU time 3.44 seconds
Started Jun 11 12:28:28 PM PDT 24
Finished Jun 11 12:28:33 PM PDT 24
Peak memory 197952 kb
Host smart-5545171b-4f61-4111-9aeb-d66a736cc621
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568536145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.1568536145
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.3348166050
Short name T519
Test name
Test status
Simulation time 552524118 ps
CPU time 2.61 seconds
Started Jun 11 12:28:18 PM PDT 24
Finished Jun 11 12:28:24 PM PDT 24
Peak memory 196360 kb
Host smart-17f99983-37a8-4a49-a754-3336ad889741
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348166050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.3348166050
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.617927747
Short name T67
Test name
Test status
Simulation time 38164829 ps
CPU time 0.98 seconds
Started Jun 11 12:28:24 PM PDT 24
Finished Jun 11 12:28:29 PM PDT 24
Peak memory 196028 kb
Host smart-b696196a-8951-4031-bb4f-f05c2e47cedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617927747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.617927747
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.290073386
Short name T56
Test name
Test status
Simulation time 48948772 ps
CPU time 0.95 seconds
Started Jun 11 12:28:28 PM PDT 24
Finished Jun 11 12:28:31 PM PDT 24
Peak memory 196616 kb
Host smart-2851c1ac-1dc4-4966-a57e-1e75bcba2be4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290073386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullup
_pulldown.290073386
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.612724860
Short name T294
Test name
Test status
Simulation time 578042349 ps
CPU time 2.75 seconds
Started Jun 11 12:28:24 PM PDT 24
Finished Jun 11 12:28:30 PM PDT 24
Peak memory 197872 kb
Host smart-c0a7cf30-5f6f-4e61-b9d9-212454a4f9f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612724860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ran
dom_long_reg_writes_reg_reads.612724860
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.709054671
Short name T253
Test name
Test status
Simulation time 806806304 ps
CPU time 1.01 seconds
Started Jun 11 12:28:33 PM PDT 24
Finished Jun 11 12:28:35 PM PDT 24
Peak memory 195528 kb
Host smart-bf206638-5d70-4445-bfcf-1f457d3fd5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709054671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.709054671
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.1711264605
Short name T332
Test name
Test status
Simulation time 59546223 ps
CPU time 1.01 seconds
Started Jun 11 12:28:20 PM PDT 24
Finished Jun 11 12:28:25 PM PDT 24
Peak memory 195596 kb
Host smart-52166db3-fdfa-4d22-b956-53593ebad258
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711264605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.1711264605
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.3191738700
Short name T146
Test name
Test status
Simulation time 27509320322 ps
CPU time 200.63 seconds
Started Jun 11 12:28:19 PM PDT 24
Finished Jun 11 12:31:42 PM PDT 24
Peak memory 197932 kb
Host smart-14a8702d-2bcc-41aa-8077-ea1f77acc3fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191738700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.3191738700
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.1404732219
Short name T509
Test name
Test status
Simulation time 16741615 ps
CPU time 0.59 seconds
Started Jun 11 12:28:18 PM PDT 24
Finished Jun 11 12:28:20 PM PDT 24
Peak memory 193796 kb
Host smart-5ba93f19-12b3-40fa-9c70-0f46211fb3e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404732219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.1404732219
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.1349916475
Short name T491
Test name
Test status
Simulation time 129659244 ps
CPU time 0.82 seconds
Started Jun 11 12:28:22 PM PDT 24
Finished Jun 11 12:28:26 PM PDT 24
Peak memory 195224 kb
Host smart-978c7e7f-ec3e-4a23-955d-349b72812bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349916475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.1349916475
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.2761378193
Short name T688
Test name
Test status
Simulation time 1622962830 ps
CPU time 21.33 seconds
Started Jun 11 12:28:14 PM PDT 24
Finished Jun 11 12:28:37 PM PDT 24
Peak memory 196084 kb
Host smart-b2f09b24-eb00-4dd4-b56a-46402e7d81f5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761378193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.2761378193
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.1091706399
Short name T20
Test name
Test status
Simulation time 85939870 ps
CPU time 0.61 seconds
Started Jun 11 12:28:25 PM PDT 24
Finished Jun 11 12:28:29 PM PDT 24
Peak memory 194472 kb
Host smart-c6fd65c8-bd4a-431c-b37f-6ded72eec9e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091706399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.1091706399
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.3036215724
Short name T258
Test name
Test status
Simulation time 384464641 ps
CPU time 1.45 seconds
Started Jun 11 12:28:14 PM PDT 24
Finished Jun 11 12:28:17 PM PDT 24
Peak memory 197984 kb
Host smart-620752b3-fb4c-44b0-8a9f-d38524bc872d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036215724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.3036215724
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.2989288079
Short name T164
Test name
Test status
Simulation time 35796285 ps
CPU time 1.36 seconds
Started Jun 11 12:28:20 PM PDT 24
Finished Jun 11 12:28:23 PM PDT 24
Peak memory 196748 kb
Host smart-814244b1-0089-46a2-a665-144cb58a6728
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989288079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.2989288079
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.590495489
Short name T201
Test name
Test status
Simulation time 115530260 ps
CPU time 0.93 seconds
Started Jun 11 12:28:26 PM PDT 24
Finished Jun 11 12:28:30 PM PDT 24
Peak memory 195264 kb
Host smart-280d0204-fd30-4769-96ba-4dd056cd4122
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590495489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger.
590495489
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.3232457979
Short name T70
Test name
Test status
Simulation time 60728325 ps
CPU time 0.67 seconds
Started Jun 11 12:28:23 PM PDT 24
Finished Jun 11 12:28:27 PM PDT 24
Peak memory 194304 kb
Host smart-fafe9baa-aec3-4b6f-bda3-048bd925d3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232457979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.3232457979
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.2655591717
Short name T17
Test name
Test status
Simulation time 674382579 ps
CPU time 0.94 seconds
Started Jun 11 12:28:20 PM PDT 24
Finished Jun 11 12:28:24 PM PDT 24
Peak memory 195616 kb
Host smart-1bc59265-8003-4653-b095-c759526ea4ff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655591717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.2655591717
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.3973202719
Short name T431
Test name
Test status
Simulation time 61350862 ps
CPU time 1.5 seconds
Started Jun 11 12:28:25 PM PDT 24
Finished Jun 11 12:28:30 PM PDT 24
Peak memory 198124 kb
Host smart-cc928da1-08e0-40d3-bb55-71e6cb354928
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973202719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.3973202719
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.1057283805
Short name T280
Test name
Test status
Simulation time 94088225 ps
CPU time 0.78 seconds
Started Jun 11 12:28:26 PM PDT 24
Finished Jun 11 12:28:30 PM PDT 24
Peak memory 195124 kb
Host smart-87d6afef-f886-4ead-8819-a56863477389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057283805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.1057283805
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.1324795631
Short name T417
Test name
Test status
Simulation time 185750449 ps
CPU time 0.96 seconds
Started Jun 11 12:28:25 PM PDT 24
Finished Jun 11 12:28:29 PM PDT 24
Peak memory 195712 kb
Host smart-058f2ef6-d21f-49a6-9a5a-6bc13ac723b8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324795631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.1324795631
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.2111716245
Short name T480
Test name
Test status
Simulation time 13770539682 ps
CPU time 183.56 seconds
Started Jun 11 12:28:31 PM PDT 24
Finished Jun 11 12:31:36 PM PDT 24
Peak memory 198108 kb
Host smart-876277e4-7037-46c9-8d76-024c6e87708f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111716245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.2111716245
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.1245252842
Short name T500
Test name
Test status
Simulation time 114513757765 ps
CPU time 1578.87 seconds
Started Jun 11 12:28:21 PM PDT 24
Finished Jun 11 12:54:43 PM PDT 24
Peak memory 198076 kb
Host smart-56ad8714-cbf4-4703-b21c-032a60cd166a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1245252842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.1245252842
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.2031532135
Short name T445
Test name
Test status
Simulation time 90265837 ps
CPU time 0.54 seconds
Started Jun 11 12:28:26 PM PDT 24
Finished Jun 11 12:28:30 PM PDT 24
Peak memory 193828 kb
Host smart-9201534c-f13d-4f00-b95e-fcb205ba4532
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031532135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.2031532135
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.145461817
Short name T255
Test name
Test status
Simulation time 96580046 ps
CPU time 0.63 seconds
Started Jun 11 12:28:21 PM PDT 24
Finished Jun 11 12:28:25 PM PDT 24
Peak memory 193964 kb
Host smart-8ab9a96b-ad83-4e45-bd07-2e7f792edf59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145461817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.145461817
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.1180582985
Short name T342
Test name
Test status
Simulation time 430002252 ps
CPU time 11.38 seconds
Started Jun 11 12:28:23 PM PDT 24
Finished Jun 11 12:28:38 PM PDT 24
Peak memory 196880 kb
Host smart-ef4d960e-8c1b-4658-8e4c-691835770b06
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180582985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.1180582985
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.2305591980
Short name T452
Test name
Test status
Simulation time 197711933 ps
CPU time 0.86 seconds
Started Jun 11 12:28:22 PM PDT 24
Finished Jun 11 12:28:26 PM PDT 24
Peak memory 197864 kb
Host smart-07efe715-e7aa-4a5c-9408-1432d717187b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305591980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2305591980
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.2761499747
Short name T631
Test name
Test status
Simulation time 272734212 ps
CPU time 1.09 seconds
Started Jun 11 12:28:16 PM PDT 24
Finished Jun 11 12:28:19 PM PDT 24
Peak memory 195884 kb
Host smart-9a48b4d2-4b59-4a07-8218-559ed1793362
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761499747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.2761499747
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.2919005256
Short name T246
Test name
Test status
Simulation time 88515397 ps
CPU time 1.83 seconds
Started Jun 11 12:28:29 PM PDT 24
Finished Jun 11 12:28:33 PM PDT 24
Peak memory 198000 kb
Host smart-cf4cade1-dbe3-4a33-8cef-a979f3a2cad8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919005256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.2919005256
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.2451241385
Short name T134
Test name
Test status
Simulation time 499688403 ps
CPU time 1.34 seconds
Started Jun 11 12:28:25 PM PDT 24
Finished Jun 11 12:28:30 PM PDT 24
Peak memory 196560 kb
Host smart-cf6b4e1b-924e-462c-9e6e-ba8f929b3e62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451241385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.2451241385
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.3435306328
Short name T337
Test name
Test status
Simulation time 56632572 ps
CPU time 0.66 seconds
Started Jun 11 12:28:25 PM PDT 24
Finished Jun 11 12:28:29 PM PDT 24
Peak memory 196076 kb
Host smart-1dfa3ccf-907e-486d-91d8-063afa17010e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435306328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.3435306328
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.407828011
Short name T345
Test name
Test status
Simulation time 179061315 ps
CPU time 1.19 seconds
Started Jun 11 12:28:20 PM PDT 24
Finished Jun 11 12:28:29 PM PDT 24
Peak memory 196956 kb
Host smart-2831cec2-f2fe-4165-aab9-c98555cdb40d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407828011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullup
_pulldown.407828011
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.3383646967
Short name T243
Test name
Test status
Simulation time 1316945412 ps
CPU time 5.43 seconds
Started Jun 11 12:28:14 PM PDT 24
Finished Jun 11 12:28:21 PM PDT 24
Peak memory 197804 kb
Host smart-52bab951-091a-47b8-800c-8fb8a910db5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383646967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.3383646967
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.3245393960
Short name T260
Test name
Test status
Simulation time 192128265 ps
CPU time 1.19 seconds
Started Jun 11 12:28:22 PM PDT 24
Finished Jun 11 12:28:26 PM PDT 24
Peak memory 195548 kb
Host smart-51a391c1-b357-4eca-9b99-7549bd5c3a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245393960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.3245393960
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.4280021408
Short name T296
Test name
Test status
Simulation time 114606878 ps
CPU time 0.92 seconds
Started Jun 11 12:28:22 PM PDT 24
Finished Jun 11 12:28:27 PM PDT 24
Peak memory 195380 kb
Host smart-3d4114fa-c1c9-4c28-9e62-0a5ac71666d4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280021408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.4280021408
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.4094518838
Short name T4
Test name
Test status
Simulation time 13840116595 ps
CPU time 140.44 seconds
Started Jun 11 12:28:27 PM PDT 24
Finished Jun 11 12:30:55 PM PDT 24
Peak memory 198120 kb
Host smart-273fa889-688c-48e5-b342-7e56b7d80eda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094518838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.4094518838
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.3690174963
Short name T691
Test name
Test status
Simulation time 25877292 ps
CPU time 0.57 seconds
Started Jun 11 12:28:24 PM PDT 24
Finished Jun 11 12:28:28 PM PDT 24
Peak memory 194016 kb
Host smart-90642b8d-fded-4343-aaf1-d70143eefbe2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690174963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.3690174963
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.2342058343
Short name T304
Test name
Test status
Simulation time 72933659 ps
CPU time 0.78 seconds
Started Jun 11 12:28:28 PM PDT 24
Finished Jun 11 12:28:31 PM PDT 24
Peak memory 195208 kb
Host smart-c49a179d-a1a2-422b-9c58-794d0ae5e648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342058343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.2342058343
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.3913254716
Short name T343
Test name
Test status
Simulation time 634814245 ps
CPU time 17.93 seconds
Started Jun 11 12:28:22 PM PDT 24
Finished Jun 11 12:28:44 PM PDT 24
Peak memory 196440 kb
Host smart-5689dc23-2612-4ad7-87be-d3f1ed3637c2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913254716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.3913254716
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.4020589010
Short name T34
Test name
Test status
Simulation time 553686303 ps
CPU time 0.81 seconds
Started Jun 11 12:28:20 PM PDT 24
Finished Jun 11 12:28:23 PM PDT 24
Peak memory 196512 kb
Host smart-33168e2f-df79-41ed-b7dd-410e5c0d22bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020589010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.4020589010
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.1265402715
Short name T215
Test name
Test status
Simulation time 231464825 ps
CPU time 0.85 seconds
Started Jun 11 12:28:22 PM PDT 24
Finished Jun 11 12:28:27 PM PDT 24
Peak memory 197332 kb
Host smart-e0694d3f-e326-491e-93bb-df306c36b1ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265402715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.1265402715
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.2805003207
Short name T240
Test name
Test status
Simulation time 21932244 ps
CPU time 0.86 seconds
Started Jun 11 12:28:25 PM PDT 24
Finished Jun 11 12:28:29 PM PDT 24
Peak memory 196160 kb
Host smart-365f2888-d197-4511-93bd-82c254673d4d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805003207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.2805003207
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.1534487122
Short name T372
Test name
Test status
Simulation time 159647806 ps
CPU time 0.93 seconds
Started Jun 11 12:28:20 PM PDT 24
Finished Jun 11 12:28:23 PM PDT 24
Peak memory 196184 kb
Host smart-ea51e3b6-02c9-4309-8fbd-0e0fc042ea43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534487122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.1534487122
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.3493116539
Short name T363
Test name
Test status
Simulation time 90771784 ps
CPU time 1.01 seconds
Started Jun 11 12:28:22 PM PDT 24
Finished Jun 11 12:28:27 PM PDT 24
Peak memory 195720 kb
Host smart-5bc93788-7d1c-4afa-9f98-4772df354a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493116539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.3493116539
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.33740663
Short name T667
Test name
Test status
Simulation time 49323142 ps
CPU time 1.03 seconds
Started Jun 11 12:28:20 PM PDT 24
Finished Jun 11 12:28:24 PM PDT 24
Peak memory 196440 kb
Host smart-fb19c80b-8e27-4989-bf11-02c7a208c50b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33740663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullup_
pulldown.33740663
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.3243149002
Short name T145
Test name
Test status
Simulation time 131979512 ps
CPU time 1.77 seconds
Started Jun 11 12:28:21 PM PDT 24
Finished Jun 11 12:28:26 PM PDT 24
Peak memory 197864 kb
Host smart-65b2054c-1459-48bc-9f06-c09f20889722
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243149002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.3243149002
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.1092581713
Short name T297
Test name
Test status
Simulation time 69664674 ps
CPU time 1.14 seconds
Started Jun 11 12:28:27 PM PDT 24
Finished Jun 11 12:28:31 PM PDT 24
Peak memory 195664 kb
Host smart-f306807a-1972-4257-bbe5-888bc963ac95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092581713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.1092581713
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.1049891283
Short name T435
Test name
Test status
Simulation time 76358116 ps
CPU time 0.85 seconds
Started Jun 11 12:28:21 PM PDT 24
Finished Jun 11 12:28:25 PM PDT 24
Peak memory 196092 kb
Host smart-df8ebfb1-e55a-4dbc-9998-421147209ca4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049891283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.1049891283
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.3621109995
Short name T161
Test name
Test status
Simulation time 5628365902 ps
CPU time 135.6 seconds
Started Jun 11 12:28:20 PM PDT 24
Finished Jun 11 12:30:38 PM PDT 24
Peak memory 198064 kb
Host smart-a88a91aa-3e3d-476d-a253-3aaf33c42a5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621109995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.3621109995
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.1536162000
Short name T364
Test name
Test status
Simulation time 14398293 ps
CPU time 0.54 seconds
Started Jun 11 12:28:18 PM PDT 24
Finished Jun 11 12:28:21 PM PDT 24
Peak memory 193832 kb
Host smart-cc4d2467-3097-4c5b-afc5-57acf305cfac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536162000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.1536162000
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.4008935226
Short name T203
Test name
Test status
Simulation time 15969527 ps
CPU time 0.71 seconds
Started Jun 11 12:28:21 PM PDT 24
Finished Jun 11 12:28:25 PM PDT 24
Peak memory 193980 kb
Host smart-0b80d241-542a-44b8-8217-8fd5bbff686f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008935226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.4008935226
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.1957620675
Short name T108
Test name
Test status
Simulation time 5202378592 ps
CPU time 20.01 seconds
Started Jun 11 12:28:20 PM PDT 24
Finished Jun 11 12:28:44 PM PDT 24
Peak memory 196756 kb
Host smart-083fae36-b895-4a48-bdc7-e726828d7713
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957620675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.1957620675
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.2227202557
Short name T386
Test name
Test status
Simulation time 476449641 ps
CPU time 0.83 seconds
Started Jun 11 12:28:28 PM PDT 24
Finished Jun 11 12:28:31 PM PDT 24
Peak memory 197164 kb
Host smart-ca3d0714-19bb-4f58-ae30-3bf3116fed43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227202557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.2227202557
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.2047491258
Short name T27
Test name
Test status
Simulation time 86799151 ps
CPU time 0.86 seconds
Started Jun 11 12:28:28 PM PDT 24
Finished Jun 11 12:28:31 PM PDT 24
Peak memory 196420 kb
Host smart-a568f225-954c-4393-a2d5-1174d8bf1c5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047491258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.2047491258
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.3109391093
Short name T493
Test name
Test status
Simulation time 168341578 ps
CPU time 3.03 seconds
Started Jun 11 12:28:24 PM PDT 24
Finished Jun 11 12:28:30 PM PDT 24
Peak memory 197608 kb
Host smart-0cfe079d-59af-4fd8-9b02-9ddd3668fe18
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109391093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.3109391093
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.3222816830
Short name T290
Test name
Test status
Simulation time 619362103 ps
CPU time 1.57 seconds
Started Jun 11 12:28:34 PM PDT 24
Finished Jun 11 12:28:37 PM PDT 24
Peak memory 195956 kb
Host smart-a8419cae-a2a8-4cb9-a28f-c96d306affcc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222816830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.3222816830
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.1575643798
Short name T526
Test name
Test status
Simulation time 88219469 ps
CPU time 0.97 seconds
Started Jun 11 12:28:22 PM PDT 24
Finished Jun 11 12:28:26 PM PDT 24
Peak memory 195884 kb
Host smart-038c5bef-56df-4b18-b5f1-14935f9f9871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575643798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.1575643798
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.3364291499
Short name T172
Test name
Test status
Simulation time 81233732 ps
CPU time 0.92 seconds
Started Jun 11 12:28:26 PM PDT 24
Finished Jun 11 12:28:30 PM PDT 24
Peak memory 196264 kb
Host smart-1750a031-4222-40d1-bc29-e6b8ebde75b0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364291499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.3364291499
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.981570304
Short name T273
Test name
Test status
Simulation time 2240088860 ps
CPU time 2.46 seconds
Started Jun 11 12:28:25 PM PDT 24
Finished Jun 11 12:28:30 PM PDT 24
Peak memory 198260 kb
Host smart-e9caaadc-ea1d-498e-97ee-926113eec357
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981570304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ran
dom_long_reg_writes_reg_reads.981570304
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.979258696
Short name T249
Test name
Test status
Simulation time 140185156 ps
CPU time 1.36 seconds
Started Jun 11 12:28:26 PM PDT 24
Finished Jun 11 12:28:30 PM PDT 24
Peak memory 196448 kb
Host smart-6896f10d-5cde-4292-a9ed-50dd7e16bd57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979258696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.979258696
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.3703091584
Short name T575
Test name
Test status
Simulation time 52383647 ps
CPU time 0.96 seconds
Started Jun 11 12:28:25 PM PDT 24
Finished Jun 11 12:28:29 PM PDT 24
Peak memory 196188 kb
Host smart-182b99b2-d85a-43cc-bc72-b579556ed64b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703091584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.3703091584
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.4223044058
Short name T560
Test name
Test status
Simulation time 38101736244 ps
CPU time 122.84 seconds
Started Jun 11 12:28:25 PM PDT 24
Finished Jun 11 12:30:31 PM PDT 24
Peak memory 198148 kb
Host smart-8ce95004-9fcc-44bd-8d8c-9990441b8a4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223044058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.4223044058
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.3907553850
Short name T26
Test name
Test status
Simulation time 80031014 ps
CPU time 0.59 seconds
Started Jun 11 12:28:41 PM PDT 24
Finished Jun 11 12:28:43 PM PDT 24
Peak memory 193972 kb
Host smart-ab5bd766-129e-4e4c-a44e-c001c532981a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907553850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.3907553850
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.127097664
Short name T374
Test name
Test status
Simulation time 22602776 ps
CPU time 0.72 seconds
Started Jun 11 12:28:38 PM PDT 24
Finished Jun 11 12:28:41 PM PDT 24
Peak memory 195860 kb
Host smart-c8f7c013-b226-4514-9932-f030485e9eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127097664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.127097664
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.526989998
Short name T645
Test name
Test status
Simulation time 2112526567 ps
CPU time 27.79 seconds
Started Jun 11 12:28:35 PM PDT 24
Finished Jun 11 12:29:04 PM PDT 24
Peak memory 196656 kb
Host smart-034d393b-2e28-4bdc-9409-a0f7f660b6e7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526989998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stres
s.526989998
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.3363273390
Short name T256
Test name
Test status
Simulation time 189954260 ps
CPU time 0.84 seconds
Started Jun 11 12:28:39 PM PDT 24
Finished Jun 11 12:28:41 PM PDT 24
Peak memory 195924 kb
Host smart-f1929c9c-a481-4fc5-8e49-e8b828ae11ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363273390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.3363273390
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.465120756
Short name T338
Test name
Test status
Simulation time 58464628 ps
CPU time 0.65 seconds
Started Jun 11 12:28:36 PM PDT 24
Finished Jun 11 12:28:38 PM PDT 24
Peak memory 194880 kb
Host smart-689d7503-2ce9-4e87-bfe1-623143f5b3c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465120756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.465120756
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.893441419
Short name T446
Test name
Test status
Simulation time 115849115 ps
CPU time 2.21 seconds
Started Jun 11 12:28:44 PM PDT 24
Finished Jun 11 12:28:46 PM PDT 24
Peak memory 196308 kb
Host smart-713bf21b-2acb-4374-af89-0cbd5cfde3ff
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893441419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.gpio_intr_with_filter_rand_intr_event.893441419
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.1167964243
Short name T367
Test name
Test status
Simulation time 267308325 ps
CPU time 1.57 seconds
Started Jun 11 12:28:46 PM PDT 24
Finished Jun 11 12:28:50 PM PDT 24
Peak memory 196644 kb
Host smart-495f396b-e280-4fba-a454-a421e858ad4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167964243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.1167964243
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.2055392629
Short name T457
Test name
Test status
Simulation time 27117654 ps
CPU time 0.97 seconds
Started Jun 11 12:28:22 PM PDT 24
Finished Jun 11 12:28:27 PM PDT 24
Peak memory 195608 kb
Host smart-e1fe4ee4-4130-4334-89ae-e1cbf280c1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055392629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.2055392629
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.2743939936
Short name T169
Test name
Test status
Simulation time 43725531 ps
CPU time 1.03 seconds
Started Jun 11 12:28:31 PM PDT 24
Finished Jun 11 12:28:33 PM PDT 24
Peak memory 196016 kb
Host smart-4ae37a1f-2876-4582-ba5f-123f80fb99c1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743939936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.2743939936
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.3744674098
Short name T147
Test name
Test status
Simulation time 610203301 ps
CPU time 4.04 seconds
Started Jun 11 12:28:42 PM PDT 24
Finished Jun 11 12:28:47 PM PDT 24
Peak memory 197900 kb
Host smart-a3899a8a-bc81-4f72-92f7-df6003b1a2a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744674098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.3744674098
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.430335972
Short name T579
Test name
Test status
Simulation time 128817043 ps
CPU time 0.8 seconds
Started Jun 11 12:28:24 PM PDT 24
Finished Jun 11 12:28:29 PM PDT 24
Peak memory 195744 kb
Host smart-c19e03f7-c8b8-474a-a871-313c83c584b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430335972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.430335972
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.3690051261
Short name T459
Test name
Test status
Simulation time 52559368 ps
CPU time 1.3 seconds
Started Jun 11 12:28:30 PM PDT 24
Finished Jun 11 12:28:33 PM PDT 24
Peak memory 197808 kb
Host smart-30600a70-9211-4525-886d-b8f95211c637
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690051261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.3690051261
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.3080814503
Short name T197
Test name
Test status
Simulation time 6457725917 ps
CPU time 166.97 seconds
Started Jun 11 12:28:30 PM PDT 24
Finished Jun 11 12:31:18 PM PDT 24
Peak memory 198056 kb
Host smart-e96c1d2f-e4ee-4669-a734-02849f4b2b13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080814503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.3080814503
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.1961281686
Short name T71
Test name
Test status
Simulation time 50608107 ps
CPU time 0.57 seconds
Started Jun 11 12:28:38 PM PDT 24
Finished Jun 11 12:28:40 PM PDT 24
Peak memory 194484 kb
Host smart-c91fdd27-803b-4b8c-ad64-fe6b7aa1e5ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961281686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.1961281686
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.2173068849
Short name T436
Test name
Test status
Simulation time 91379163 ps
CPU time 0.81 seconds
Started Jun 11 12:28:40 PM PDT 24
Finished Jun 11 12:28:43 PM PDT 24
Peak memory 195288 kb
Host smart-92d3618c-dffa-452e-a7df-549bb287bd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173068849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.2173068849
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.4201475448
Short name T498
Test name
Test status
Simulation time 401244262 ps
CPU time 9.8 seconds
Started Jun 11 12:28:34 PM PDT 24
Finished Jun 11 12:28:44 PM PDT 24
Peak memory 196744 kb
Host smart-5c641e2f-6fa5-4599-a7d9-4d0969984796
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201475448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.4201475448
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.3005683991
Short name T485
Test name
Test status
Simulation time 59096307 ps
CPU time 0.65 seconds
Started Jun 11 12:28:48 PM PDT 24
Finished Jun 11 12:28:51 PM PDT 24
Peak memory 194480 kb
Host smart-9ec4546f-12b7-4e5b-a9bf-74f09c4c0631
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005683991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.3005683991
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.1889608308
Short name T400
Test name
Test status
Simulation time 88619516 ps
CPU time 0.95 seconds
Started Jun 11 12:28:57 PM PDT 24
Finished Jun 11 12:29:00 PM PDT 24
Peak memory 195572 kb
Host smart-a7b29163-fe7a-4724-92fb-b005fe739232
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889608308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.1889608308
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.2969335531
Short name T666
Test name
Test status
Simulation time 157723299 ps
CPU time 3.02 seconds
Started Jun 11 12:28:54 PM PDT 24
Finished Jun 11 12:29:00 PM PDT 24
Peak memory 198044 kb
Host smart-d9d9f28c-d917-4ae4-83e9-95524a0af834
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969335531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.2969335531
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.3820107675
Short name T200
Test name
Test status
Simulation time 168910261 ps
CPU time 2.45 seconds
Started Jun 11 12:28:38 PM PDT 24
Finished Jun 11 12:28:42 PM PDT 24
Peak memory 197168 kb
Host smart-800358e2-7a83-401f-b91e-566b72022e73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820107675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.3820107675
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.2963966054
Short name T186
Test name
Test status
Simulation time 23489478 ps
CPU time 0.72 seconds
Started Jun 11 12:28:36 PM PDT 24
Finished Jun 11 12:28:38 PM PDT 24
Peak memory 195952 kb
Host smart-3c2e5ebc-6307-46ad-888c-6c1718cd7bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963966054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.2963966054
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.1675528125
Short name T358
Test name
Test status
Simulation time 173045355 ps
CPU time 1.07 seconds
Started Jun 11 12:28:48 PM PDT 24
Finished Jun 11 12:28:51 PM PDT 24
Peak memory 196104 kb
Host smart-247ac759-2516-4d0b-9fea-0d7cf3f0cd09
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675528125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.1675528125
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.428854629
Short name T632
Test name
Test status
Simulation time 75911772 ps
CPU time 1.47 seconds
Started Jun 11 12:29:00 PM PDT 24
Finished Jun 11 12:29:03 PM PDT 24
Peak memory 197864 kb
Host smart-fe687ef3-7d40-4d18-b181-74c13c66f830
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428854629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ran
dom_long_reg_writes_reg_reads.428854629
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.2589886912
Short name T284
Test name
Test status
Simulation time 762220702 ps
CPU time 1.1 seconds
Started Jun 11 12:28:39 PM PDT 24
Finished Jun 11 12:28:42 PM PDT 24
Peak memory 195492 kb
Host smart-8a48ac54-36a6-4e3e-815c-e469fa95bc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589886912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.2589886912
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.1596798023
Short name T559
Test name
Test status
Simulation time 114970506 ps
CPU time 0.93 seconds
Started Jun 11 12:28:37 PM PDT 24
Finished Jun 11 12:28:39 PM PDT 24
Peak memory 196140 kb
Host smart-1e7f174b-1887-40be-bc16-983e9e54514f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596798023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.1596798023
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.2997602977
Short name T490
Test name
Test status
Simulation time 20389429140 ps
CPU time 123.15 seconds
Started Jun 11 12:28:40 PM PDT 24
Finished Jun 11 12:30:45 PM PDT 24
Peak memory 198168 kb
Host smart-46160598-e303-4ee6-b28f-7077b15f99ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997602977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.2997602977
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.2860276227
Short name T263
Test name
Test status
Simulation time 65119710 ps
CPU time 0.57 seconds
Started Jun 11 12:27:24 PM PDT 24
Finished Jun 11 12:27:30 PM PDT 24
Peak memory 193948 kb
Host smart-899ea8da-56a2-494d-8448-1ce29375dcd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860276227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.2860276227
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.3493391002
Short name T316
Test name
Test status
Simulation time 148131022 ps
CPU time 0.78 seconds
Started Jun 11 12:27:22 PM PDT 24
Finished Jun 11 12:27:27 PM PDT 24
Peak memory 195360 kb
Host smart-e33e1bbc-03e7-4dab-a59f-6517f87a5c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493391002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.3493391002
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.1604880843
Short name T318
Test name
Test status
Simulation time 573651285 ps
CPU time 4.33 seconds
Started Jun 11 12:27:21 PM PDT 24
Finished Jun 11 12:27:30 PM PDT 24
Peak memory 196580 kb
Host smart-695961ed-35ce-4ca7-aa1e-c800b7f3c7ba
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604880843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.1604880843
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.242481778
Short name T427
Test name
Test status
Simulation time 60442879 ps
CPU time 0.64 seconds
Started Jun 11 12:27:20 PM PDT 24
Finished Jun 11 12:27:22 PM PDT 24
Peak memory 194492 kb
Host smart-b9b289f1-fc8b-4199-bc82-f1508fa201e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242481778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.242481778
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.2335228787
Short name T496
Test name
Test status
Simulation time 22164892 ps
CPU time 0.69 seconds
Started Jun 11 12:27:20 PM PDT 24
Finished Jun 11 12:27:22 PM PDT 24
Peak memory 194236 kb
Host smart-3a6ae33f-f7da-4f08-af12-928b83dd53b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335228787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.2335228787
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.3202575381
Short name T639
Test name
Test status
Simulation time 519154806 ps
CPU time 3.19 seconds
Started Jun 11 12:27:21 PM PDT 24
Finished Jun 11 12:27:26 PM PDT 24
Peak memory 197932 kb
Host smart-998569c6-f04e-4013-aca5-8b74acc529fb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202575381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.3202575381
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.3016721393
Short name T437
Test name
Test status
Simulation time 666366084 ps
CPU time 3.15 seconds
Started Jun 11 12:27:22 PM PDT 24
Finished Jun 11 12:27:29 PM PDT 24
Peak memory 196996 kb
Host smart-2ac0ef9f-4e49-4ad9-aba3-adf658254c7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016721393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
3016721393
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.935001574
Short name T416
Test name
Test status
Simulation time 132178519 ps
CPU time 1.19 seconds
Started Jun 11 12:27:10 PM PDT 24
Finished Jun 11 12:27:13 PM PDT 24
Peak memory 196888 kb
Host smart-9bc4911a-021c-478a-ac2c-696d44f25ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935001574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.935001574
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.4155865146
Short name T564
Test name
Test status
Simulation time 29129857 ps
CPU time 0.97 seconds
Started Jun 11 12:27:12 PM PDT 24
Finished Jun 11 12:27:16 PM PDT 24
Peak memory 195852 kb
Host smart-8d0fe2a3-16b3-4d9e-850a-d51921f5d6ed
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155865146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.4155865146
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.2765797149
Short name T547
Test name
Test status
Simulation time 32272211 ps
CPU time 1.34 seconds
Started Jun 11 12:27:22 PM PDT 24
Finished Jun 11 12:27:29 PM PDT 24
Peak memory 197824 kb
Host smart-347f7c01-ce55-4b16-96df-25a3f0df5ec5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765797149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.2765797149
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.2726009679
Short name T43
Test name
Test status
Simulation time 34833984 ps
CPU time 0.8 seconds
Started Jun 11 12:27:21 PM PDT 24
Finished Jun 11 12:27:24 PM PDT 24
Peak memory 213668 kb
Host smart-84fccbbd-6059-4954-b019-fec2ba3c265c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726009679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.2726009679
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.2444514259
Short name T139
Test name
Test status
Simulation time 150975111 ps
CPU time 0.96 seconds
Started Jun 11 12:27:11 PM PDT 24
Finished Jun 11 12:27:15 PM PDT 24
Peak memory 195664 kb
Host smart-1c6be414-6d32-4e0f-8c73-ad848c283f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444514259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.2444514259
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.2301157569
Short name T514
Test name
Test status
Simulation time 81214494 ps
CPU time 0.91 seconds
Started Jun 11 12:27:09 PM PDT 24
Finished Jun 11 12:27:11 PM PDT 24
Peak memory 195512 kb
Host smart-32a43c34-7581-4f80-aee3-b32bd4d9a397
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301157569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.2301157569
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.1035306633
Short name T683
Test name
Test status
Simulation time 19299963657 ps
CPU time 69.66 seconds
Started Jun 11 12:27:23 PM PDT 24
Finished Jun 11 12:28:38 PM PDT 24
Peak memory 198200 kb
Host smart-f958c651-8e95-4089-ac2a-4e9afcd28cc4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035306633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.1035306633
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.1797986107
Short name T65
Test name
Test status
Simulation time 78868780731 ps
CPU time 1049.81 seconds
Started Jun 11 12:27:20 PM PDT 24
Finished Jun 11 12:44:51 PM PDT 24
Peak memory 198172 kb
Host smart-bc8e3ff2-6050-4e5f-ad0f-86abeb3bbc40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1797986107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.1797986107
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.3265471576
Short name T673
Test name
Test status
Simulation time 10644328 ps
CPU time 0.57 seconds
Started Jun 11 12:28:41 PM PDT 24
Finished Jun 11 12:28:43 PM PDT 24
Peak memory 193772 kb
Host smart-348b5066-00fd-49f2-a18f-fe81e992efe8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265471576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.3265471576
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.2773286355
Short name T451
Test name
Test status
Simulation time 76070590 ps
CPU time 0.66 seconds
Started Jun 11 12:28:35 PM PDT 24
Finished Jun 11 12:28:36 PM PDT 24
Peak memory 194144 kb
Host smart-5535d80f-fe41-4d1c-8ad0-02fb859d935f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773286355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.2773286355
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.2136622703
Short name T106
Test name
Test status
Simulation time 512988699 ps
CPU time 9.34 seconds
Started Jun 11 12:28:45 PM PDT 24
Finished Jun 11 12:28:56 PM PDT 24
Peak memory 196800 kb
Host smart-38849d95-3352-4274-8d70-31362db55660
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136622703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.2136622703
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.2177829052
Short name T326
Test name
Test status
Simulation time 306244515 ps
CPU time 0.9 seconds
Started Jun 11 12:28:52 PM PDT 24
Finished Jun 11 12:28:55 PM PDT 24
Peak memory 196952 kb
Host smart-fa62e4cd-b42d-4e83-81bd-512f4906ce25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177829052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.2177829052
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.2631635445
Short name T267
Test name
Test status
Simulation time 129105031 ps
CPU time 1.03 seconds
Started Jun 11 12:28:49 PM PDT 24
Finished Jun 11 12:28:52 PM PDT 24
Peak memory 196684 kb
Host smart-57738ddb-352b-43d2-a187-7a298cdf60eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631635445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.2631635445
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.3416168054
Short name T471
Test name
Test status
Simulation time 60815974 ps
CPU time 2.37 seconds
Started Jun 11 12:28:48 PM PDT 24
Finished Jun 11 12:28:53 PM PDT 24
Peak memory 197936 kb
Host smart-88aecd16-6548-4bf6-881b-941f29ec6481
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416168054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.3416168054
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.2366594193
Short name T228
Test name
Test status
Simulation time 152746100 ps
CPU time 1.04 seconds
Started Jun 11 12:28:35 PM PDT 24
Finished Jun 11 12:28:37 PM PDT 24
Peak memory 195628 kb
Host smart-aea9e344-2faa-4fef-9129-a5a5b45212bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366594193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.2366594193
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.793086883
Short name T148
Test name
Test status
Simulation time 62359508 ps
CPU time 0.86 seconds
Started Jun 11 12:28:53 PM PDT 24
Finished Jun 11 12:28:56 PM PDT 24
Peak memory 197300 kb
Host smart-5470c9f9-16c2-4164-8b29-24a51052a43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793086883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.793086883
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.1438259369
Short name T128
Test name
Test status
Simulation time 44240375 ps
CPU time 0.9 seconds
Started Jun 11 12:28:45 PM PDT 24
Finished Jun 11 12:28:47 PM PDT 24
Peak memory 196464 kb
Host smart-9906c8d7-ec69-4efc-972b-a886cb8982e7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438259369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.1438259369
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.3736797226
Short name T570
Test name
Test status
Simulation time 400829544 ps
CPU time 5 seconds
Started Jun 11 12:28:30 PM PDT 24
Finished Jun 11 12:28:36 PM PDT 24
Peak memory 197908 kb
Host smart-f01fc43b-ec5f-451d-b75e-30ab9f0fbebb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736797226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.3736797226
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.3684315229
Short name T166
Test name
Test status
Simulation time 27154251 ps
CPU time 0.74 seconds
Started Jun 11 12:28:36 PM PDT 24
Finished Jun 11 12:28:39 PM PDT 24
Peak memory 195792 kb
Host smart-ed55179e-39b2-44a5-aeb2-898e960738c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684315229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.3684315229
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.2391956438
Short name T279
Test name
Test status
Simulation time 547002476 ps
CPU time 0.92 seconds
Started Jun 11 12:28:36 PM PDT 24
Finished Jun 11 12:28:38 PM PDT 24
Peak memory 196152 kb
Host smart-1ce16c6e-f010-4720-b4a4-1b00962bdf5e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391956438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.2391956438
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.666931160
Short name T154
Test name
Test status
Simulation time 15964747371 ps
CPU time 102.67 seconds
Started Jun 11 12:28:37 PM PDT 24
Finished Jun 11 12:30:22 PM PDT 24
Peak memory 197948 kb
Host smart-9685702a-c729-456b-8c9b-ba3355d2a105
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666931160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.g
pio_stress_all.666931160
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.1545217675
Short name T707
Test name
Test status
Simulation time 528956668561 ps
CPU time 1930.95 seconds
Started Jun 11 12:28:35 PM PDT 24
Finished Jun 11 01:00:48 PM PDT 24
Peak memory 198132 kb
Host smart-b3a3f3ea-75c3-4361-8721-140872f760e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1545217675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.1545217675
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.353273710
Short name T189
Test name
Test status
Simulation time 56332330 ps
CPU time 0.53 seconds
Started Jun 11 12:28:44 PM PDT 24
Finished Jun 11 12:28:46 PM PDT 24
Peak memory 193804 kb
Host smart-29e551f9-7e9a-4488-91ba-7b3c0bfd0878
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353273710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.353273710
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.969576029
Short name T453
Test name
Test status
Simulation time 218549995 ps
CPU time 0.84 seconds
Started Jun 11 12:28:34 PM PDT 24
Finished Jun 11 12:28:36 PM PDT 24
Peak memory 196108 kb
Host smart-ac0ff4a4-afec-400f-ae04-748bf4ed590e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969576029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.969576029
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.1688753099
Short name T382
Test name
Test status
Simulation time 679666170 ps
CPU time 8.85 seconds
Started Jun 11 12:28:40 PM PDT 24
Finished Jun 11 12:28:50 PM PDT 24
Peak memory 196784 kb
Host smart-6414a7d1-b7bd-48e5-ba0e-741acae81049
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688753099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.1688753099
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.2219040142
Short name T262
Test name
Test status
Simulation time 96476628 ps
CPU time 1.05 seconds
Started Jun 11 12:28:36 PM PDT 24
Finished Jun 11 12:28:38 PM PDT 24
Peak memory 197824 kb
Host smart-58782d20-abb4-4e9a-9c4f-3e4f4254a3ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219040142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.2219040142
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.3862427798
Short name T689
Test name
Test status
Simulation time 558570976 ps
CPU time 0.82 seconds
Started Jun 11 12:28:39 PM PDT 24
Finished Jun 11 12:28:41 PM PDT 24
Peak memory 195464 kb
Host smart-76f93fca-9c52-42b1-8b3d-18267bc50f71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862427798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.3862427798
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.373721470
Short name T532
Test name
Test status
Simulation time 139130513 ps
CPU time 1.58 seconds
Started Jun 11 12:28:39 PM PDT 24
Finished Jun 11 12:28:42 PM PDT 24
Peak memory 196420 kb
Host smart-24a06994-1aa6-4ec7-8a67-ef51f89c2a00
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373721470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.gpio_intr_with_filter_rand_intr_event.373721470
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.1679633477
Short name T618
Test name
Test status
Simulation time 110326708 ps
CPU time 1.14 seconds
Started Jun 11 12:28:50 PM PDT 24
Finished Jun 11 12:28:54 PM PDT 24
Peak memory 196864 kb
Host smart-6aef35b1-e1d4-4524-8f38-13605aa34805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679633477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.1679633477
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.710006979
Short name T418
Test name
Test status
Simulation time 52187791 ps
CPU time 1.02 seconds
Started Jun 11 12:28:36 PM PDT 24
Finished Jun 11 12:28:39 PM PDT 24
Peak memory 195864 kb
Host smart-fdb0fab8-e15c-4a27-b4d7-bc857f64f245
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710006979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullup
_pulldown.710006979
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.243486969
Short name T151
Test name
Test status
Simulation time 110510887 ps
CPU time 1.37 seconds
Started Jun 11 12:28:52 PM PDT 24
Finished Jun 11 12:28:56 PM PDT 24
Peak memory 197888 kb
Host smart-9571e0d5-6873-4092-9b71-6a809bd6fcf7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243486969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ran
dom_long_reg_writes_reg_reads.243486969
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.3625944359
Short name T292
Test name
Test status
Simulation time 36827330 ps
CPU time 1.06 seconds
Started Jun 11 12:28:38 PM PDT 24
Finished Jun 11 12:28:40 PM PDT 24
Peak memory 195612 kb
Host smart-01761547-4ce3-4775-9224-f6cc3c54154b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625944359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.3625944359
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.4184048761
Short name T595
Test name
Test status
Simulation time 153156941 ps
CPU time 0.94 seconds
Started Jun 11 12:28:48 PM PDT 24
Finished Jun 11 12:28:51 PM PDT 24
Peak memory 196324 kb
Host smart-781614b8-048b-4974-ae62-c0e88207580c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184048761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.4184048761
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.2987727040
Short name T700
Test name
Test status
Simulation time 7975277157 ps
CPU time 53.74 seconds
Started Jun 11 12:28:56 PM PDT 24
Finished Jun 11 12:29:52 PM PDT 24
Peak memory 198148 kb
Host smart-8ce2d9e9-67c7-4491-92ec-00895cb8340e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987727040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.2987727040
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.2562911301
Short name T175
Test name
Test status
Simulation time 201451671 ps
CPU time 0.55 seconds
Started Jun 11 12:28:38 PM PDT 24
Finished Jun 11 12:28:40 PM PDT 24
Peak memory 194724 kb
Host smart-25e8df2c-ba92-4615-a6e8-d87314519421
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562911301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.2562911301
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.3588734099
Short name T467
Test name
Test status
Simulation time 33408241 ps
CPU time 0.61 seconds
Started Jun 11 12:28:38 PM PDT 24
Finished Jun 11 12:28:40 PM PDT 24
Peak memory 193928 kb
Host smart-ef10b632-7e0e-4f82-8ea4-afe68eeaf8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588734099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.3588734099
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.3964152848
Short name T679
Test name
Test status
Simulation time 1731729369 ps
CPU time 15.67 seconds
Started Jun 11 12:28:35 PM PDT 24
Finished Jun 11 12:28:52 PM PDT 24
Peak memory 196592 kb
Host smart-1795e7a3-f786-42b4-ae1a-7aa7650043e0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964152848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.3964152848
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.1495685882
Short name T293
Test name
Test status
Simulation time 32231676 ps
CPU time 0.61 seconds
Started Jun 11 12:28:37 PM PDT 24
Finished Jun 11 12:28:39 PM PDT 24
Peak memory 194440 kb
Host smart-c8d1c82a-d3c7-48f7-bd86-ea0fa2700f61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495685882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.1495685882
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.1578150024
Short name T354
Test name
Test status
Simulation time 109441424 ps
CPU time 0.72 seconds
Started Jun 11 12:28:36 PM PDT 24
Finished Jun 11 12:28:38 PM PDT 24
Peak memory 195256 kb
Host smart-51b10a2a-63da-4065-8e7f-b6a0e683ed5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578150024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.1578150024
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.1399275782
Short name T518
Test name
Test status
Simulation time 81382534 ps
CPU time 3 seconds
Started Jun 11 12:28:49 PM PDT 24
Finished Jun 11 12:28:54 PM PDT 24
Peak memory 198028 kb
Host smart-eed3e9a7-4b7f-475d-b0f0-1e34a96382f5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399275782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.1399275782
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.3204931458
Short name T324
Test name
Test status
Simulation time 175375547 ps
CPU time 1.18 seconds
Started Jun 11 12:29:04 PM PDT 24
Finished Jun 11 12:29:07 PM PDT 24
Peak memory 195964 kb
Host smart-b51dfaec-df96-4dfb-85ca-99c4248d122a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204931458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.3204931458
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.3710193888
Short name T640
Test name
Test status
Simulation time 31297926 ps
CPU time 0.83 seconds
Started Jun 11 12:28:34 PM PDT 24
Finished Jun 11 12:28:36 PM PDT 24
Peak memory 197080 kb
Host smart-8b20d339-5de5-4a2f-a82f-7ede5e4ce388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710193888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.3710193888
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.1269829066
Short name T397
Test name
Test status
Simulation time 114804291 ps
CPU time 0.7 seconds
Started Jun 11 12:28:50 PM PDT 24
Finished Jun 11 12:28:53 PM PDT 24
Peak memory 195980 kb
Host smart-80d628c1-2669-4b58-ad55-ba3875608b7f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269829066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.1269829066
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.2601893638
Short name T227
Test name
Test status
Simulation time 130211638 ps
CPU time 2.85 seconds
Started Jun 11 12:28:40 PM PDT 24
Finished Jun 11 12:28:44 PM PDT 24
Peak memory 197816 kb
Host smart-e17f104d-0e7d-4bec-accb-8e286458dff9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601893638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.2601893638
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.2942605457
Short name T360
Test name
Test status
Simulation time 158623443 ps
CPU time 1.14 seconds
Started Jun 11 12:28:36 PM PDT 24
Finished Jun 11 12:28:39 PM PDT 24
Peak memory 196704 kb
Host smart-668a313f-3f82-424f-b548-789eede489ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942605457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.2942605457
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.2236324327
Short name T517
Test name
Test status
Simulation time 33642218 ps
CPU time 0.92 seconds
Started Jun 11 12:28:33 PM PDT 24
Finished Jun 11 12:28:35 PM PDT 24
Peak memory 195780 kb
Host smart-76d22b03-bb5d-4146-9350-33c20c06a11f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236324327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.2236324327
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.2344563636
Short name T562
Test name
Test status
Simulation time 5656309110 ps
CPU time 130.45 seconds
Started Jun 11 12:28:35 PM PDT 24
Finished Jun 11 12:30:46 PM PDT 24
Peak memory 198064 kb
Host smart-b9967dbc-f63c-4110-a186-2933653fb523
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344563636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.2344563636
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.2051537920
Short name T520
Test name
Test status
Simulation time 25335852 ps
CPU time 0.56 seconds
Started Jun 11 12:28:39 PM PDT 24
Finished Jun 11 12:28:41 PM PDT 24
Peak memory 193840 kb
Host smart-fd86cbd7-33c9-4c3d-a175-4078f250ac76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051537920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.2051537920
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.4248371770
Short name T158
Test name
Test status
Simulation time 112122310 ps
CPU time 0.72 seconds
Started Jun 11 12:28:38 PM PDT 24
Finished Jun 11 12:28:40 PM PDT 24
Peak memory 195988 kb
Host smart-cb287e94-9d52-4108-8e83-944746fe0c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248371770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.4248371770
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.2591178734
Short name T306
Test name
Test status
Simulation time 1720711559 ps
CPU time 13 seconds
Started Jun 11 12:28:33 PM PDT 24
Finished Jun 11 12:28:47 PM PDT 24
Peak memory 196780 kb
Host smart-2809271f-2e98-4e9b-aaa8-53ff1075f3f3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591178734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.2591178734
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.1944116617
Short name T483
Test name
Test status
Simulation time 49309189 ps
CPU time 0.72 seconds
Started Jun 11 12:28:38 PM PDT 24
Finished Jun 11 12:28:41 PM PDT 24
Peak memory 195840 kb
Host smart-376a7037-ecbe-418b-8cbb-825d21512a48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944116617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.1944116617
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.929813195
Short name T209
Test name
Test status
Simulation time 241528711 ps
CPU time 1.1 seconds
Started Jun 11 12:28:37 PM PDT 24
Finished Jun 11 12:28:40 PM PDT 24
Peak memory 196696 kb
Host smart-60f05df6-dc6e-464b-adbf-a7123474a68e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929813195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.929813195
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.1403696711
Short name T629
Test name
Test status
Simulation time 87290816 ps
CPU time 3.15 seconds
Started Jun 11 12:28:46 PM PDT 24
Finished Jun 11 12:28:51 PM PDT 24
Peak memory 197864 kb
Host smart-ba3b0a2a-8e4b-4135-8da9-861f83a941c9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403696711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.1403696711
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.3591082124
Short name T72
Test name
Test status
Simulation time 165487428 ps
CPU time 3.19 seconds
Started Jun 11 12:28:43 PM PDT 24
Finished Jun 11 12:28:47 PM PDT 24
Peak memory 197324 kb
Host smart-f4c11343-d47b-4556-bb9d-08b1666a7ce1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591082124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.3591082124
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.4211620349
Short name T30
Test name
Test status
Simulation time 47802871 ps
CPU time 0.68 seconds
Started Jun 11 12:28:41 PM PDT 24
Finished Jun 11 12:28:43 PM PDT 24
Peak memory 196080 kb
Host smart-96b57341-b49d-4240-86a0-a8e2578eddf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211620349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.4211620349
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.487085587
Short name T368
Test name
Test status
Simulation time 82458180 ps
CPU time 0.78 seconds
Started Jun 11 12:28:44 PM PDT 24
Finished Jun 11 12:28:45 PM PDT 24
Peak memory 196392 kb
Host smart-acc3bcdb-6dab-4c82-9323-58ed5a8bb8b2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487085587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullup
_pulldown.487085587
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.1371089465
Short name T646
Test name
Test status
Simulation time 1218947168 ps
CPU time 6.33 seconds
Started Jun 11 12:28:39 PM PDT 24
Finished Jun 11 12:28:47 PM PDT 24
Peak memory 197920 kb
Host smart-cb63deaf-1384-4df3-90ab-6a7fec51bf3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371089465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.1371089465
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.592165812
Short name T221
Test name
Test status
Simulation time 86888927 ps
CPU time 1.28 seconds
Started Jun 11 12:28:46 PM PDT 24
Finished Jun 11 12:28:49 PM PDT 24
Peak memory 196496 kb
Host smart-73d9cb3a-cbd0-438c-9aa5-27f3300d8bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592165812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.592165812
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.2030830665
Short name T443
Test name
Test status
Simulation time 517201751 ps
CPU time 1.4 seconds
Started Jun 11 12:28:36 PM PDT 24
Finished Jun 11 12:28:38 PM PDT 24
Peak memory 196572 kb
Host smart-e117b0fd-51f0-4daa-aac3-400ae877bbcf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030830665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.2030830665
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.1545004565
Short name T637
Test name
Test status
Simulation time 16093956730 ps
CPU time 50.22 seconds
Started Jun 11 12:28:37 PM PDT 24
Finished Jun 11 12:29:29 PM PDT 24
Peak memory 191824 kb
Host smart-d9268818-882a-4df5-832a-e0ae8f5f9db3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545004565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.1545004565
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.1290809151
Short name T287
Test name
Test status
Simulation time 49547492 ps
CPU time 0.59 seconds
Started Jun 11 12:28:40 PM PDT 24
Finished Jun 11 12:28:42 PM PDT 24
Peak memory 193992 kb
Host smart-2dd6625e-76ad-4227-a180-f057eac918e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290809151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.1290809151
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.2865645756
Short name T14
Test name
Test status
Simulation time 118441658 ps
CPU time 0.8 seconds
Started Jun 11 12:28:42 PM PDT 24
Finished Jun 11 12:28:44 PM PDT 24
Peak memory 195352 kb
Host smart-61b79a63-65dc-4d23-aa50-4d318e670e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865645756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.2865645756
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.2036801939
Short name T552
Test name
Test status
Simulation time 1349815274 ps
CPU time 19.32 seconds
Started Jun 11 12:28:38 PM PDT 24
Finished Jun 11 12:28:59 PM PDT 24
Peak memory 196936 kb
Host smart-52bdde4d-9ba6-4efd-b141-45b4dd4ccb44
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036801939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.2036801939
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.841918090
Short name T352
Test name
Test status
Simulation time 19696755 ps
CPU time 0.6 seconds
Started Jun 11 12:28:56 PM PDT 24
Finished Jun 11 12:28:59 PM PDT 24
Peak memory 195048 kb
Host smart-354323cd-6486-4b10-984e-268cf3af5d68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841918090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.841918090
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.858844783
Short name T606
Test name
Test status
Simulation time 81073378 ps
CPU time 1.13 seconds
Started Jun 11 12:28:51 PM PDT 24
Finished Jun 11 12:28:54 PM PDT 24
Peak memory 196552 kb
Host smart-68400631-8199-48ec-87f3-3a9631324e20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858844783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.858844783
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.1823738843
Short name T449
Test name
Test status
Simulation time 95296305 ps
CPU time 3.49 seconds
Started Jun 11 12:28:48 PM PDT 24
Finished Jun 11 12:28:54 PM PDT 24
Peak memory 197948 kb
Host smart-508def20-9e35-4bd9-af03-4723c7e254de
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823738843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.1823738843
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.220168131
Short name T542
Test name
Test status
Simulation time 84725929 ps
CPU time 2.35 seconds
Started Jun 11 12:28:51 PM PDT 24
Finished Jun 11 12:28:55 PM PDT 24
Peak memory 196868 kb
Host smart-12886b4a-68d3-4ff2-8443-97c033a91d92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220168131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger.
220168131
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.1939161295
Short name T105
Test name
Test status
Simulation time 71862638 ps
CPU time 1.37 seconds
Started Jun 11 12:28:43 PM PDT 24
Finished Jun 11 12:28:45 PM PDT 24
Peak memory 198284 kb
Host smart-0cfd776f-7ef1-432b-99c1-67ad96508ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939161295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.1939161295
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.815121939
Short name T270
Test name
Test status
Simulation time 246033742 ps
CPU time 1.28 seconds
Started Jun 11 12:28:39 PM PDT 24
Finished Jun 11 12:28:42 PM PDT 24
Peak memory 197956 kb
Host smart-502f0556-2463-463f-ad01-da9d75e56be8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815121939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullup
_pulldown.815121939
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.3944240863
Short name T176
Test name
Test status
Simulation time 497220569 ps
CPU time 5.46 seconds
Started Jun 11 12:28:39 PM PDT 24
Finished Jun 11 12:28:47 PM PDT 24
Peak memory 197764 kb
Host smart-35698aae-d3a9-4bc4-a245-ad364fe39ae9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944240863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.3944240863
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.1785998063
Short name T329
Test name
Test status
Simulation time 74606386 ps
CPU time 1.2 seconds
Started Jun 11 12:28:38 PM PDT 24
Finished Jun 11 12:28:41 PM PDT 24
Peak memory 195720 kb
Host smart-afa7a0e2-2692-4521-81bd-d815ea114ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785998063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.1785998063
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.1054026796
Short name T477
Test name
Test status
Simulation time 491820853 ps
CPU time 1.34 seconds
Started Jun 11 12:28:33 PM PDT 24
Finished Jun 11 12:28:35 PM PDT 24
Peak memory 196616 kb
Host smart-e6c01811-0d80-4dde-8d6e-a68636c05f1c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054026796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.1054026796
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.955247677
Short name T442
Test name
Test status
Simulation time 29658512898 ps
CPU time 215.63 seconds
Started Jun 11 12:28:37 PM PDT 24
Finished Jun 11 12:32:14 PM PDT 24
Peak memory 198036 kb
Host smart-61dcd018-6b8d-4c29-bf77-c2b028dcea69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955247677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.g
pio_stress_all.955247677
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.4212525847
Short name T351
Test name
Test status
Simulation time 44589222 ps
CPU time 0.56 seconds
Started Jun 11 12:28:42 PM PDT 24
Finished Jun 11 12:28:43 PM PDT 24
Peak memory 194552 kb
Host smart-034f0e35-73a2-4455-b9e4-a1d501921749
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212525847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.4212525847
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.3115271132
Short name T247
Test name
Test status
Simulation time 91688985 ps
CPU time 0.9 seconds
Started Jun 11 12:28:38 PM PDT 24
Finished Jun 11 12:28:40 PM PDT 24
Peak memory 196552 kb
Host smart-402653b7-708b-465d-9344-f5edf82fb43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115271132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.3115271132
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.2123903250
Short name T196
Test name
Test status
Simulation time 1280989237 ps
CPU time 21.72 seconds
Started Jun 11 12:28:47 PM PDT 24
Finished Jun 11 12:29:10 PM PDT 24
Peak memory 196584 kb
Host smart-cf0d87f4-44ba-4dcd-bb2d-cb33d66f2b41
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123903250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.2123903250
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.3339468771
Short name T392
Test name
Test status
Simulation time 91633956 ps
CPU time 1.1 seconds
Started Jun 11 12:28:47 PM PDT 24
Finished Jun 11 12:28:50 PM PDT 24
Peak memory 197824 kb
Host smart-1252495c-2965-4336-8730-b7fe1f41bcf9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339468771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.3339468771
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.1384942
Short name T157
Test name
Test status
Simulation time 203375410 ps
CPU time 1.01 seconds
Started Jun 11 12:28:38 PM PDT 24
Finished Jun 11 12:28:41 PM PDT 24
Peak memory 196632 kb
Host smart-9500bd1b-940f-456e-ac6c-b675039d1ac8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.1384942
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.2247075168
Short name T581
Test name
Test status
Simulation time 85607230 ps
CPU time 3.18 seconds
Started Jun 11 12:28:50 PM PDT 24
Finished Jun 11 12:28:55 PM PDT 24
Peak memory 197948 kb
Host smart-c34d45d9-bfa7-4afa-b086-f6bf046af483
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247075168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.2247075168
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.3387501110
Short name T370
Test name
Test status
Simulation time 87899872 ps
CPU time 0.82 seconds
Started Jun 11 12:28:40 PM PDT 24
Finished Jun 11 12:28:42 PM PDT 24
Peak memory 195052 kb
Host smart-0d95c949-e494-4b08-8629-92ef9b4bb78a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387501110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.3387501110
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.1404681809
Short name T470
Test name
Test status
Simulation time 92189232 ps
CPU time 0.71 seconds
Started Jun 11 12:28:36 PM PDT 24
Finished Jun 11 12:28:38 PM PDT 24
Peak memory 195152 kb
Host smart-9e9eecaa-3ebd-49a9-8978-2bea0d39c298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404681809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.1404681809
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.2880580128
Short name T381
Test name
Test status
Simulation time 58635204 ps
CPU time 1.26 seconds
Started Jun 11 12:28:42 PM PDT 24
Finished Jun 11 12:28:45 PM PDT 24
Peak memory 195708 kb
Host smart-ff19a70b-73e8-4bf9-8811-b0081dd63306
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880580128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.2880580128
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.3645727085
Short name T138
Test name
Test status
Simulation time 126982408 ps
CPU time 2.85 seconds
Started Jun 11 12:28:39 PM PDT 24
Finished Jun 11 12:28:44 PM PDT 24
Peak memory 197792 kb
Host smart-75c3c32f-2b9f-4574-ba40-73c6deebb2c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645727085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.3645727085
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.1320195447
Short name T515
Test name
Test status
Simulation time 230112724 ps
CPU time 1.06 seconds
Started Jun 11 12:28:49 PM PDT 24
Finished Jun 11 12:28:52 PM PDT 24
Peak memory 195604 kb
Host smart-07d83faa-ad29-4c07-917a-49c38a697222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320195447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.1320195447
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.4223556051
Short name T170
Test name
Test status
Simulation time 76359543 ps
CPU time 1.11 seconds
Started Jun 11 12:28:46 PM PDT 24
Finished Jun 11 12:28:49 PM PDT 24
Peak memory 196156 kb
Host smart-1613925b-21fd-463c-b5b4-b00c2c9e6a98
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223556051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.4223556051
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.132209141
Short name T155
Test name
Test status
Simulation time 6500804059 ps
CPU time 153.28 seconds
Started Jun 11 12:28:50 PM PDT 24
Finished Jun 11 12:31:26 PM PDT 24
Peak memory 198108 kb
Host smart-bc627bf4-9ae8-4bbd-8e4e-4e9776b05167
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132209141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.g
pio_stress_all.132209141
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.2502989830
Short name T177
Test name
Test status
Simulation time 10975287 ps
CPU time 0.56 seconds
Started Jun 11 12:28:46 PM PDT 24
Finished Jun 11 12:28:48 PM PDT 24
Peak memory 193808 kb
Host smart-2534d0d8-17ff-444b-a8de-671e8e66ce24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502989830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.2502989830
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.425481379
Short name T544
Test name
Test status
Simulation time 48864261 ps
CPU time 0.8 seconds
Started Jun 11 12:28:37 PM PDT 24
Finished Jun 11 12:28:40 PM PDT 24
Peak memory 195384 kb
Host smart-b17085ba-467d-43aa-83f0-365c42095994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425481379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.425481379
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.1405554366
Short name T187
Test name
Test status
Simulation time 2688194639 ps
CPU time 8.23 seconds
Started Jun 11 12:28:37 PM PDT 24
Finished Jun 11 12:28:46 PM PDT 24
Peak memory 198000 kb
Host smart-e41484f1-3051-4064-9d93-89a3c14d9681
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405554366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.1405554366
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.2440131266
Short name T704
Test name
Test status
Simulation time 78431540 ps
CPU time 0.92 seconds
Started Jun 11 12:28:35 PM PDT 24
Finished Jun 11 12:28:37 PM PDT 24
Peak memory 196432 kb
Host smart-9acf784f-6794-4a17-aa7d-e68f8a0c8fff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440131266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.2440131266
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.3972079131
Short name T135
Test name
Test status
Simulation time 32550906 ps
CPU time 0.72 seconds
Started Jun 11 12:28:39 PM PDT 24
Finished Jun 11 12:28:41 PM PDT 24
Peak memory 195460 kb
Host smart-809d70d0-811c-4cb4-b1da-cf30f7d371da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972079131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.3972079131
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.4934951
Short name T114
Test name
Test status
Simulation time 200278989 ps
CPU time 2.14 seconds
Started Jun 11 12:28:40 PM PDT 24
Finished Jun 11 12:28:44 PM PDT 24
Peak memory 197916 kb
Host smart-0224115b-d99b-44f8-b6af-c93ab5fc8e76
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4934951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.gpio_intr_with_filter_rand_intr_event.4934951
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.587157849
Short name T361
Test name
Test status
Simulation time 587015666 ps
CPU time 1.22 seconds
Started Jun 11 12:28:46 PM PDT 24
Finished Jun 11 12:28:50 PM PDT 24
Peak memory 196732 kb
Host smart-57e4e42f-693a-4a6f-8c36-4c00d58004c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587157849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger.
587157849
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.1368432804
Short name T234
Test name
Test status
Simulation time 110061133 ps
CPU time 0.82 seconds
Started Jun 11 12:28:39 PM PDT 24
Finished Jun 11 12:28:42 PM PDT 24
Peak memory 197012 kb
Host smart-4b14d736-b413-4978-8913-686989e4eb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368432804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.1368432804
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.4091765714
Short name T302
Test name
Test status
Simulation time 124090161 ps
CPU time 1.18 seconds
Started Jun 11 12:28:44 PM PDT 24
Finished Jun 11 12:28:47 PM PDT 24
Peak memory 196912 kb
Host smart-dd8d74d7-7ba7-4b94-ad1a-eb2f3b9e2081
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091765714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.4091765714
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.730212500
Short name T600
Test name
Test status
Simulation time 4172859583 ps
CPU time 3.64 seconds
Started Jun 11 12:28:46 PM PDT 24
Finished Jun 11 12:28:52 PM PDT 24
Peak memory 198064 kb
Host smart-66678d4f-0cde-4cf7-821b-5e1ebd76cd3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730212500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ran
dom_long_reg_writes_reg_reads.730212500
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.867746106
Short name T283
Test name
Test status
Simulation time 228255375 ps
CPU time 1.04 seconds
Started Jun 11 12:28:39 PM PDT 24
Finished Jun 11 12:28:42 PM PDT 24
Peak memory 195544 kb
Host smart-cd23ca03-d117-4773-b287-2d1357ec5c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867746106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.867746106
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.3913925388
Short name T25
Test name
Test status
Simulation time 106883451 ps
CPU time 1.1 seconds
Started Jun 11 12:28:39 PM PDT 24
Finished Jun 11 12:28:42 PM PDT 24
Peak memory 196440 kb
Host smart-22eb824c-4ca2-427d-9a4d-cb63970ecf54
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913925388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.3913925388
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.2355288134
Short name T540
Test name
Test status
Simulation time 3381161359 ps
CPU time 42.93 seconds
Started Jun 11 12:28:38 PM PDT 24
Finished Jun 11 12:29:22 PM PDT 24
Peak memory 198148 kb
Host smart-89f18b76-186e-4723-a28f-b4f5e896a2a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355288134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.2355288134
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.343783861
Short name T665
Test name
Test status
Simulation time 17233828 ps
CPU time 0.57 seconds
Started Jun 11 12:29:10 PM PDT 24
Finished Jun 11 12:29:12 PM PDT 24
Peak memory 193992 kb
Host smart-870eaef9-196c-4cdf-86e6-da7a8f793601
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343783861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.343783861
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.2798975876
Short name T317
Test name
Test status
Simulation time 543255893 ps
CPU time 0.74 seconds
Started Jun 11 12:28:45 PM PDT 24
Finished Jun 11 12:28:47 PM PDT 24
Peak memory 195148 kb
Host smart-f8fc2e16-0df6-44f2-8b79-47e9e49f6cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798975876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.2798975876
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.3743787292
Short name T644
Test name
Test status
Simulation time 471335368 ps
CPU time 16.18 seconds
Started Jun 11 12:28:47 PM PDT 24
Finished Jun 11 12:29:05 PM PDT 24
Peak memory 197952 kb
Host smart-62b4857e-3343-4026-88cd-4eb8bfe2762b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743787292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.3743787292
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.1261264511
Short name T16
Test name
Test status
Simulation time 58175253 ps
CPU time 0.93 seconds
Started Jun 11 12:29:00 PM PDT 24
Finished Jun 11 12:29:02 PM PDT 24
Peak memory 196564 kb
Host smart-6018b316-b5d1-47c1-a8d2-a49de2a5074b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261264511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.1261264511
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.951187784
Short name T602
Test name
Test status
Simulation time 175476159 ps
CPU time 0.95 seconds
Started Jun 11 12:28:58 PM PDT 24
Finished Jun 11 12:29:00 PM PDT 24
Peak memory 195964 kb
Host smart-729a5ed3-3a56-4006-bc84-3e62007fb4a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951187784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.951187784
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.1120053650
Short name T341
Test name
Test status
Simulation time 30406099 ps
CPU time 1.01 seconds
Started Jun 11 12:28:51 PM PDT 24
Finished Jun 11 12:28:54 PM PDT 24
Peak memory 196284 kb
Host smart-445a9d4b-3340-44d3-9462-df09c9978a1e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120053650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.1120053650
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.1263817636
Short name T676
Test name
Test status
Simulation time 115863755 ps
CPU time 1.85 seconds
Started Jun 11 12:28:59 PM PDT 24
Finished Jun 11 12:29:02 PM PDT 24
Peak memory 196976 kb
Host smart-eb2e7de5-ecba-46a5-891c-0d2539c705ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263817636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.1263817636
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.3393280878
Short name T675
Test name
Test status
Simulation time 176573867 ps
CPU time 1.12 seconds
Started Jun 11 12:28:48 PM PDT 24
Finished Jun 11 12:28:51 PM PDT 24
Peak memory 195772 kb
Host smart-9604518e-2685-4f62-96ca-227c62db3b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393280878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.3393280878
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.3047121672
Short name T623
Test name
Test status
Simulation time 54606315 ps
CPU time 1.13 seconds
Started Jun 11 12:28:54 PM PDT 24
Finished Jun 11 12:28:57 PM PDT 24
Peak memory 197232 kb
Host smart-58f67523-d364-4175-8ccb-55f2a108eb59
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047121672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.3047121672
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.1489135940
Short name T530
Test name
Test status
Simulation time 82630021 ps
CPU time 1.59 seconds
Started Jun 11 12:29:00 PM PDT 24
Finished Jun 11 12:29:04 PM PDT 24
Peak memory 197772 kb
Host smart-84c15902-71fd-40aa-a73e-a0382f27c9c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489135940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.1489135940
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.66241144
Short name T687
Test name
Test status
Simulation time 468806074 ps
CPU time 1.35 seconds
Started Jun 11 12:29:02 PM PDT 24
Finished Jun 11 12:29:05 PM PDT 24
Peak memory 197916 kb
Host smart-124dca3c-7b99-4b03-b53a-2c2607b23482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66241144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.66241144
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.228957648
Short name T144
Test name
Test status
Simulation time 51725758 ps
CPU time 1.1 seconds
Started Jun 11 12:28:47 PM PDT 24
Finished Jun 11 12:28:50 PM PDT 24
Peak memory 195760 kb
Host smart-dd7f8a36-d856-4796-9fb4-19ae656c7db6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228957648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.228957648
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.2189408664
Short name T275
Test name
Test status
Simulation time 15870018698 ps
CPU time 79.65 seconds
Started Jun 11 12:28:56 PM PDT 24
Finished Jun 11 12:30:17 PM PDT 24
Peak memory 198148 kb
Host smart-ecae26ca-3a8a-4f6b-9aec-fc6ad5f3d7d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189408664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.2189408664
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.2722066569
Short name T222
Test name
Test status
Simulation time 174813862 ps
CPU time 0.57 seconds
Started Jun 11 12:29:01 PM PDT 24
Finished Jun 11 12:29:04 PM PDT 24
Peak memory 194396 kb
Host smart-16ec2806-f7d7-45c1-8f8c-0f35fac98bd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722066569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.2722066569
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.2092665142
Short name T419
Test name
Test status
Simulation time 37751603 ps
CPU time 0.72 seconds
Started Jun 11 12:29:02 PM PDT 24
Finished Jun 11 12:29:05 PM PDT 24
Peak memory 195364 kb
Host smart-e25db578-cbd3-48e3-83ae-30e047735e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092665142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.2092665142
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.4152713295
Short name T245
Test name
Test status
Simulation time 318860118 ps
CPU time 6.67 seconds
Started Jun 11 12:28:58 PM PDT 24
Finished Jun 11 12:29:06 PM PDT 24
Peak memory 197940 kb
Host smart-75d919bb-b9a9-4bad-af74-57ece5359512
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152713295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.4152713295
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.1714526291
Short name T635
Test name
Test status
Simulation time 120562151 ps
CPU time 0.67 seconds
Started Jun 11 12:29:03 PM PDT 24
Finished Jun 11 12:29:06 PM PDT 24
Peak memory 195228 kb
Host smart-c680f33b-1204-4b8c-956d-fa49bd4f054c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714526291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.1714526291
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.3440512071
Short name T123
Test name
Test status
Simulation time 335749974 ps
CPU time 1.24 seconds
Started Jun 11 12:28:58 PM PDT 24
Finished Jun 11 12:29:01 PM PDT 24
Peak memory 195868 kb
Host smart-1e0accfc-c1b8-4c5a-a881-42357e935dec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440512071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.3440512071
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.3000253020
Short name T340
Test name
Test status
Simulation time 47936149 ps
CPU time 1.91 seconds
Started Jun 11 12:28:55 PM PDT 24
Finished Jun 11 12:28:59 PM PDT 24
Peak memory 198240 kb
Host smart-04bb0b06-2440-40d1-b1aa-23ffd99a61e5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000253020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.3000253020
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.2839673077
Short name T512
Test name
Test status
Simulation time 357298116 ps
CPU time 1.07 seconds
Started Jun 11 12:28:46 PM PDT 24
Finished Jun 11 12:28:50 PM PDT 24
Peak memory 196844 kb
Host smart-3c033177-7238-47d1-acbe-8f620bc208c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839673077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.2839673077
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.2637467080
Short name T289
Test name
Test status
Simulation time 38017726 ps
CPU time 0.89 seconds
Started Jun 11 12:28:59 PM PDT 24
Finished Jun 11 12:29:01 PM PDT 24
Peak memory 195896 kb
Host smart-9cbdf697-df31-4ddb-9d83-842eddfad4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637467080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.2637467080
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.398126890
Short name T323
Test name
Test status
Simulation time 123753724 ps
CPU time 0.85 seconds
Started Jun 11 12:29:02 PM PDT 24
Finished Jun 11 12:29:05 PM PDT 24
Peak memory 195784 kb
Host smart-234946ee-bbb6-481f-955a-bc21dd2cc5d1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398126890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullup
_pulldown.398126890
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.709364361
Short name T348
Test name
Test status
Simulation time 98348503 ps
CPU time 4.44 seconds
Started Jun 11 12:28:47 PM PDT 24
Finished Jun 11 12:28:53 PM PDT 24
Peak memory 197916 kb
Host smart-5099740d-d831-40be-96d3-c94db5b746e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709364361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ran
dom_long_reg_writes_reg_reads.709364361
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.508039449
Short name T320
Test name
Test status
Simulation time 155193992 ps
CPU time 1.07 seconds
Started Jun 11 12:28:57 PM PDT 24
Finished Jun 11 12:28:59 PM PDT 24
Peak memory 196260 kb
Host smart-d3d56729-fb58-4533-bd83-d57482cd8539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508039449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.508039449
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.3569975661
Short name T636
Test name
Test status
Simulation time 67597901 ps
CPU time 1.27 seconds
Started Jun 11 12:29:00 PM PDT 24
Finished Jun 11 12:29:02 PM PDT 24
Peak memory 197924 kb
Host smart-6cf99af1-122e-436a-a877-7be92c64d685
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569975661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.3569975661
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.1361308953
Short name T440
Test name
Test status
Simulation time 15106591860 ps
CPU time 88.35 seconds
Started Jun 11 12:28:59 PM PDT 24
Finished Jun 11 12:30:29 PM PDT 24
Peak memory 198096 kb
Host smart-64f9173b-5a74-47a4-9497-aa40f58cc9cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361308953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.1361308953
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.446463234
Short name T60
Test name
Test status
Simulation time 149694179644 ps
CPU time 1855.24 seconds
Started Jun 11 12:28:51 PM PDT 24
Finished Jun 11 12:59:49 PM PDT 24
Peak memory 198128 kb
Host smart-ef4bd5b5-a725-488e-b5a0-dd11003ed8d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=446463234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.446463234
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.3748733807
Short name T191
Test name
Test status
Simulation time 18052783 ps
CPU time 0.57 seconds
Started Jun 11 12:28:49 PM PDT 24
Finished Jun 11 12:28:52 PM PDT 24
Peak memory 194512 kb
Host smart-858284ac-8a5d-4624-83b6-b975f046d393
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748733807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.3748733807
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.2408750516
Short name T702
Test name
Test status
Simulation time 219188269 ps
CPU time 0.64 seconds
Started Jun 11 12:29:00 PM PDT 24
Finished Jun 11 12:29:02 PM PDT 24
Peak memory 194064 kb
Host smart-dbbec76d-da4b-4856-9c81-071c5b2688c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408750516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.2408750516
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.166856345
Short name T433
Test name
Test status
Simulation time 1031617207 ps
CPU time 18.43 seconds
Started Jun 11 12:29:08 PM PDT 24
Finished Jun 11 12:29:28 PM PDT 24
Peak memory 196684 kb
Host smart-e991f036-a593-40a3-99a0-ddb06388ad89
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166856345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stres
s.166856345
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.4249128066
Short name T591
Test name
Test status
Simulation time 30322992 ps
CPU time 0.68 seconds
Started Jun 11 12:29:02 PM PDT 24
Finished Jun 11 12:29:05 PM PDT 24
Peak memory 194664 kb
Host smart-d1526e5c-0dba-4102-94b2-eaf0c4037061
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249128066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.4249128066
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.3789539288
Short name T615
Test name
Test status
Simulation time 43604826 ps
CPU time 1.13 seconds
Started Jun 11 12:28:45 PM PDT 24
Finished Jun 11 12:28:48 PM PDT 24
Peak memory 196708 kb
Host smart-e33ce67d-f96e-47f3-bacd-2c3a4ce7f36a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789539288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.3789539288
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.4186159790
Short name T184
Test name
Test status
Simulation time 49441110 ps
CPU time 1.91 seconds
Started Jun 11 12:28:58 PM PDT 24
Finished Jun 11 12:29:01 PM PDT 24
Peak memory 197948 kb
Host smart-132efff7-dbc6-4764-84d4-2f0a3e387390
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186159790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.4186159790
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.4127787633
Short name T250
Test name
Test status
Simulation time 329207287 ps
CPU time 2.7 seconds
Started Jun 11 12:28:57 PM PDT 24
Finished Jun 11 12:29:01 PM PDT 24
Peak memory 197984 kb
Host smart-02dba94f-5621-49fb-9707-dc0680d0f386
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127787633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.4127787633
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.2604062857
Short name T481
Test name
Test status
Simulation time 149232563 ps
CPU time 1.24 seconds
Started Jun 11 12:29:00 PM PDT 24
Finished Jun 11 12:29:03 PM PDT 24
Peak memory 195688 kb
Host smart-1b5279a1-c82e-46d9-9a7e-619b12669f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604062857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.2604062857
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.2195649988
Short name T328
Test name
Test status
Simulation time 35881919 ps
CPU time 1.24 seconds
Started Jun 11 12:28:48 PM PDT 24
Finished Jun 11 12:28:52 PM PDT 24
Peak memory 197884 kb
Host smart-76969217-43b4-4893-8480-37773c69f5fd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195649988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.2195649988
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.1374769406
Short name T349
Test name
Test status
Simulation time 55257043 ps
CPU time 2.23 seconds
Started Jun 11 12:28:51 PM PDT 24
Finished Jun 11 12:28:55 PM PDT 24
Peak memory 197896 kb
Host smart-bc44cd2c-fdac-464c-befa-acaac7434e29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374769406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.1374769406
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.2567807566
Short name T551
Test name
Test status
Simulation time 172083106 ps
CPU time 1.28 seconds
Started Jun 11 12:28:49 PM PDT 24
Finished Jun 11 12:28:52 PM PDT 24
Peak memory 197900 kb
Host smart-0ac82dbd-9409-44bb-b83d-c16fa741e26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567807566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.2567807566
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.1914300991
Short name T430
Test name
Test status
Simulation time 121548099 ps
CPU time 0.85 seconds
Started Jun 11 12:28:55 PM PDT 24
Finished Jun 11 12:28:58 PM PDT 24
Peak memory 195448 kb
Host smart-ed081914-a854-4c6a-bc76-05d5ad3dcd4d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914300991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.1914300991
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.1558206030
Short name T11
Test name
Test status
Simulation time 6159241324 ps
CPU time 90.75 seconds
Started Jun 11 12:28:47 PM PDT 24
Finished Jun 11 12:30:19 PM PDT 24
Peak memory 198088 kb
Host smart-cf6d5238-7b22-4398-b23d-e3f5b90ac478
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558206030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.1558206030
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.905379759
Short name T61
Test name
Test status
Simulation time 16196573302 ps
CPU time 497.9 seconds
Started Jun 11 12:28:56 PM PDT 24
Finished Jun 11 12:37:16 PM PDT 24
Peak memory 198052 kb
Host smart-74b36bc7-7fd9-4717-89fa-a499e0a84d40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=905379759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.905379759
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.2137787347
Short name T622
Test name
Test status
Simulation time 23775160 ps
CPU time 0.58 seconds
Started Jun 11 12:27:22 PM PDT 24
Finished Jun 11 12:27:27 PM PDT 24
Peak memory 194000 kb
Host smart-dec95e85-15f0-41ac-b154-dcd47d7c1a48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137787347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.2137787347
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.1914850574
Short name T434
Test name
Test status
Simulation time 82248237 ps
CPU time 0.75 seconds
Started Jun 11 12:27:21 PM PDT 24
Finished Jun 11 12:27:26 PM PDT 24
Peak memory 195908 kb
Host smart-b5842256-9ce7-418b-bc00-37fd911b8621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914850574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.1914850574
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.35304078
Short name T395
Test name
Test status
Simulation time 2369346308 ps
CPU time 8.74 seconds
Started Jun 11 12:27:24 PM PDT 24
Finished Jun 11 12:27:38 PM PDT 24
Peak memory 197044 kb
Host smart-bdbe95f7-526d-4e47-b879-f151caa6577c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35304078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stress.35304078
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.248555536
Short name T692
Test name
Test status
Simulation time 80441908 ps
CPU time 0.81 seconds
Started Jun 11 12:27:28 PM PDT 24
Finished Jun 11 12:27:34 PM PDT 24
Peak memory 196824 kb
Host smart-b672463c-130e-42a3-82df-fe2aa57d4d34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248555536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.248555536
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.2383533198
Short name T484
Test name
Test status
Simulation time 31564192 ps
CPU time 0.94 seconds
Started Jun 11 12:27:20 PM PDT 24
Finished Jun 11 12:27:22 PM PDT 24
Peak memory 195748 kb
Host smart-5ae082cb-bb3d-475e-9c53-479d1f0de355
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383533198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.2383533198
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.2961295454
Short name T523
Test name
Test status
Simulation time 87651416 ps
CPU time 3.13 seconds
Started Jun 11 12:27:25 PM PDT 24
Finished Jun 11 12:27:34 PM PDT 24
Peak memory 197984 kb
Host smart-2187dd0f-314f-4f14-9c62-0d16f487c0f5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961295454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.2961295454
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.2112415270
Short name T426
Test name
Test status
Simulation time 29822891 ps
CPU time 1.08 seconds
Started Jun 11 12:27:24 PM PDT 24
Finished Jun 11 12:27:31 PM PDT 24
Peak memory 195768 kb
Host smart-816737f3-9f3b-4a97-b4b2-75a45bf22f72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112415270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
2112415270
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.3248272229
Short name T350
Test name
Test status
Simulation time 37189409 ps
CPU time 1.25 seconds
Started Jun 11 12:27:20 PM PDT 24
Finished Jun 11 12:27:23 PM PDT 24
Peak memory 195792 kb
Host smart-12aa4a31-c7fa-4318-8f5b-9f56a5ce48ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248272229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.3248272229
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.3523518329
Short name T685
Test name
Test status
Simulation time 85722340 ps
CPU time 0.94 seconds
Started Jun 11 12:27:23 PM PDT 24
Finished Jun 11 12:27:29 PM PDT 24
Peak memory 195916 kb
Host smart-e14634cc-df09-4b9c-b88d-909b44f94bf2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523518329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.3523518329
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.801182346
Short name T402
Test name
Test status
Simulation time 964229647 ps
CPU time 5.55 seconds
Started Jun 11 12:27:21 PM PDT 24
Finished Jun 11 12:27:31 PM PDT 24
Peak memory 197900 kb
Host smart-090e688b-55cd-463a-8fe6-37793b961244
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801182346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand
om_long_reg_writes_reg_reads.801182346
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.857825030
Short name T650
Test name
Test status
Simulation time 100347279 ps
CPU time 0.75 seconds
Started Jun 11 12:27:21 PM PDT 24
Finished Jun 11 12:27:25 PM PDT 24
Peak memory 195800 kb
Host smart-649ac461-ee09-40f2-a6a7-0c647f7f2acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857825030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.857825030
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.2079943428
Short name T596
Test name
Test status
Simulation time 692863017 ps
CPU time 1.28 seconds
Started Jun 11 12:27:23 PM PDT 24
Finished Jun 11 12:27:29 PM PDT 24
Peak memory 196636 kb
Host smart-afcd3bcc-de72-46a7-8694-0d9c8c10fde8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079943428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.2079943428
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.2595558700
Short name T32
Test name
Test status
Simulation time 12717835213 ps
CPU time 159.51 seconds
Started Jun 11 12:27:24 PM PDT 24
Finished Jun 11 12:30:09 PM PDT 24
Peak memory 198100 kb
Host smart-821dc00f-11d6-46b2-9194-fabf5d4ca8ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595558700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.2595558700
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.3004435905
Short name T63
Test name
Test status
Simulation time 499137880859 ps
CPU time 1093.75 seconds
Started Jun 11 12:27:22 PM PDT 24
Finished Jun 11 12:45:41 PM PDT 24
Peak memory 198164 kb
Host smart-fe48d1a2-ae7a-4ac8-b867-f2062857b619
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3004435905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.3004435905
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.79317774
Short name T647
Test name
Test status
Simulation time 15941393 ps
CPU time 0.57 seconds
Started Jun 11 12:27:21 PM PDT 24
Finished Jun 11 12:27:24 PM PDT 24
Peak memory 193872 kb
Host smart-b9ceff48-235b-477c-a5ac-8acd6161bbb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79317774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.79317774
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.512311091
Short name T282
Test name
Test status
Simulation time 38851185 ps
CPU time 0.84 seconds
Started Jun 11 12:27:20 PM PDT 24
Finished Jun 11 12:27:23 PM PDT 24
Peak memory 196336 kb
Host smart-ec12d2cc-e4c1-4b74-a2bb-0863df20c360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512311091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.512311091
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.2771839994
Short name T327
Test name
Test status
Simulation time 996880229 ps
CPU time 6.42 seconds
Started Jun 11 12:27:23 PM PDT 24
Finished Jun 11 12:27:34 PM PDT 24
Peak memory 195336 kb
Host smart-a84a2916-b8f0-4d1a-8ab1-b619150bd0c0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771839994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.2771839994
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.2500279899
Short name T597
Test name
Test status
Simulation time 97894159 ps
CPU time 1.38 seconds
Started Jun 11 12:27:22 PM PDT 24
Finished Jun 11 12:27:28 PM PDT 24
Peak memory 198040 kb
Host smart-31057736-5967-48e8-b3f8-05d2067723f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500279899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.2500279899
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.2327452055
Short name T406
Test name
Test status
Simulation time 78257171 ps
CPU time 1.01 seconds
Started Jun 11 12:27:24 PM PDT 24
Finished Jun 11 12:27:29 PM PDT 24
Peak memory 196216 kb
Host smart-9380fbfc-f807-400e-8598-4f86463e270d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327452055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.2327452055
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.1318569897
Short name T648
Test name
Test status
Simulation time 583084658 ps
CPU time 2.69 seconds
Started Jun 11 12:27:22 PM PDT 24
Finished Jun 11 12:27:30 PM PDT 24
Peak memory 197044 kb
Host smart-7d2bcdb3-df9b-4be8-8f97-46f370bfe9e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318569897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
1318569897
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.2498896546
Short name T142
Test name
Test status
Simulation time 170567016 ps
CPU time 1.01 seconds
Started Jun 11 12:27:23 PM PDT 24
Finished Jun 11 12:27:28 PM PDT 24
Peak memory 196164 kb
Host smart-5939cc87-ebf7-4318-93a2-9d53c8923609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498896546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.2498896546
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.3044587627
Short name T614
Test name
Test status
Simulation time 93481258 ps
CPU time 1.13 seconds
Started Jun 11 12:27:28 PM PDT 24
Finished Jun 11 12:27:35 PM PDT 24
Peak memory 195984 kb
Host smart-180c9d3b-d1fe-4f48-87a8-f5559e67acee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044587627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.3044587627
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.2789658820
Short name T658
Test name
Test status
Simulation time 357768603 ps
CPU time 4.22 seconds
Started Jun 11 12:27:28 PM PDT 24
Finished Jun 11 12:27:38 PM PDT 24
Peak memory 198160 kb
Host smart-a032f2fb-8dc9-4aa8-a3e7-754e884778de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789658820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.2789658820
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.1838439131
Short name T117
Test name
Test status
Simulation time 66056839 ps
CPU time 1.11 seconds
Started Jun 11 12:27:23 PM PDT 24
Finished Jun 11 12:27:29 PM PDT 24
Peak memory 195616 kb
Host smart-d0950b04-5a02-4e1e-9ca7-d9d03543b3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838439131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.1838439131
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.2736284432
Short name T23
Test name
Test status
Simulation time 240949248 ps
CPU time 0.87 seconds
Started Jun 11 12:27:25 PM PDT 24
Finished Jun 11 12:27:31 PM PDT 24
Peak memory 195068 kb
Host smart-3af27051-6a0c-439a-9bff-713ae76e425f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736284432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.2736284432
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.3479222609
Short name T380
Test name
Test status
Simulation time 70117888970 ps
CPU time 217.96 seconds
Started Jun 11 12:27:22 PM PDT 24
Finished Jun 11 12:31:05 PM PDT 24
Peak memory 197992 kb
Host smart-559999af-bd06-4e55-899c-472917ae7015
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479222609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.3479222609
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.1583397025
Short name T678
Test name
Test status
Simulation time 40005228 ps
CPU time 0.57 seconds
Started Jun 11 12:27:24 PM PDT 24
Finished Jun 11 12:27:30 PM PDT 24
Peak memory 193792 kb
Host smart-b54d0bc5-1b56-46d7-9126-f0fa7c6dfde7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583397025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.1583397025
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.2228646242
Short name T312
Test name
Test status
Simulation time 255750005 ps
CPU time 0.87 seconds
Started Jun 11 12:27:24 PM PDT 24
Finished Jun 11 12:27:31 PM PDT 24
Peak memory 195804 kb
Host smart-5a573861-df38-4f6f-b662-dca5ab3692a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228646242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.2228646242
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.3312545409
Short name T546
Test name
Test status
Simulation time 708597481 ps
CPU time 17.29 seconds
Started Jun 11 12:27:30 PM PDT 24
Finished Jun 11 12:27:54 PM PDT 24
Peak memory 196168 kb
Host smart-1fdc5c5d-0b7a-4d36-a748-e47f6f44d784
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312545409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.3312545409
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.542655621
Short name T587
Test name
Test status
Simulation time 180369841 ps
CPU time 0.81 seconds
Started Jun 11 12:27:24 PM PDT 24
Finished Jun 11 12:27:31 PM PDT 24
Peak memory 195948 kb
Host smart-49bcde46-d3fe-4ea3-8b0c-35b040e20389
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542655621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.542655621
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.2672900299
Short name T102
Test name
Test status
Simulation time 83921159 ps
CPU time 0.83 seconds
Started Jun 11 12:27:21 PM PDT 24
Finished Jun 11 12:27:26 PM PDT 24
Peak memory 196636 kb
Host smart-97a5d0b4-6628-4231-9bd6-38061dd3190e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672900299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.2672900299
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.4164040312
Short name T590
Test name
Test status
Simulation time 19962899 ps
CPU time 0.93 seconds
Started Jun 11 12:27:20 PM PDT 24
Finished Jun 11 12:27:23 PM PDT 24
Peak memory 195944 kb
Host smart-eb018718-feec-4565-a417-8712197c97b8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164040312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.4164040312
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.13404088
Short name T137
Test name
Test status
Simulation time 205112091 ps
CPU time 2.64 seconds
Started Jun 11 12:27:21 PM PDT 24
Finished Jun 11 12:27:27 PM PDT 24
Peak memory 197980 kb
Host smart-e6f299ea-6f15-480f-94d7-5fdacd056ef7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13404088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.13404088
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.1464836596
Short name T660
Test name
Test status
Simulation time 35167110 ps
CPU time 1.15 seconds
Started Jun 11 12:27:23 PM PDT 24
Finished Jun 11 12:27:29 PM PDT 24
Peak memory 195740 kb
Host smart-6729d539-2048-42d6-b5d2-3453cca8ed2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464836596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.1464836596
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.3451147554
Short name T274
Test name
Test status
Simulation time 19687821 ps
CPU time 0.67 seconds
Started Jun 11 12:27:24 PM PDT 24
Finished Jun 11 12:27:30 PM PDT 24
Peak memory 194160 kb
Host smart-2acdcf95-a586-4765-8d41-37c6ad7ea288
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451147554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.3451147554
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.3286839803
Short name T344
Test name
Test status
Simulation time 269069401 ps
CPU time 3.26 seconds
Started Jun 11 12:27:25 PM PDT 24
Finished Jun 11 12:27:34 PM PDT 24
Peak memory 197804 kb
Host smart-e0c20c94-adf2-4bad-ac9a-e06db4ed7a97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286839803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.3286839803
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.3598225299
Short name T313
Test name
Test status
Simulation time 95138090 ps
CPU time 1.26 seconds
Started Jun 11 12:27:25 PM PDT 24
Finished Jun 11 12:27:32 PM PDT 24
Peak memory 195376 kb
Host smart-003608dc-e1ed-46d3-bac4-dab7b48ddd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598225299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.3598225299
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.3876857429
Short name T118
Test name
Test status
Simulation time 70926801 ps
CPU time 1.01 seconds
Started Jun 11 12:27:26 PM PDT 24
Finished Jun 11 12:27:32 PM PDT 24
Peak memory 195440 kb
Host smart-3cf7e825-def0-44ab-8fbe-88902a297f4f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876857429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.3876857429
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.2334483158
Short name T371
Test name
Test status
Simulation time 4835075184 ps
CPU time 63.53 seconds
Started Jun 11 12:27:22 PM PDT 24
Finished Jun 11 12:28:30 PM PDT 24
Peak memory 198108 kb
Host smart-513d1b78-e351-4986-be4a-e395eaef938d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334483158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.2334483158
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.203386432
Short name T421
Test name
Test status
Simulation time 24119622 ps
CPU time 0.6 seconds
Started Jun 11 12:27:25 PM PDT 24
Finished Jun 11 12:27:31 PM PDT 24
Peak memory 193956 kb
Host smart-5c496c19-2358-421a-b408-9ded600f3e27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203386432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.203386432
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.3113963955
Short name T346
Test name
Test status
Simulation time 83775023 ps
CPU time 0.86 seconds
Started Jun 11 12:27:27 PM PDT 24
Finished Jun 11 12:27:34 PM PDT 24
Peak memory 196968 kb
Host smart-1903c424-c8c8-42cb-b35d-b794ed0b05da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113963955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.3113963955
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.1844772073
Short name T288
Test name
Test status
Simulation time 1352757702 ps
CPU time 18.81 seconds
Started Jun 11 12:27:22 PM PDT 24
Finished Jun 11 12:27:46 PM PDT 24
Peak memory 197880 kb
Host smart-ee2aecbc-08e5-4a58-bb27-d0f6b48959b1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844772073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.1844772073
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.3433678134
Short name T454
Test name
Test status
Simulation time 255567704 ps
CPU time 0.89 seconds
Started Jun 11 12:27:22 PM PDT 24
Finished Jun 11 12:27:28 PM PDT 24
Peak memory 197060 kb
Host smart-8e7027b7-267e-4539-89e2-8eb8f6b93d3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433678134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.3433678134
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.1418585447
Short name T387
Test name
Test status
Simulation time 208021933 ps
CPU time 0.65 seconds
Started Jun 11 12:27:23 PM PDT 24
Finished Jun 11 12:27:29 PM PDT 24
Peak memory 194284 kb
Host smart-5820f475-c53c-4d29-b391-18af396df157
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418585447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.1418585447
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.255513582
Short name T311
Test name
Test status
Simulation time 86144275 ps
CPU time 1.74 seconds
Started Jun 11 12:27:30 PM PDT 24
Finished Jun 11 12:27:38 PM PDT 24
Peak memory 197948 kb
Host smart-a2da0177-8803-4538-abc8-49c7e4ee59aa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255513582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.gpio_intr_with_filter_rand_intr_event.255513582
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.1382760047
Short name T232
Test name
Test status
Simulation time 356283660 ps
CPU time 2.23 seconds
Started Jun 11 12:27:27 PM PDT 24
Finished Jun 11 12:27:35 PM PDT 24
Peak memory 196968 kb
Host smart-26bc50bf-83f0-405c-bf8d-d9ef07d2c34b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382760047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
1382760047
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.1875091697
Short name T310
Test name
Test status
Simulation time 47124814 ps
CPU time 0.72 seconds
Started Jun 11 12:27:22 PM PDT 24
Finished Jun 11 12:27:27 PM PDT 24
Peak memory 195244 kb
Host smart-0433e6e9-df6d-4b33-a01b-5cfafb69f0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875091697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.1875091697
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.916416294
Short name T680
Test name
Test status
Simulation time 59502094 ps
CPU time 0.72 seconds
Started Jun 11 12:27:27 PM PDT 24
Finished Jun 11 12:27:33 PM PDT 24
Peak memory 195324 kb
Host smart-a95fb49e-867e-41bf-8b11-72a6540da5df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916416294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup_
pulldown.916416294
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.2548756195
Short name T508
Test name
Test status
Simulation time 810564089 ps
CPU time 2.99 seconds
Started Jun 11 12:27:28 PM PDT 24
Finished Jun 11 12:27:37 PM PDT 24
Peak memory 198148 kb
Host smart-e88c3b94-cf07-443c-87d7-16a1c0c0af44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548756195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.2548756195
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.3894506031
Short name T303
Test name
Test status
Simulation time 535601585 ps
CPU time 1.06 seconds
Started Jun 11 12:27:27 PM PDT 24
Finished Jun 11 12:27:34 PM PDT 24
Peak memory 195688 kb
Host smart-4e74d64e-96a6-4e29-b963-2759bcd65c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894506031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.3894506031
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.3787695809
Short name T486
Test name
Test status
Simulation time 54963345 ps
CPU time 1.35 seconds
Started Jun 11 12:27:26 PM PDT 24
Finished Jun 11 12:27:33 PM PDT 24
Peak memory 197928 kb
Host smart-7b2173d5-4489-4239-b005-90f3a1fa8b4d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787695809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.3787695809
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.4279660605
Short name T248
Test name
Test status
Simulation time 53604652979 ps
CPU time 174.87 seconds
Started Jun 11 12:27:25 PM PDT 24
Finished Jun 11 12:30:25 PM PDT 24
Peak memory 198140 kb
Host smart-fe51f7b6-29cb-418e-80d5-70919767fe47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279660605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.4279660605
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.1189464474
Short name T168
Test name
Test status
Simulation time 13261358 ps
CPU time 0.56 seconds
Started Jun 11 12:27:30 PM PDT 24
Finished Jun 11 12:27:37 PM PDT 24
Peak memory 193724 kb
Host smart-98904abf-8d78-4e21-b6e0-95cca63877c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189464474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.1189464474
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.537629739
Short name T165
Test name
Test status
Simulation time 55975849 ps
CPU time 0.83 seconds
Started Jun 11 12:27:26 PM PDT 24
Finished Jun 11 12:27:33 PM PDT 24
Peak memory 197240 kb
Host smart-ab3326f1-01d2-4ec2-9563-0a5190348a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537629739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.537629739
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.8690031
Short name T612
Test name
Test status
Simulation time 1926516900 ps
CPU time 23.34 seconds
Started Jun 11 12:27:23 PM PDT 24
Finished Jun 11 12:27:51 PM PDT 24
Peak memory 197908 kb
Host smart-48ee5f4e-c418-4416-8dd8-f2905458460e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8690031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_s
tress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stress.8690031
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.32739278
Short name T9
Test name
Test status
Simulation time 42684042 ps
CPU time 0.77 seconds
Started Jun 11 12:27:30 PM PDT 24
Finished Jun 11 12:27:37 PM PDT 24
Peak memory 195808 kb
Host smart-724dcb83-20fb-4359-b108-ec051bb5e53d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32739278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.32739278
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.3547278764
Short name T712
Test name
Test status
Simulation time 53031157 ps
CPU time 0.99 seconds
Started Jun 11 12:27:30 PM PDT 24
Finished Jun 11 12:27:37 PM PDT 24
Peak memory 195940 kb
Host smart-7a17ed0a-6e7f-49e3-b866-70d418c2edb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547278764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.3547278764
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.1240647183
Short name T594
Test name
Test status
Simulation time 313563518 ps
CPU time 2.56 seconds
Started Jun 11 12:27:30 PM PDT 24
Finished Jun 11 12:27:39 PM PDT 24
Peak memory 196244 kb
Host smart-b249e3ea-fd5a-4e45-8295-61a9502680ed
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240647183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.1240647183
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.3516065977
Short name T314
Test name
Test status
Simulation time 26897395 ps
CPU time 0.84 seconds
Started Jun 11 12:27:30 PM PDT 24
Finished Jun 11 12:27:37 PM PDT 24
Peak memory 194316 kb
Host smart-72707ad0-49af-4f4e-a3e8-4466eb69b097
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516065977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
3516065977
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.767457309
Short name T22
Test name
Test status
Simulation time 135752066 ps
CPU time 1 seconds
Started Jun 11 12:27:24 PM PDT 24
Finished Jun 11 12:27:31 PM PDT 24
Peak memory 196684 kb
Host smart-a3a8b13d-e365-43d6-8e6b-9f8a586fb39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767457309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.767457309
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.724608034
Short name T181
Test name
Test status
Simulation time 230397063 ps
CPU time 1.24 seconds
Started Jun 11 12:27:23 PM PDT 24
Finished Jun 11 12:27:29 PM PDT 24
Peak memory 195788 kb
Host smart-69472a14-b1fa-4ad5-8639-ac0380e7d70a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724608034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup_
pulldown.724608034
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.3011512856
Short name T553
Test name
Test status
Simulation time 243108871 ps
CPU time 3.85 seconds
Started Jun 11 12:27:28 PM PDT 24
Finished Jun 11 12:27:37 PM PDT 24
Peak memory 197832 kb
Host smart-4f19bf93-074e-4054-a12d-c2d60762d2cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011512856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.3011512856
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.980412687
Short name T183
Test name
Test status
Simulation time 97002727 ps
CPU time 0.84 seconds
Started Jun 11 12:27:23 PM PDT 24
Finished Jun 11 12:27:28 PM PDT 24
Peak memory 194872 kb
Host smart-5d2f4e10-e1b6-43d6-82bb-0d2fd6867eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980412687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.980412687
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.2917530718
Short name T489
Test name
Test status
Simulation time 80152072 ps
CPU time 0.9 seconds
Started Jun 11 12:27:23 PM PDT 24
Finished Jun 11 12:27:28 PM PDT 24
Peak memory 196880 kb
Host smart-e1fe55cd-ec4b-4df0-a789-9153105aff9e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917530718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.2917530718
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.1879827207
Short name T388
Test name
Test status
Simulation time 39267742498 ps
CPU time 149.69 seconds
Started Jun 11 12:27:23 PM PDT 24
Finished Jun 11 12:29:58 PM PDT 24
Peak memory 198432 kb
Host smart-73669b01-5440-4780-9b2a-c22194513a99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879827207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.1879827207
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.4225929667
Short name T909
Test name
Test status
Simulation time 521137885 ps
CPU time 0.93 seconds
Started Jun 11 01:23:37 PM PDT 24
Finished Jun 11 01:23:39 PM PDT 24
Peak memory 196684 kb
Host smart-cd976149-5343-4373-8057-21f051dd7042
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4225929667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.4225929667
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2304438676
Short name T847
Test name
Test status
Simulation time 68988667 ps
CPU time 1.34 seconds
Started Jun 11 01:23:39 PM PDT 24
Finished Jun 11 01:23:41 PM PDT 24
Peak memory 192316 kb
Host smart-b8a12a8c-76e7-4538-b274-c5034243df97
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304438676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2304438676
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2441786331
Short name T885
Test name
Test status
Simulation time 595967056 ps
CPU time 0.98 seconds
Started Jun 11 01:23:38 PM PDT 24
Finished Jun 11 01:23:41 PM PDT 24
Peak memory 192488 kb
Host smart-fc302b0e-3b0b-4f45-8510-85ca77865a61
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2441786331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.2441786331
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1702814879
Short name T900
Test name
Test status
Simulation time 119371312 ps
CPU time 1.19 seconds
Started Jun 11 01:23:38 PM PDT 24
Finished Jun 11 01:23:40 PM PDT 24
Peak memory 198604 kb
Host smart-1109aa4f-ccf8-474b-969b-71f74e8f73d6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702814879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1702814879
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2414785081
Short name T939
Test name
Test status
Simulation time 53568796 ps
CPU time 1.04 seconds
Started Jun 11 01:23:52 PM PDT 24
Finished Jun 11 01:23:54 PM PDT 24
Peak memory 192324 kb
Host smart-2293a09c-c3f8-4502-a861-a1c6360e8ae0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2414785081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.2414785081
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3355123488
Short name T878
Test name
Test status
Simulation time 258851455 ps
CPU time 1.14 seconds
Started Jun 11 01:23:51 PM PDT 24
Finished Jun 11 01:23:53 PM PDT 24
Peak memory 192252 kb
Host smart-886be2c6-b37d-47fd-91b9-34ae5f83838c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355123488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3355123488
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1287065698
Short name T861
Test name
Test status
Simulation time 186254177 ps
CPU time 1.11 seconds
Started Jun 11 01:23:51 PM PDT 24
Finished Jun 11 01:23:53 PM PDT 24
Peak memory 192264 kb
Host smart-39b1f5cc-3c87-465b-b4ac-e9dff2a65041
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1287065698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.1287065698
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2895745780
Short name T898
Test name
Test status
Simulation time 217660341 ps
CPU time 0.82 seconds
Started Jun 11 01:23:53 PM PDT 24
Finished Jun 11 01:23:55 PM PDT 24
Peak memory 196572 kb
Host smart-b3756643-6cd0-4fc6-a7de-cec664fa01cf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895745780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2895745780
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1304136170
Short name T842
Test name
Test status
Simulation time 46998145 ps
CPU time 0.98 seconds
Started Jun 11 01:23:51 PM PDT 24
Finished Jun 11 01:23:53 PM PDT 24
Peak memory 192124 kb
Host smart-25c717e6-0f6f-4657-8dd0-a9a67d99c6e6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1304136170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.1304136170
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1574846056
Short name T903
Test name
Test status
Simulation time 95416471 ps
CPU time 1.41 seconds
Started Jun 11 01:23:54 PM PDT 24
Finished Jun 11 01:23:56 PM PDT 24
Peak memory 192304 kb
Host smart-cfafece8-0121-4f9f-a13b-4ca8233c8c19
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574846056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1574846056
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2847860495
Short name T873
Test name
Test status
Simulation time 47656483 ps
CPU time 1.03 seconds
Started Jun 11 01:23:55 PM PDT 24
Finished Jun 11 01:23:57 PM PDT 24
Peak memory 192280 kb
Host smart-808a8463-9289-446a-9ff0-0bc618eba440
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2847860495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.2847860495
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3033537362
Short name T905
Test name
Test status
Simulation time 271841507 ps
CPU time 1.14 seconds
Started Jun 11 01:24:03 PM PDT 24
Finished Jun 11 01:24:05 PM PDT 24
Peak memory 192308 kb
Host smart-b15f0019-2358-4b96-a47b-017dfa6a5a22
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033537362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3033537362
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.931008133
Short name T917
Test name
Test status
Simulation time 229101625 ps
CPU time 1.4 seconds
Started Jun 11 01:24:03 PM PDT 24
Finished Jun 11 01:24:05 PM PDT 24
Peak memory 192280 kb
Host smart-1c64f156-c057-450f-a19d-730299014fcb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=931008133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.931008133
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3387612497
Short name T845
Test name
Test status
Simulation time 49130840 ps
CPU time 0.98 seconds
Started Jun 11 01:24:02 PM PDT 24
Finished Jun 11 01:24:04 PM PDT 24
Peak memory 192336 kb
Host smart-d086f452-5feb-48ce-9aa4-63bea66a09fc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387612497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3387612497
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1167982049
Short name T846
Test name
Test status
Simulation time 71821801 ps
CPU time 1.1 seconds
Started Jun 11 01:24:03 PM PDT 24
Finished Jun 11 01:24:05 PM PDT 24
Peak memory 192324 kb
Host smart-b318e032-13b3-4583-ae71-48f1c646ce0c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1167982049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.1167982049
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3550229264
Short name T869
Test name
Test status
Simulation time 48107437 ps
CPU time 1.33 seconds
Started Jun 11 01:24:01 PM PDT 24
Finished Jun 11 01:24:03 PM PDT 24
Peak memory 192184 kb
Host smart-2bfcb089-77a5-44ae-af3e-47f126361767
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550229264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3550229264
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.581722030
Short name T886
Test name
Test status
Simulation time 33290260 ps
CPU time 0.94 seconds
Started Jun 11 01:24:05 PM PDT 24
Finished Jun 11 01:24:07 PM PDT 24
Peak memory 196712 kb
Host smart-976eb897-5744-48e2-ac6f-163131c7073e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=581722030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.581722030
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2019388825
Short name T887
Test name
Test status
Simulation time 88335554 ps
CPU time 1.06 seconds
Started Jun 11 01:24:03 PM PDT 24
Finished Jun 11 01:24:05 PM PDT 24
Peak memory 196996 kb
Host smart-0f4fbc54-10a1-4e52-9fda-51ba48c582d7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019388825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2019388825
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.554160989
Short name T921
Test name
Test status
Simulation time 33930552 ps
CPU time 1.06 seconds
Started Jun 11 01:24:06 PM PDT 24
Finished Jun 11 01:24:08 PM PDT 24
Peak memory 192216 kb
Host smart-2f6c1eb2-a2ac-4a82-8687-bc79d4f3a36a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=554160989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.554160989
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3207573464
Short name T871
Test name
Test status
Simulation time 272484028 ps
CPU time 1.21 seconds
Started Jun 11 01:24:04 PM PDT 24
Finished Jun 11 01:24:07 PM PDT 24
Peak memory 192280 kb
Host smart-3beb7532-611f-4d9a-afdc-cf306557318f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207573464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3207573464
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2768097605
Short name T896
Test name
Test status
Simulation time 123250329 ps
CPU time 0.76 seconds
Started Jun 11 01:24:05 PM PDT 24
Finished Jun 11 01:24:07 PM PDT 24
Peak memory 196716 kb
Host smart-dbb9df6c-9199-4651-a003-baa49600e052
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2768097605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.2768097605
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2526513790
Short name T863
Test name
Test status
Simulation time 114827161 ps
CPU time 0.87 seconds
Started Jun 11 01:24:04 PM PDT 24
Finished Jun 11 01:24:06 PM PDT 24
Peak memory 192104 kb
Host smart-af988244-a15e-41d5-9feb-292f0b37fbf3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526513790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2526513790
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1731211429
Short name T899
Test name
Test status
Simulation time 123363522 ps
CPU time 0.94 seconds
Started Jun 11 01:24:05 PM PDT 24
Finished Jun 11 01:24:07 PM PDT 24
Peak memory 192288 kb
Host smart-1b046eb6-b660-4b81-a3d7-8a144e0307d7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1731211429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.1731211429
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3039366424
Short name T920
Test name
Test status
Simulation time 48147776 ps
CPU time 1.22 seconds
Started Jun 11 01:24:03 PM PDT 24
Finished Jun 11 01:24:05 PM PDT 24
Peak memory 192196 kb
Host smart-3c94d12d-fa92-4292-ab55-0ec8fa1b87a9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039366424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3039366424
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2050124709
Short name T856
Test name
Test status
Simulation time 249252265 ps
CPU time 0.96 seconds
Started Jun 11 01:23:50 PM PDT 24
Finished Jun 11 01:23:52 PM PDT 24
Peak memory 192092 kb
Host smart-0a320fa2-8c10-43bb-a91a-0591da8f05eb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2050124709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.2050124709
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1789486484
Short name T850
Test name
Test status
Simulation time 94126472 ps
CPU time 0.93 seconds
Started Jun 11 01:23:50 PM PDT 24
Finished Jun 11 01:23:52 PM PDT 24
Peak memory 196792 kb
Host smart-d07fd2f6-985e-41b8-bb28-65d45a778965
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789486484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1789486484
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.4251705196
Short name T935
Test name
Test status
Simulation time 53970254 ps
CPU time 1.15 seconds
Started Jun 11 01:24:04 PM PDT 24
Finished Jun 11 01:24:07 PM PDT 24
Peak memory 192292 kb
Host smart-e8d6f4f1-3f17-49f8-a7a3-a5eaf4b467cc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4251705196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.4251705196
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3731534467
Short name T933
Test name
Test status
Simulation time 319214405 ps
CPU time 1.25 seconds
Started Jun 11 01:24:05 PM PDT 24
Finished Jun 11 01:24:07 PM PDT 24
Peak memory 192244 kb
Host smart-95d14e18-924a-4e97-9265-c5789cac782c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731534467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3731534467
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.4266861638
Short name T876
Test name
Test status
Simulation time 118224859 ps
CPU time 0.87 seconds
Started Jun 11 01:24:05 PM PDT 24
Finished Jun 11 01:24:07 PM PDT 24
Peak memory 192084 kb
Host smart-77c9b3ab-586c-44e8-b95b-7d64f5828776
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4266861638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.4266861638
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2130726317
Short name T936
Test name
Test status
Simulation time 699452468 ps
CPU time 1.39 seconds
Started Jun 11 01:24:03 PM PDT 24
Finished Jun 11 01:24:05 PM PDT 24
Peak memory 197056 kb
Host smart-55bd4d75-95bd-4170-ba48-04910421db77
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130726317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2130726317
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3240263693
Short name T841
Test name
Test status
Simulation time 125148294 ps
CPU time 1.01 seconds
Started Jun 11 01:24:03 PM PDT 24
Finished Jun 11 01:24:05 PM PDT 24
Peak memory 196968 kb
Host smart-8af9f3ea-fd08-4923-b12b-b7a9a0b5a947
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3240263693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.3240263693
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2239296744
Short name T924
Test name
Test status
Simulation time 33005448 ps
CPU time 0.78 seconds
Started Jun 11 01:24:02 PM PDT 24
Finished Jun 11 01:24:03 PM PDT 24
Peak memory 195644 kb
Host smart-bc17904e-9d45-4e5f-a6d4-e30f9110bd33
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239296744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2239296744
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.483550334
Short name T934
Test name
Test status
Simulation time 67360835 ps
CPU time 1.09 seconds
Started Jun 11 01:24:03 PM PDT 24
Finished Jun 11 01:24:06 PM PDT 24
Peak memory 192264 kb
Host smart-42560434-a1ef-4929-9fa7-3aff0050552b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=483550334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.483550334
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4174664029
Short name T894
Test name
Test status
Simulation time 171600096 ps
CPU time 1.18 seconds
Started Jun 11 01:24:02 PM PDT 24
Finished Jun 11 01:24:04 PM PDT 24
Peak memory 198520 kb
Host smart-494bbbf7-36cb-4d5f-bc14-08f4ead2bd7a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174664029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4174664029
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1713996736
Short name T867
Test name
Test status
Simulation time 47818305 ps
CPU time 1.21 seconds
Started Jun 11 01:24:04 PM PDT 24
Finished Jun 11 01:24:06 PM PDT 24
Peak memory 192276 kb
Host smart-0434e664-99c6-4a29-9acb-3c8fce2f4386
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1713996736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.1713996736
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4206717903
Short name T870
Test name
Test status
Simulation time 138403638 ps
CPU time 0.86 seconds
Started Jun 11 01:24:04 PM PDT 24
Finished Jun 11 01:24:06 PM PDT 24
Peak memory 192096 kb
Host smart-fd9e0bda-52ef-4990-acb5-69fa8d0e9c60
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206717903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4206717903
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1332632305
Short name T860
Test name
Test status
Simulation time 179821512 ps
CPU time 1.34 seconds
Started Jun 11 01:24:04 PM PDT 24
Finished Jun 11 01:24:06 PM PDT 24
Peak memory 192260 kb
Host smart-fd76371e-b23d-4e55-b665-2e05d420a8fb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1332632305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.1332632305
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3399523594
Short name T848
Test name
Test status
Simulation time 78980427 ps
CPU time 1.33 seconds
Started Jun 11 01:24:03 PM PDT 24
Finished Jun 11 01:24:05 PM PDT 24
Peak memory 192280 kb
Host smart-1239751b-42b3-49cf-b2d9-144ef9884abf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399523594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3399523594
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3990151961
Short name T862
Test name
Test status
Simulation time 281781511 ps
CPU time 1.33 seconds
Started Jun 11 01:24:04 PM PDT 24
Finished Jun 11 01:24:07 PM PDT 24
Peak memory 192284 kb
Host smart-c2cdb982-7f1f-40fa-bf14-a5d5dfdde1d5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3990151961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.3990151961
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3253649061
Short name T922
Test name
Test status
Simulation time 22861782 ps
CPU time 0.78 seconds
Started Jun 11 01:24:03 PM PDT 24
Finished Jun 11 01:24:05 PM PDT 24
Peak memory 192140 kb
Host smart-55ef5d20-9b05-4355-8c9c-54d9db002157
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253649061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3253649061
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1168165264
Short name T902
Test name
Test status
Simulation time 141381679 ps
CPU time 1.11 seconds
Started Jun 11 01:24:04 PM PDT 24
Finished Jun 11 01:24:06 PM PDT 24
Peak memory 192316 kb
Host smart-be1ae509-7b4a-4c99-952b-d98b7e7e8941
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1168165264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.1168165264
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3320353891
Short name T890
Test name
Test status
Simulation time 1102337035 ps
CPU time 1.13 seconds
Started Jun 11 01:24:04 PM PDT 24
Finished Jun 11 01:24:07 PM PDT 24
Peak memory 192304 kb
Host smart-135c7365-39da-4af9-83db-69252476c7cf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320353891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3320353891
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.445267333
Short name T881
Test name
Test status
Simulation time 381975118 ps
CPU time 1.24 seconds
Started Jun 11 01:24:02 PM PDT 24
Finished Jun 11 01:24:04 PM PDT 24
Peak memory 192276 kb
Host smart-df6f5df2-c2ae-4aed-9fdb-3b06cbb41a61
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=445267333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.445267333
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1498379358
Short name T915
Test name
Test status
Simulation time 177822589 ps
CPU time 1.48 seconds
Started Jun 11 01:24:02 PM PDT 24
Finished Jun 11 01:24:05 PM PDT 24
Peak memory 192272 kb
Host smart-31808df8-aa37-452a-9840-2ac75e8f2cc2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498379358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1498379358
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2808560230
Short name T929
Test name
Test status
Simulation time 104503278 ps
CPU time 0.89 seconds
Started Jun 11 01:24:03 PM PDT 24
Finished Jun 11 01:24:05 PM PDT 24
Peak memory 192112 kb
Host smart-1beb0dd8-201c-415e-b73e-529cc41f8047
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2808560230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.2808560230
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.124470984
Short name T913
Test name
Test status
Simulation time 333191999 ps
CPU time 0.97 seconds
Started Jun 11 01:24:15 PM PDT 24
Finished Jun 11 01:24:19 PM PDT 24
Peak memory 192100 kb
Host smart-202168e7-1e1b-4d86-81a6-3b1957d8ba7a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124470984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.124470984
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.169831198
Short name T912
Test name
Test status
Simulation time 38330231 ps
CPU time 0.89 seconds
Started Jun 11 01:23:51 PM PDT 24
Finished Jun 11 01:23:53 PM PDT 24
Peak memory 192124 kb
Host smart-afa9af6d-2e0d-4348-98be-b39342c437bb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=169831198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.169831198
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2368061915
Short name T907
Test name
Test status
Simulation time 943376319 ps
CPU time 1.26 seconds
Started Jun 11 01:23:51 PM PDT 24
Finished Jun 11 01:23:53 PM PDT 24
Peak memory 192280 kb
Host smart-f960a6cf-3e31-4313-90eb-6d02d2ffa481
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368061915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2368061915
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1103923831
Short name T918
Test name
Test status
Simulation time 72825462 ps
CPU time 1.28 seconds
Started Jun 11 01:24:15 PM PDT 24
Finished Jun 11 01:24:20 PM PDT 24
Peak memory 197140 kb
Host smart-8e810763-ba14-424d-b0db-3aaf66bb7b93
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1103923831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.1103923831
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2016410059
Short name T840
Test name
Test status
Simulation time 178959914 ps
CPU time 1.21 seconds
Started Jun 11 01:24:16 PM PDT 24
Finished Jun 11 01:24:20 PM PDT 24
Peak memory 198108 kb
Host smart-1853ea6a-00ca-40a5-96d0-7b2130bd0851
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016410059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2016410059
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2748064083
Short name T853
Test name
Test status
Simulation time 206496156 ps
CPU time 1.2 seconds
Started Jun 11 01:24:15 PM PDT 24
Finished Jun 11 01:24:19 PM PDT 24
Peak memory 198608 kb
Host smart-8ad73218-1853-4401-a630-dca6588514f2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2748064083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.2748064083
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3520743166
Short name T911
Test name
Test status
Simulation time 142299713 ps
CPU time 1.02 seconds
Started Jun 11 01:24:15 PM PDT 24
Finished Jun 11 01:24:20 PM PDT 24
Peak memory 192224 kb
Host smart-a10635c1-46b5-4e30-8560-72581e4f5ef3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520743166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3520743166
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3921428600
Short name T875
Test name
Test status
Simulation time 149308533 ps
CPU time 1.27 seconds
Started Jun 11 01:24:14 PM PDT 24
Finished Jun 11 01:24:18 PM PDT 24
Peak memory 197512 kb
Host smart-db27e21c-5e47-4717-a1e3-109c1d057707
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3921428600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.3921428600
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2647691528
Short name T901
Test name
Test status
Simulation time 723560940 ps
CPU time 1.11 seconds
Started Jun 11 01:24:18 PM PDT 24
Finished Jun 11 01:24:21 PM PDT 24
Peak memory 197260 kb
Host smart-601ec939-4b89-4e3b-a1fb-11111346d04f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647691528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2647691528
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1833563794
Short name T893
Test name
Test status
Simulation time 97625394 ps
CPU time 0.89 seconds
Started Jun 11 01:24:14 PM PDT 24
Finished Jun 11 01:24:15 PM PDT 24
Peak memory 192244 kb
Host smart-db82e47b-1804-4f8a-806e-4065ae517e85
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1833563794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.1833563794
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.480875752
Short name T904
Test name
Test status
Simulation time 170709503 ps
CPU time 0.91 seconds
Started Jun 11 01:24:15 PM PDT 24
Finished Jun 11 01:24:19 PM PDT 24
Peak memory 192120 kb
Host smart-aabf93b7-62ed-4ea2-9abe-752221bb2500
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480875752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.480875752
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2971361637
Short name T895
Test name
Test status
Simulation time 53923538 ps
CPU time 1.13 seconds
Started Jun 11 01:24:16 PM PDT 24
Finished Jun 11 01:24:20 PM PDT 24
Peak memory 192212 kb
Host smart-621ef75f-365f-4596-bd3b-e74d4ddd3baa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2971361637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.2971361637
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4194722526
Short name T843
Test name
Test status
Simulation time 29337172 ps
CPU time 0.92 seconds
Started Jun 11 01:24:15 PM PDT 24
Finished Jun 11 01:24:20 PM PDT 24
Peak memory 198440 kb
Host smart-24e4da0e-b2dc-4fc7-989c-63f4315c807b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194722526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4194722526
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1423573687
Short name T864
Test name
Test status
Simulation time 50958522 ps
CPU time 1.43 seconds
Started Jun 11 01:24:15 PM PDT 24
Finished Jun 11 01:24:20 PM PDT 24
Peak memory 192300 kb
Host smart-974955b2-9b64-450d-9df8-ad854f662fb3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1423573687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.1423573687
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.581025956
Short name T923
Test name
Test status
Simulation time 43766324 ps
CPU time 1.06 seconds
Started Jun 11 01:24:14 PM PDT 24
Finished Jun 11 01:24:19 PM PDT 24
Peak memory 197036 kb
Host smart-600f6141-71e6-44f2-84ef-ec46cf23983f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581025956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.581025956
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3682018048
Short name T926
Test name
Test status
Simulation time 100469614 ps
CPU time 0.98 seconds
Started Jun 11 01:24:15 PM PDT 24
Finished Jun 11 01:24:20 PM PDT 24
Peak memory 192132 kb
Host smart-00b93c2f-e3a4-4087-8efa-14b0f5b78ef0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3682018048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.3682018048
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1155913024
Short name T931
Test name
Test status
Simulation time 141534092 ps
CPU time 1.34 seconds
Started Jun 11 01:24:16 PM PDT 24
Finished Jun 11 01:24:20 PM PDT 24
Peak memory 192308 kb
Host smart-6184d045-c6b1-4fe8-b77b-3ec5c237df61
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155913024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1155913024
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.704440466
Short name T880
Test name
Test status
Simulation time 276849020 ps
CPU time 1.43 seconds
Started Jun 11 01:24:18 PM PDT 24
Finished Jun 11 01:24:22 PM PDT 24
Peak memory 192296 kb
Host smart-ad62d7f3-7ba6-4e02-b0a3-b1fb9b53a142
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=704440466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.704440466
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2459754281
Short name T849
Test name
Test status
Simulation time 76010238 ps
CPU time 1.14 seconds
Started Jun 11 01:24:16 PM PDT 24
Finished Jun 11 01:24:20 PM PDT 24
Peak memory 192196 kb
Host smart-43a2418c-089a-4004-aea3-7ff519b2cb24
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459754281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2459754281
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2927107672
Short name T855
Test name
Test status
Simulation time 440163121 ps
CPU time 1.56 seconds
Started Jun 11 01:24:14 PM PDT 24
Finished Jun 11 01:24:17 PM PDT 24
Peak memory 192316 kb
Host smart-7d060eb0-fc5b-4924-8642-acbec22cea31
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2927107672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.2927107672
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1950703849
Short name T927
Test name
Test status
Simulation time 120749368 ps
CPU time 0.91 seconds
Started Jun 11 01:24:15 PM PDT 24
Finished Jun 11 01:24:20 PM PDT 24
Peak memory 192116 kb
Host smart-d51499b1-cddb-463a-90a5-ab708200b98f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950703849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1950703849
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.124916892
Short name T930
Test name
Test status
Simulation time 67304103 ps
CPU time 1.2 seconds
Started Jun 11 01:24:17 PM PDT 24
Finished Jun 11 01:24:21 PM PDT 24
Peak memory 197132 kb
Host smart-7fadabc5-3b44-42b3-a629-82fff6977993
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=124916892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.124916892
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3431877312
Short name T938
Test name
Test status
Simulation time 288021175 ps
CPU time 1.31 seconds
Started Jun 11 01:24:14 PM PDT 24
Finished Jun 11 01:24:16 PM PDT 24
Peak memory 192288 kb
Host smart-ad6d40dd-0431-436e-8471-ddb4053896c4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431877312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3431877312
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2463367782
Short name T857
Test name
Test status
Simulation time 157440059 ps
CPU time 0.98 seconds
Started Jun 11 01:23:51 PM PDT 24
Finished Jun 11 01:23:53 PM PDT 24
Peak memory 192264 kb
Host smart-77922cb8-8617-451b-b7d1-f6b3bfaa1303
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2463367782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.2463367782
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1166770912
Short name T877
Test name
Test status
Simulation time 188066407 ps
CPU time 1 seconds
Started Jun 11 01:23:53 PM PDT 24
Finished Jun 11 01:23:55 PM PDT 24
Peak memory 198584 kb
Host smart-5dc1c9bb-d15c-4cee-85e2-b6c17bd9c793
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166770912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1166770912
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.4154614523
Short name T937
Test name
Test status
Simulation time 51137578 ps
CPU time 1.08 seconds
Started Jun 11 01:24:15 PM PDT 24
Finished Jun 11 01:24:20 PM PDT 24
Peak memory 198592 kb
Host smart-abad8d83-115a-4421-ac66-448023f621c3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4154614523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.4154614523
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3803196620
Short name T854
Test name
Test status
Simulation time 54544479 ps
CPU time 0.97 seconds
Started Jun 11 01:24:13 PM PDT 24
Finished Jun 11 01:24:14 PM PDT 24
Peak memory 192136 kb
Host smart-0d1f19b1-7b67-41f2-9283-e9e66b508059
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803196620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3803196620
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1993865011
Short name T858
Test name
Test status
Simulation time 100134715 ps
CPU time 1.05 seconds
Started Jun 11 01:24:13 PM PDT 24
Finished Jun 11 01:24:15 PM PDT 24
Peak memory 192180 kb
Host smart-23c1f524-5dc2-44ab-ba08-9ede29cfd99f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1993865011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.1993865011
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3093221047
Short name T872
Test name
Test status
Simulation time 192745669 ps
CPU time 1.11 seconds
Started Jun 11 01:24:16 PM PDT 24
Finished Jun 11 01:24:20 PM PDT 24
Peak memory 192256 kb
Host smart-4b3a3cb9-a583-4b0f-b326-87437c321a09
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093221047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3093221047
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.2305305221
Short name T932
Test name
Test status
Simulation time 214605143 ps
CPU time 1.1 seconds
Started Jun 11 01:24:14 PM PDT 24
Finished Jun 11 01:24:18 PM PDT 24
Peak memory 192288 kb
Host smart-003ccfda-874f-41e4-b421-db1de429937a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2305305221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.2305305221
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2009128743
Short name T882
Test name
Test status
Simulation time 180654492 ps
CPU time 1.32 seconds
Started Jun 11 01:24:14 PM PDT 24
Finished Jun 11 01:24:16 PM PDT 24
Peak memory 192296 kb
Host smart-94b01af9-7480-4c70-9bcf-ab6502b0a988
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009128743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2009128743
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3476994454
Short name T906
Test name
Test status
Simulation time 36356993 ps
CPU time 0.94 seconds
Started Jun 11 01:24:15 PM PDT 24
Finished Jun 11 01:24:19 PM PDT 24
Peak memory 198424 kb
Host smart-a2e0b79c-41c2-4758-9b94-9b09d39cb39f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3476994454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.3476994454
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1292215603
Short name T910
Test name
Test status
Simulation time 116323633 ps
CPU time 1.35 seconds
Started Jun 11 01:24:17 PM PDT 24
Finished Jun 11 01:24:21 PM PDT 24
Peak memory 192312 kb
Host smart-bbc1ee4a-5f76-4068-aed8-a0ce5ddd2a59
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292215603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1292215603
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1453796695
Short name T844
Test name
Test status
Simulation time 195658664 ps
CPU time 1.13 seconds
Started Jun 11 01:24:15 PM PDT 24
Finished Jun 11 01:24:19 PM PDT 24
Peak memory 198624 kb
Host smart-e256e641-b05b-4082-a543-1a27bea7b769
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1453796695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.1453796695
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.139547835
Short name T884
Test name
Test status
Simulation time 79854130 ps
CPU time 0.82 seconds
Started Jun 11 01:24:15 PM PDT 24
Finished Jun 11 01:24:20 PM PDT 24
Peak memory 192004 kb
Host smart-5193db58-4a1b-420b-a417-7cd61a78e8e6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139547835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.139547835
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.3579893861
Short name T888
Test name
Test status
Simulation time 169736985 ps
CPU time 1.13 seconds
Started Jun 11 01:24:25 PM PDT 24
Finished Jun 11 01:24:27 PM PDT 24
Peak memory 192284 kb
Host smart-123cfb75-19c5-420f-916e-9c7afda3950f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3579893861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.3579893861
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2078230687
Short name T859
Test name
Test status
Simulation time 47910038 ps
CPU time 1 seconds
Started Jun 11 01:24:24 PM PDT 24
Finished Jun 11 01:24:27 PM PDT 24
Peak memory 198448 kb
Host smart-902344ec-2165-437f-8038-a754b312a23f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078230687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2078230687
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1845462917
Short name T883
Test name
Test status
Simulation time 77805094 ps
CPU time 1.6 seconds
Started Jun 11 01:24:27 PM PDT 24
Finished Jun 11 01:24:30 PM PDT 24
Peak memory 197212 kb
Host smart-0c481983-6c6c-458a-8eb3-0134913baf96
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1845462917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.1845462917
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3978951970
Short name T925
Test name
Test status
Simulation time 38025306 ps
CPU time 0.89 seconds
Started Jun 11 01:24:25 PM PDT 24
Finished Jun 11 01:24:27 PM PDT 24
Peak memory 192120 kb
Host smart-e24229d1-2268-4d14-a25a-ede1ef3ecfb7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978951970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3978951970
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1998748030
Short name T866
Test name
Test status
Simulation time 108850354 ps
CPU time 1.06 seconds
Started Jun 11 01:24:27 PM PDT 24
Finished Jun 11 01:24:29 PM PDT 24
Peak memory 192308 kb
Host smart-b5b96eae-4b4b-48c3-8dff-f70fa17ed6c3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1998748030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.1998748030
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2498522013
Short name T892
Test name
Test status
Simulation time 157935038 ps
CPU time 0.84 seconds
Started Jun 11 01:24:27 PM PDT 24
Finished Jun 11 01:24:29 PM PDT 24
Peak memory 196712 kb
Host smart-dae8c393-5f27-48ea-a655-aa4fb06cf55e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498522013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2498522013
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.2868579235
Short name T914
Test name
Test status
Simulation time 103108073 ps
CPU time 1.29 seconds
Started Jun 11 01:24:26 PM PDT 24
Finished Jun 11 01:24:28 PM PDT 24
Peak memory 192324 kb
Host smart-5893b195-89a3-4d06-9c73-52db687088e1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2868579235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.2868579235
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1394191907
Short name T928
Test name
Test status
Simulation time 69198752 ps
CPU time 1.27 seconds
Started Jun 11 01:24:26 PM PDT 24
Finished Jun 11 01:24:28 PM PDT 24
Peak memory 198616 kb
Host smart-4040ad92-ff4e-4a86-97d2-34ac5715ef8d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394191907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1394191907
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1154979216
Short name T874
Test name
Test status
Simulation time 194143644 ps
CPU time 0.97 seconds
Started Jun 11 01:24:25 PM PDT 24
Finished Jun 11 01:24:27 PM PDT 24
Peak memory 192272 kb
Host smart-31a5d00d-ed30-4ab5-878f-9c540f7cbf5d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1154979216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.1154979216
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1614099942
Short name T897
Test name
Test status
Simulation time 140121206 ps
CPU time 1.36 seconds
Started Jun 11 01:24:26 PM PDT 24
Finished Jun 11 01:24:28 PM PDT 24
Peak memory 198656 kb
Host smart-fb863992-e187-45e0-b6f7-27cfa825292c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614099942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1614099942
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.88481402
Short name T879
Test name
Test status
Simulation time 39499149 ps
CPU time 1.05 seconds
Started Jun 11 01:23:50 PM PDT 24
Finished Jun 11 01:23:52 PM PDT 24
Peak memory 197460 kb
Host smart-21f98022-3c0b-4607-9910-99b17cd80c06
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=88481402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.88481402
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2307879377
Short name T908
Test name
Test status
Simulation time 51978750 ps
CPU time 0.76 seconds
Started Jun 11 01:23:50 PM PDT 24
Finished Jun 11 01:23:52 PM PDT 24
Peak memory 192036 kb
Host smart-3ee67a24-0498-4f29-979a-c68879e83604
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307879377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2307879377
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2821182293
Short name T889
Test name
Test status
Simulation time 154393927 ps
CPU time 1.47 seconds
Started Jun 11 01:23:51 PM PDT 24
Finished Jun 11 01:23:53 PM PDT 24
Peak memory 192248 kb
Host smart-360d1c6f-c125-4c3b-a9ef-a55db0b4ec9a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2821182293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.2821182293
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2776761170
Short name T852
Test name
Test status
Simulation time 156690104 ps
CPU time 0.99 seconds
Started Jun 11 01:23:50 PM PDT 24
Finished Jun 11 01:23:52 PM PDT 24
Peak memory 198480 kb
Host smart-a73558d4-6da3-4299-9e11-cb901a57afbd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776761170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2776761170
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3037929097
Short name T868
Test name
Test status
Simulation time 66805431 ps
CPU time 1.01 seconds
Started Jun 11 01:23:51 PM PDT 24
Finished Jun 11 01:23:53 PM PDT 24
Peak memory 192256 kb
Host smart-bea968a2-2d67-407a-84cb-66664d4381c4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3037929097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.3037929097
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2942431014
Short name T916
Test name
Test status
Simulation time 61466607 ps
CPU time 1.15 seconds
Started Jun 11 01:23:51 PM PDT 24
Finished Jun 11 01:23:53 PM PDT 24
Peak memory 196996 kb
Host smart-2e61a3d3-4b0f-4f62-931a-2a67306630ab
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942431014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2942431014
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2506406229
Short name T891
Test name
Test status
Simulation time 77920613 ps
CPU time 1.13 seconds
Started Jun 11 01:23:51 PM PDT 24
Finished Jun 11 01:23:53 PM PDT 24
Peak memory 192280 kb
Host smart-374db7a5-b487-4caa-b3e4-5590e9290200
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2506406229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.2506406229
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.255788483
Short name T865
Test name
Test status
Simulation time 40592237 ps
CPU time 0.86 seconds
Started Jun 11 01:23:51 PM PDT 24
Finished Jun 11 01:23:53 PM PDT 24
Peak memory 196776 kb
Host smart-200a9889-5a44-4b8a-b609-1a7e6bdbc6c7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255788483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.255788483
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.271375884
Short name T851
Test name
Test status
Simulation time 281308849 ps
CPU time 1.1 seconds
Started Jun 11 01:23:52 PM PDT 24
Finished Jun 11 01:23:54 PM PDT 24
Peak memory 192284 kb
Host smart-498fcd1a-0824-4aeb-82fe-0dec4e21d4e3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=271375884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.271375884
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2567248864
Short name T919
Test name
Test status
Simulation time 320302247 ps
CPU time 1.27 seconds
Started Jun 11 01:23:52 PM PDT 24
Finished Jun 11 01:23:55 PM PDT 24
Peak memory 198604 kb
Host smart-e014a455-2519-4efd-a659-bf4f9951086c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567248864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2567248864
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%