Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3452767	1			T23	103		T24	318		T25	1
all_pins[1]	3452767	1			T23	103		T24	318		T25	1
all_pins[2]	3452767	1			T23	103		T24	318		T25	1
all_pins[3]	3452767	1			T23	103		T24	318		T25	1
all_pins[4]	3452767	1			T23	103		T24	318		T25	1
all_pins[5]	3452767	1			T23	103		T24	318		T25	1
all_pins[6]	3452767	1			T23	103		T24	318		T25	1
all_pins[7]	3452767	1			T23	103		T24	318		T25	1
all_pins[8]	3452767	1			T23	103		T24	318		T25	1
all_pins[9]	3452767	1			T23	103		T24	318		T25	1
all_pins[10]	3452767	1			T23	103		T24	318		T25	1
all_pins[11]	3452767	1			T23	103		T24	318		T25	1
all_pins[12]	3452767	1			T23	103		T24	318		T25	1
all_pins[13]	3452767	1			T23	103		T24	318		T25	1
all_pins[14]	3452767	1			T23	103		T24	318		T25	1
all_pins[15]	3452767	1			T23	103		T24	318		T25	1
all_pins[16]	3452767	1			T23	103		T24	318		T25	1
all_pins[17]	3452767	1			T23	103		T24	318		T25	1
all_pins[18]	3452767	1			T23	103		T24	318		T25	1
all_pins[19]	3452767	1			T23	103		T24	318		T25	1
all_pins[20]	3452767	1			T23	103		T24	318		T25	1
all_pins[21]	3452767	1			T23	103		T24	318		T25	1
all_pins[22]	3452767	1			T23	103		T24	318		T25	1
all_pins[23]	3452767	1			T23	103		T24	318		T25	1
all_pins[24]	3452767	1			T23	103		T24	318		T25	1
all_pins[25]	3452767	1			T23	103		T24	318		T25	1
all_pins[26]	3452767	1			T23	103		T24	318		T25	1
all_pins[27]	3452767	1			T23	103		T24	318		T25	1
all_pins[28]	3452767	1			T23	103		T24	318		T25	1
all_pins[29]	3452767	1			T23	103		T24	318		T25	1
all_pins[30]	3452767	1			T23	103		T24	318		T25	1
all_pins[31]	3452767	1			T23	103		T24	318		T25	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	68613167	1			T23	2045		T24	6196		T25	32
values[0x1]	41875377	1			T23	1251		T24	3980		T1	189405
transitions[0x0=>0x1]	25069356	1			T23	768		T24	2345		T1	113271
transitions[0x1=>0x0]	25069200	1			T23	768		T24	2344		T1	113271

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2139869	1			T23	59		T24	180		T25	1
all_pins[0]	values[0x1]	1312898	1			T23	44		T24	138		T1	5698
all_pins[0]	transitions[0x0=>0x1]	811940	1			T23	20		T24	94		T1	3406
all_pins[0]	transitions[0x1=>0x0]	808390	1			T23	26		T24	79		T1	3918
all_pins[1]	values[0x0]	2143075	1			T23	53		T24	210		T25	1
all_pins[1]	values[0x1]	1309692	1			T23	50		T24	108		T1	5594
all_pins[1]	transitions[0x0=>0x1]	782718	1			T23	9		T24	55		T1	3393
all_pins[1]	transitions[0x1=>0x0]	785924	1			T23	3		T24	85		T1	3497
all_pins[2]	values[0x0]	2149117	1			T23	73		T24	163		T25	1
all_pins[2]	values[0x1]	1303650	1			T23	30		T24	155		T1	5908
all_pins[2]	transitions[0x0=>0x1]	780024	1			T23	14		T24	100		T1	3584
all_pins[2]	transitions[0x1=>0x0]	786066	1			T23	34		T24	53		T1	3270
all_pins[3]	values[0x0]	2146316	1			T23	72		T24	186		T25	1
all_pins[3]	values[0x1]	1306451	1			T23	31		T24	132		T1	5856
all_pins[3]	transitions[0x0=>0x1]	783854	1			T23	20		T24	64		T1	3593
all_pins[3]	transitions[0x1=>0x0]	781053	1			T23	19		T24	87		T1	3645
all_pins[4]	values[0x0]	2143723	1			T23	66		T24	181		T25	1
all_pins[4]	values[0x1]	1309044	1			T23	37		T24	137		T1	6025
all_pins[4]	transitions[0x0=>0x1]	783564	1			T23	28		T24	64		T1	3660
all_pins[4]	transitions[0x1=>0x0]	780971	1			T23	22		T24	59		T1	3491
all_pins[5]	values[0x0]	2145486	1			T23	56		T24	165		T25	1
all_pins[5]	values[0x1]	1307281	1			T23	47		T24	153		T1	5830
all_pins[5]	transitions[0x0=>0x1]	780430	1			T23	35		T24	74		T1	3553
all_pins[5]	transitions[0x1=>0x0]	782193	1			T23	25		T24	58		T1	3748
all_pins[6]	values[0x0]	2141765	1			T23	57		T24	165		T25	1
all_pins[6]	values[0x1]	1311002	1			T23	46		T24	153		T1	6113
all_pins[6]	transitions[0x0=>0x1]	784224	1			T23	31		T24	83		T1	3714
all_pins[6]	transitions[0x1=>0x0]	780503	1			T23	32		T24	83		T1	3431
all_pins[7]	values[0x0]	2147600	1			T23	68		T24	158		T25	1
all_pins[7]	values[0x1]	1305167	1			T23	35		T24	160		T1	5803
all_pins[7]	transitions[0x0=>0x1]	780721	1			T23	19		T24	81		T1	3439
all_pins[7]	transitions[0x1=>0x0]	786556	1			T23	30		T24	74		T1	3749
all_pins[8]	values[0x0]	2141900	1			T23	67		T24	143		T25	1
all_pins[8]	values[0x1]	1310867	1			T23	36		T24	175		T1	6134
all_pins[8]	transitions[0x0=>0x1]	784320	1			T23	26		T24	82		T1	3736
all_pins[8]	transitions[0x1=>0x0]	778620	1			T23	25		T24	67		T1	3405
all_pins[9]	values[0x0]	2143546	1			T23	68		T24	195		T25	1
all_pins[9]	values[0x1]	1309221	1			T23	35		T24	123		T1	6015
all_pins[9]	transitions[0x0=>0x1]	781517	1			T23	12		T24	60		T1	3529
all_pins[9]	transitions[0x1=>0x0]	783163	1			T23	13		T24	112		T1	3648
all_pins[10]	values[0x0]	2140471	1			T23	46		T24	189		T25	1
all_pins[10]	values[0x1]	1312296	1			T23	57		T24	129		T1	6146
all_pins[10]	transitions[0x0=>0x1]	783826	1			T23	36		T24	81		T1	3664
all_pins[10]	transitions[0x1=>0x0]	780751	1			T23	14		T24	75		T1	3533
all_pins[11]	values[0x0]	2139732	1			T23	76		T24	206		T25	1
all_pins[11]	values[0x1]	1313035	1			T23	27		T24	112		T1	5919
all_pins[11]	transitions[0x0=>0x1]	784162	1			T23	15		T24	63		T1	3547
all_pins[11]	transitions[0x1=>0x0]	783423	1			T23	45		T24	80		T1	3774
all_pins[12]	values[0x0]	2148446	1			T23	60		T24	219		T25	1
all_pins[12]	values[0x1]	1304321	1			T23	43		T24	99		T1	6059
all_pins[12]	transitions[0x0=>0x1]	778245	1			T23	40		T24	76		T1	3663
all_pins[12]	transitions[0x1=>0x0]	786959	1			T23	24		T24	89		T1	3523
all_pins[13]	values[0x0]	2143535	1			T23	81		T24	224		T25	1
all_pins[13]	values[0x1]	1309232	1			T23	22		T24	94		T1	5842
all_pins[13]	transitions[0x0=>0x1]	785923	1			T23	10		T24	47		T1	3428
all_pins[13]	transitions[0x1=>0x0]	781012	1			T23	31		T24	52		T1	3645
all_pins[14]	values[0x0]	2143810	1			T23	76		T24	217		T25	1
all_pins[14]	values[0x1]	1308957	1			T23	27		T24	101		T1	5842
all_pins[14]	transitions[0x0=>0x1]	782373	1			T23	19		T24	72		T1	3607
all_pins[14]	transitions[0x1=>0x0]	782648	1			T23	14		T24	65		T1	3607
all_pins[15]	values[0x0]	2143314	1			T23	56		T24	186		T25	1
all_pins[15]	values[0x1]	1309453	1			T23	47		T24	132		T1	5900
all_pins[15]	transitions[0x0=>0x1]	782368	1			T23	34		T24	96		T1	3516
all_pins[15]	transitions[0x1=>0x0]	781872	1			T23	14		T24	65		T1	3458
all_pins[16]	values[0x0]	2146706	1			T23	73		T24	232		T25	1
all_pins[16]	values[0x1]	1306061	1			T23	30		T24	86		T1	5882
all_pins[16]	transitions[0x0=>0x1]	779199	1			T23	18		T24	44		T1	3519
all_pins[16]	transitions[0x1=>0x0]	782591	1			T23	35		T24	90		T1	3537
all_pins[17]	values[0x0]	2143897	1			T23	69		T24	260		T25	1
all_pins[17]	values[0x1]	1308870	1			T23	34		T24	58		T1	6004
all_pins[17]	transitions[0x0=>0x1]	784940	1			T23	27		T24	46		T1	3619
all_pins[17]	transitions[0x1=>0x0]	782131	1			T23	23		T24	74		T1	3497
all_pins[18]	values[0x0]	2147402	1			T23	60		T24	187		T25	1
all_pins[18]	values[0x1]	1305365	1			T23	43		T24	131		T1	6014
all_pins[18]	transitions[0x0=>0x1]	779381	1			T23	31		T24	110		T1	3498
all_pins[18]	transitions[0x1=>0x0]	782886	1			T23	22		T24	37		T1	3488
all_pins[19]	values[0x0]	2143455	1			T23	80		T24	168		T25	1
all_pins[19]	values[0x1]	1309312	1			T23	23		T24	150		T1	6065
all_pins[19]	transitions[0x0=>0x1]	784699	1			T23	8		T24	82		T1	3450
all_pins[19]	transitions[0x1=>0x0]	780752	1			T23	28		T24	63		T1	3399
all_pins[20]	values[0x0]	2143841	1			T23	64		T24	205		T25	1
all_pins[20]	values[0x1]	1308926	1			T23	39		T24	113		T1	5709
all_pins[20]	transitions[0x0=>0x1]	781690	1			T23	32		T24	72		T1	3304
all_pins[20]	transitions[0x1=>0x0]	782076	1			T23	16		T24	109		T1	3660
all_pins[21]	values[0x0]	2144117	1			T23	60		T24	211		T25	1
all_pins[21]	values[0x1]	1308650	1			T23	43		T24	107		T1	5751
all_pins[21]	transitions[0x0=>0x1]	783111	1			T23	32		T24	56		T1	3571
all_pins[21]	transitions[0x1=>0x0]	783387	1			T23	28		T24	62		T1	3529
all_pins[22]	values[0x0]	2143849	1			T23	67		T24	220		T25	1
all_pins[22]	values[0x1]	1308918	1			T23	36		T24	98		T1	5655
all_pins[22]	transitions[0x0=>0x1]	782242	1			T23	18		T24	53		T1	3422
all_pins[22]	transitions[0x1=>0x0]	781974	1			T23	25		T24	62		T1	3518
all_pins[23]	values[0x0]	2139669	1			T23	61		T24	223		T25	1
all_pins[23]	values[0x1]	1313098	1			T23	42		T24	95		T1	6045
all_pins[23]	transitions[0x0=>0x1]	784294	1			T23	31		T24	73		T1	3674
all_pins[23]	transitions[0x1=>0x0]	780114	1			T23	25		T24	76		T1	3284
all_pins[24]	values[0x0]	2147441	1			T23	55		T24	167		T25	1
all_pins[24]	values[0x1]	1305326	1			T23	48		T24	151		T1	5949
all_pins[24]	transitions[0x0=>0x1]	779554	1			T23	29		T24	120		T1	3449
all_pins[24]	transitions[0x1=>0x0]	787326	1			T23	23		T24	64		T1	3545
all_pins[25]	values[0x0]	2140867	1			T23	73		T24	219		T25	1
all_pins[25]	values[0x1]	1311900	1			T23	30		T24	99		T1	5880
all_pins[25]	transitions[0x0=>0x1]	785862	1			T23	15		T24	60		T1	3597
all_pins[25]	transitions[0x1=>0x0]	779288	1			T23	33		T24	112		T1	3666
all_pins[26]	values[0x0]	2149991	1			T23	63		T24	202		T25	1
all_pins[26]	values[0x1]	1302776	1			T23	40		T24	116		T1	5870
all_pins[26]	transitions[0x0=>0x1]	776871	1			T23	23		T24	87		T1	3464
all_pins[26]	transitions[0x1=>0x0]	785995	1			T23	13		T24	70		T1	3474
all_pins[27]	values[0x0]	2141189	1			T23	54		T24	184		T25	1
all_pins[27]	values[0x1]	1311578	1			T23	49		T24	134		T1	6085
all_pins[27]	transitions[0x0=>0x1]	785938	1			T23	31		T24	80		T1	3524
all_pins[27]	transitions[0x1=>0x0]	777136	1			T23	22		T24	62		T1	3309
all_pins[28]	values[0x0]	2143421	1			T23	49		T24	193		T25	1
all_pins[28]	values[0x1]	1309346	1			T23	54		T24	125		T1	5818
all_pins[28]	transitions[0x0=>0x1]	780938	1			T23	30		T24	58		T1	3491
all_pins[28]	transitions[0x1=>0x0]	783170	1			T23	25		T24	67		T1	3758
all_pins[29]	values[0x0]	2149031	1			T23	73		T24	170		T25	1
all_pins[29]	values[0x1]	1303736	1			T23	30		T24	148		T1	5920
all_pins[29]	transitions[0x0=>0x1]	781490	1			T23	17		T24	74		T1	3459
all_pins[29]	transitions[0x1=>0x0]	787100	1			T23	41		T24	51		T1	3357
all_pins[30]	values[0x0]	2143323	1			T23	57		T24	174		T25	1
all_pins[30]	values[0x1]	1309444	1			T23	46		T24	144		T1	5864
all_pins[30]	transitions[0x0=>0x1]	785874	1			T23	35		T24	74		T1	3496
all_pins[30]	transitions[0x1=>0x0]	780166	1			T23	19		T24	78		T1	3552
all_pins[31]	values[0x0]	2143263	1			T23	53		T24	194		T25	1
all_pins[31]	values[0x1]	1309504	1			T23	50		T24	124		T1	6210
all_pins[31]	transitions[0x0=>0x1]	783064	1			T23	23		T24	64		T1	3702
all_pins[31]	transitions[0x1=>0x0]	783004	1			T23	19		T24	84		T1	3356