Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[1]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[2]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[3]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[4]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[5]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[6]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[7]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[8]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[9]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[10]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[11]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[12]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[13]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[14]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[15]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[16]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[17]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[18]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[19]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[20]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[21]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[22]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[23]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[24]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[25]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[26]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[27]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[28]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[29]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[30]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[31]	11715961	1			T23	61		T24	710		T25	262

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

216361902

1

T23

965

T24

5085

T25

4843

auto[1]

158548850

1

T23

987

T24

17635

T25

3541

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

302420943

1

T23

1952

T24

14493

T25

7022

auto[1]

72489809

1

T24

8227

T25

1362

T1

366340

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

281433178

1

T23

1952

T24

11726

T25

7020

auto[1]

93477574

1

T24

10994

T25

1364

T1

479932

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4283413	1			T23	26		T24	24		T25	95
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3373795	1			T23	35		T24	248		T25	92
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1140520	1			T24	183		T25	15		T1	5736
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1336670	1			T24	11		T25	30		T1	8450
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	454214	1			T24	132		T1	618		T11	8393
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1127349	1			T24	112		T25	30		T1	5776
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4283138	1			T23	28		T24	18		T25	129
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3372041	1			T23	33		T24	212		T25	78
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1138990	1			T24	123		T25	27		T1	5767
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1338349	1			T24	16		T25	14		T1	8675
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	455497	1			T24	231		T1	693		T11	8292
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1127946	1			T24	110		T25	14		T1	5532
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4284716	1			T23	29		T24	20		T25	129
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3371106	1			T23	32		T24	279		T25	84
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1141015	1			T24	119		T25	14		T1	6014
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1337820	1			T24	5		T25	17		T1	8336
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	454503	1			T24	205		T1	635		T11	8184
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1126801	1			T24	82		T25	18		T1	5853
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4279251	1			T23	33		T24	21		T25	119
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3375192	1			T23	28		T24	191		T25	78
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1140981	1			T24	107		T25	22		T1	5495
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1338401	1			T24	10		T25	13		T1	8520
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	455729	1			T24	234		T1	605		T11	8188
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1126407	1			T24	147		T25	30		T1	6055
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4275902	1			T23	30		T24	11		T25	102
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3376342	1			T23	31		T24	175		T25	91
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1140497	1			T24	110		T25	6		T1	6160
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1338822	1			T24	20		T25	28		T1	8273
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	455896	1			T24	244		T1	595		T11	8402
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1128502	1			T24	150		T25	35		T1	5493
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4283506	1			T23	26		T24	4		T25	110
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3370400	1			T23	35		T24	252		T25	93
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1143986	1			T24	162		T25	16		T1	5505
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1338053	1			T24	13		T25	22		T1	8910
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	452100	1			T24	153		T1	611		T11	7976
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1127916	1			T24	126		T25	21		T1	5646
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4289179	1			T23	39		T24	18		T25	128
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3363191	1			T23	22		T24	183		T25	81
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1141236	1			T24	90		T25	10		T1	6079
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1336017	1			T24	10		T25	25		T1	8718
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	453818	1			T24	216		T1	647		T11	8498
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1132520	1			T24	193		T25	18		T1	5593
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4297442	1			T23	34		T24	8		T25	124
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3363613	1			T23	27		T24	184		T25	83
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1140948	1			T24	68		T25	12		T1	5344
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1337080	1			T24	32		T25	19		T1	9108
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	452533	1			T24	268		T1	647		T11	8034
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1124345	1			T24	150		T25	24		T1	5941
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4279364	1			T23	32		T24	19		T25	98
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3374757	1			T23	29		T24	304		T25	91
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1140278	1			T24	91		T25	30		T1	5733
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1336953	1			T24	15		T25	16		T1	8642
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	451980	1			T24	164		T1	640		T11	8199
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1132629	1			T24	117		T25	27		T1	5800
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4279932	1			T23	27		T24	13		T25	113
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3372364	1			T23	34		T24	276		T25	84
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1139193	1			T24	163		T25	25		T1	5809
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1339393	1			T24	4		T25	24		T1	8607
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	454869	1			T24	163		T1	632		T11	8055
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1130210	1			T24	91		T25	16		T1	6008
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4274987	1			T23	29		T24	10		T25	112
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3376372	1			T23	32		T24	263		T25	82
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1141541	1			T24	154		T25	24		T1	5598
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1338876	1			T24	13		T25	16		T1	8960
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	456947	1			T24	157		T1	677		T11	8417
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1127238	1			T24	113		T25	28		T1	5675
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4290908	1			T23	32		T24	6		T25	104
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3365807	1			T23	29		T24	163		T25	103
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1143045	1			T24	92		T25	15		T1	6033
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1331855	1			T24	24		T25	18		T1	8612
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	455443	1			T24	275		T1	688		T11	8433
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1128903	1			T24	150		T25	22		T1	5267
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4284638	1			T23	21		T24	13		T25	111
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3373306	1			T23	40		T24	241		T25	84
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1137544	1			T24	100		T25	31		T1	5825
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1338412	1			T24	9		T25	22		T1	8540
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	452570	1			T24	249		T1	609		T11	8520
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1129491	1			T24	98		T25	14		T1	5474
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4278247	1			T23	26		T24	15		T25	114
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3376576	1			T23	35		T24	178		T25	87
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1140907	1			T24	126		T25	21		T1	5727
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1337782	1			T24	12		T25	32		T1	9006
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	456079	1			T24	203		T1	714		T11	8207
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1126370	1			T24	176		T25	8		T1	5758
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4275251	1			T23	22		T24	13		T25	96
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3376537	1			T23	39		T24	244		T25	91
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1137234	1			T24	133		T25	12		T1	5821
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1341430	1			T24	13		T25	23		T1	8270
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	457190	1			T24	184		T1	579		T11	8127
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1128319	1			T24	123		T25	40		T1	5757
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4284535	1			T23	33		T24	16		T25	108
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3371193	1			T23	28		T24	249		T25	87
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1141048	1			T24	116		T25	35		T1	5522
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1334212	1			T24	9		T25	18		T1	8558
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	454166	1			T24	169		T1	589		T11	8040
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1130807	1			T24	151		T25	14		T1	6121
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4285789	1			T23	30		T24	20		T25	105
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3371344	1			T23	31		T24	210		T25	86
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1137635	1			T24	158		T25	19		T1	5554
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1339910	1			T24	8		T25	14		T1	8816
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	455544	1			T24	187		T1	634		T11	8340
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1125739	1			T24	127		T25	38		T1	5642
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4285509	1			T23	29		T24	15		T25	114
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3375686	1			T23	32		T24	188		T25	95
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1136294	1			T24	108		T25	29		T1	5705
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1337017	1			T24	18		T25	12		T1	8605
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	456418	1			T24	222		T1	645		T11	8197
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1125037	1			T24	159		T25	12		T1	5641
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4285812	1			T23	36		T24	5		T25	111
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3372647	1			T23	25		T24	185		T25	93
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1137590	1			T24	123		T25	10		T1	6003
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1335846	1			T24	16		T25	34		T1	8453
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	456019	1			T24	265		T1	564		T11	8337
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1128047	1			T24	116		T25	14		T1	5530
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4279620	1			T23	29		T24	9		T25	98
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3378848	1			T23	32		T24	187		T25	91
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1133752	1			T24	149		T25	33		T1	5706
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1343082	1			T24	19		T25	16		T1	8706
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	455258	1			T24	232		T1	670		T11	8195
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1125401	1			T24	114		T25	24		T1	5594
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4283139	1			T23	35		T24	9		T25	110
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3370478	1			T23	26		T24	242		T25	88
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1132399	1			T24	107		T25	20		T1	5513
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1343153	1			T24	18		T25	20		T1	9007
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	458701	1			T24	249		T1	672		T11	8051
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1128091	1			T24	85		T25	24		T1	5789
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4279556	1			T23	39		T24	12		T25	110
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3379017	1			T23	22		T24	207		T25	87
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1133976	1			T24	155		T25	30		T1	5535
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1339536	1			T24	11		T25	20		T1	8674
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	456321	1			T24	196		T1	721		T11	8405
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1127555	1			T24	129		T25	15		T1	6102
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4289632	1			T23	33		T24	15		T25	107
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3370999	1			T23	28		T24	221		T25	89
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1134034	1			T24	107		T25	14		T1	5829
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1343749	1			T24	7		T25	26		T1	8709
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	454367	1			T24	243		T1	728		T11	7757
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1123180	1			T24	117		T25	26		T1	5800
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4288577	1			T23	23		T24	20		T25	111
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3370383	1			T23	38		T24	223		T25	87
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1136305	1			T24	145		T25	8		T1	5748
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1339936	1			T24	7		T25	36		T1	8676
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	455271	1			T24	198		T1	602		T11	8162
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1125489	1			T24	117		T25	20		T1	5972
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4275319	1			T23	31		T24	13		T25	96
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3375363	1			T23	30		T24	206		T25	93
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1137139	1			T24	144		T25	25		T1	6124
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1341922	1			T24	11		T25	16		T1	8393
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	457546	1			T24	231		T1	580		T11	7733
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1128672	1			T24	105		T25	32		T1	5582
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4287304	1			T23	30		T24	12		T25	121
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3370491	1			T23	31		T24	210		T25	89
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1141900	1			T24	162		T25	16		T1	5993
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1336018	1			T24	19		T25	20		T1	8541
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	457877	1			T24	120		T1	596		T11	7931
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1122371	1			T24	187		T25	16		T1	5522
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4287872	1			T23	26		T24	16		T25	101
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3374199	1			T23	35		T24	232		T25	94
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1133165	1			T24	139		T25	28		T1	5868
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1339933	1			T24	10		T25	14		T1	8783
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	454872	1			T24	184		T1	636		T11	8092
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1125920	1			T24	129		T25	25		T1	5611
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4286927	1			T23	28		T24	16		T25	119
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3368121	1			T23	33		T24	291		T25	78
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1140436	1			T24	131		T25	22		T1	5613
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1338215	1			T24	10		T25	16		T1	8606
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	454586	1			T24	193		T1	583		T11	8405
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1127676	1			T24	69		T25	27		T1	5534
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4288400	1			T23	28		T24	32		T25	109
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3373243	1			T23	33		T24	225		T25	92
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1133344	1			T24	146		T25	21		T1	5771
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1339527	1			T24	2		T25	20		T1	8667
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	457736	1			T24	209		T1	548		T11	8156
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1123711	1			T24	96		T25	20		T1	5403
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4285085	1			T23	31		T24	14		T25	109
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3368847	1			T23	30		T24	180		T25	95
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1135986	1			T24	154		T25	22		T1	5749
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1341748	1			T24	17		T25	22		T1	8864
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	456121	1			T24	199		T1	609		T11	8151
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1128174	1			T24	146		T25	14		T1	5768
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4285587	1			T23	40		T24	6		T25	108
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3371061	1			T23	21		T24	234		T25	93
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1135987	1			T24	160		T25	18		T1	5661
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1343974	1			T24	18		T25	25		T1	8964
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	456548	1			T24	173		T1	640		T11	7978
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1122804	1			T24	119		T25	18		T1	5475
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4296853	1			T23	30		T24	11		T25	104
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3369970	1			T23	31		T24	186		T25	98
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1135594	1			T24	178		T25	28		T1	5703
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1338322	1			T24	21		T25	12		T1	8894
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	453532	1			T24	194		T1	685		T11	7791
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1121690	1			T24	120		T25	20		T1	5383

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal