Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[1]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[2]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[3]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[4]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[5]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[6]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[7]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[8]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[9]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[10]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[11]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[12]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[13]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[14]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[15]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[16]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[17]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[18]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[19]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[20]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[21]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[22]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[23]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[24]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[25]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[26]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[27]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[28]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[29]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[30]	11715961	1			T23	61		T24	710		T25	262
bins_for_gpio_bits[31]	11715961	1			T23	61		T24	710		T25	262

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

216361902

1

T23

965

T24

5085

T25

4843

auto[1]

158548850

1

T23

987

T24

17635

T25

3541

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

216355230

1

T23

965

T24

5095

T25

4837

auto[1]

158555522

1

T23

987

T24

17625

T25

3547

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	6559080	1			T23	26		T24	195		T25	135
bins_for_gpio_bits[0]	auto[0]	auto[1]	201303	1			T24	24		T25	5		T1	1012
bins_for_gpio_bits[0]	auto[1]	auto[0]	201523	1			T24	23		T25	5		T1	1020
bins_for_gpio_bits[0]	auto[1]	auto[1]	4754055	1			T23	35		T24	468		T25	117
bins_for_gpio_bits[1]	auto[0]	auto[0]	6558159	1			T23	28		T24	137		T25	167
bins_for_gpio_bits[1]	auto[0]	auto[1]	202114	1			T24	20		T25	3		T1	1004
bins_for_gpio_bits[1]	auto[1]	auto[0]	202318	1			T24	20		T25	3		T1	1010
bins_for_gpio_bits[1]	auto[1]	auto[1]	4753370	1			T23	33		T24	533		T25	89
bins_for_gpio_bits[2]	auto[0]	auto[0]	6561924	1			T23	29		T24	128		T25	157
bins_for_gpio_bits[2]	auto[0]	auto[1]	201416	1			T24	16		T25	3		T1	1042
bins_for_gpio_bits[2]	auto[1]	auto[0]	201627	1			T24	16		T25	3		T1	1048
bins_for_gpio_bits[2]	auto[1]	auto[1]	4750994	1			T23	32		T24	550		T25	99
bins_for_gpio_bits[3]	auto[0]	auto[0]	6556796	1			T23	33		T24	121		T25	150
bins_for_gpio_bits[3]	auto[0]	auto[1]	201652	1			T24	17		T25	4		T1	1017
bins_for_gpio_bits[3]	auto[1]	auto[0]	201837	1			T24	17		T25	4		T1	1026
bins_for_gpio_bits[3]	auto[1]	auto[1]	4755676	1			T23	28		T24	555		T25	104
bins_for_gpio_bits[4]	auto[0]	auto[0]	6553322	1			T23	30		T24	122		T25	130
bins_for_gpio_bits[4]	auto[0]	auto[1]	201673	1			T24	20		T25	5		T1	1003
bins_for_gpio_bits[4]	auto[1]	auto[0]	201899	1			T24	19		T25	6		T1	1007
bins_for_gpio_bits[4]	auto[1]	auto[1]	4759067	1			T23	31		T24	549		T25	121
bins_for_gpio_bits[5]	auto[0]	auto[0]	6563563	1			T23	26		T24	162		T25	144
bins_for_gpio_bits[5]	auto[0]	auto[1]	201762	1			T24	17		T25	3		T1	1008
bins_for_gpio_bits[5]	auto[1]	auto[0]	201982	1			T24	17		T25	4		T1	1014
bins_for_gpio_bits[5]	auto[1]	auto[1]	4748654	1			T23	35		T24	514		T25	111
bins_for_gpio_bits[6]	auto[0]	auto[0]	6564375	1			T23	39		T24	104		T25	158
bins_for_gpio_bits[6]	auto[0]	auto[1]	201834	1			T24	15		T25	5		T1	1030
bins_for_gpio_bits[6]	auto[1]	auto[0]	202057	1			T24	14		T25	5		T1	1037
bins_for_gpio_bits[6]	auto[1]	auto[1]	4747695	1			T23	22		T24	577		T25	94
bins_for_gpio_bits[7]	auto[0]	auto[0]	6574135	1			T23	34		T24	97		T25	151
bins_for_gpio_bits[7]	auto[0]	auto[1]	201148	1			T24	11		T25	4		T1	1040
bins_for_gpio_bits[7]	auto[1]	auto[0]	201335	1			T24	11		T25	4		T1	1046
bins_for_gpio_bits[7]	auto[1]	auto[1]	4739343	1			T23	27		T24	591		T25	103
bins_for_gpio_bits[8]	auto[0]	auto[0]	6554505	1			T23	32		T24	105		T25	138
bins_for_gpio_bits[8]	auto[0]	auto[1]	201875	1			T24	20		T25	5		T1	1019
bins_for_gpio_bits[8]	auto[1]	auto[0]	202090	1			T24	20		T25	6		T1	1024
bins_for_gpio_bits[8]	auto[1]	auto[1]	4757491	1			T23	29		T24	565		T25	113
bins_for_gpio_bits[9]	auto[0]	auto[0]	6556961	1			T23	27		T24	155		T25	156
bins_for_gpio_bits[9]	auto[0]	auto[1]	201349	1			T24	26		T25	6		T1	1041
bins_for_gpio_bits[9]	auto[1]	auto[0]	201557	1			T24	25		T25	6		T1	1045
bins_for_gpio_bits[9]	auto[1]	auto[1]	4756094	1			T23	34		T24	504		T25	94
bins_for_gpio_bits[10]	auto[0]	auto[0]	6553726	1			T23	29		T24	153		T25	146
bins_for_gpio_bits[10]	auto[0]	auto[1]	201445	1			T24	24		T25	6		T1	1026
bins_for_gpio_bits[10]	auto[1]	auto[0]	201678	1			T24	24		T25	6		T1	1034
bins_for_gpio_bits[10]	auto[1]	auto[1]	4759112	1			T23	32		T24	509		T25	104
bins_for_gpio_bits[11]	auto[0]	auto[0]	6564156	1			T23	32		T24	102		T25	130
bins_for_gpio_bits[11]	auto[0]	auto[1]	201486	1			T24	20		T25	7		T1	983
bins_for_gpio_bits[11]	auto[1]	auto[0]	201652	1			T24	20		T25	7		T1	983
bins_for_gpio_bits[11]	auto[1]	auto[1]	4748667	1			T23	29		T24	568		T25	118
bins_for_gpio_bits[12]	auto[0]	auto[0]	6558707	1			T23	21		T24	103		T25	160
bins_for_gpio_bits[12]	auto[0]	auto[1]	201682	1			T24	19		T25	4		T1	977
bins_for_gpio_bits[12]	auto[1]	auto[0]	201887	1			T24	19		T25	4		T1	984
bins_for_gpio_bits[12]	auto[1]	auto[1]	4753685	1			T23	40		T24	569		T25	94
bins_for_gpio_bits[13]	auto[0]	auto[0]	6555173	1			T23	26		T24	132		T25	164
bins_for_gpio_bits[13]	auto[0]	auto[1]	201584	1			T24	21		T25	3		T1	1000
bins_for_gpio_bits[13]	auto[1]	auto[0]	201763	1			T24	21		T25	3		T1	1004
bins_for_gpio_bits[13]	auto[1]	auto[1]	4757441	1			T23	35		T24	536		T25	92
bins_for_gpio_bits[14]	auto[0]	auto[0]	6551703	1			T23	22		T24	138		T25	126
bins_for_gpio_bits[14]	auto[0]	auto[1]	202027	1			T24	21		T25	5		T1	1003
bins_for_gpio_bits[14]	auto[1]	auto[0]	202212	1			T24	21		T25	5		T1	1009
bins_for_gpio_bits[14]	auto[1]	auto[1]	4760019	1			T23	39		T24	530		T25	126
bins_for_gpio_bits[15]	auto[0]	auto[0]	6558012	1			T23	33		T24	118		T25	157
bins_for_gpio_bits[15]	auto[0]	auto[1]	201538	1			T24	23		T25	4		T1	1013
bins_for_gpio_bits[15]	auto[1]	auto[0]	201783	1			T24	23		T25	4		T1	1016
bins_for_gpio_bits[15]	auto[1]	auto[1]	4754628	1			T23	28		T24	546		T25	97
bins_for_gpio_bits[16]	auto[0]	auto[0]	6561712	1			T23	30		T24	170		T25	132
bins_for_gpio_bits[16]	auto[0]	auto[1]	201413	1			T24	16		T25	6		T1	1016
bins_for_gpio_bits[16]	auto[1]	auto[0]	201622	1			T24	16		T25	6		T1	1023
bins_for_gpio_bits[16]	auto[1]	auto[1]	4751214	1			T23	31		T24	508		T25	118
bins_for_gpio_bits[17]	auto[0]	auto[0]	6556677	1			T23	29		T24	124		T25	151
bins_for_gpio_bits[17]	auto[0]	auto[1]	201917	1			T24	17		T25	4		T1	1030
bins_for_gpio_bits[17]	auto[1]	auto[0]	202143	1			T24	17		T25	4		T1	1036
bins_for_gpio_bits[17]	auto[1]	auto[1]	4755224	1			T23	32		T24	552		T25	103
bins_for_gpio_bits[18]	auto[0]	auto[0]	6557310	1			T23	36		T24	126		T25	152
bins_for_gpio_bits[18]	auto[0]	auto[1]	201707	1			T24	19		T25	3		T1	1034
bins_for_gpio_bits[18]	auto[1]	auto[0]	201938	1			T24	18		T25	3		T1	1038
bins_for_gpio_bits[18]	auto[1]	auto[1]	4755006	1			T23	25		T24	547		T25	104
bins_for_gpio_bits[19]	auto[0]	auto[0]	6554508	1			T23	29		T24	157		T25	140
bins_for_gpio_bits[19]	auto[0]	auto[1]	201725	1			T24	21		T25	7		T1	1003
bins_for_gpio_bits[19]	auto[1]	auto[0]	201946	1			T24	20		T25	7		T1	1012
bins_for_gpio_bits[19]	auto[1]	auto[1]	4757782	1			T23	32		T24	512		T25	108
bins_for_gpio_bits[20]	auto[0]	auto[0]	6556397	1			T23	35		T24	118		T25	144
bins_for_gpio_bits[20]	auto[0]	auto[1]	202074	1			T24	16		T25	6		T1	1010
bins_for_gpio_bits[20]	auto[1]	auto[0]	202294	1			T24	16		T25	6		T1	1016
bins_for_gpio_bits[20]	auto[1]	auto[1]	4755196	1			T23	26		T24	560		T25	106
bins_for_gpio_bits[21]	auto[0]	auto[0]	6550845	1			T23	39		T24	160		T25	153
bins_for_gpio_bits[21]	auto[0]	auto[1]	202006	1			T24	18		T25	6		T1	1038
bins_for_gpio_bits[21]	auto[1]	auto[0]	202223	1			T24	18		T25	7		T1	1043
bins_for_gpio_bits[21]	auto[1]	auto[1]	4760887	1			T23	22		T24	514		T25	96
bins_for_gpio_bits[22]	auto[0]	auto[0]	6565373	1			T23	33		T24	112		T25	141
bins_for_gpio_bits[22]	auto[0]	auto[1]	201850	1			T24	17		T25	6		T1	1071
bins_for_gpio_bits[22]	auto[1]	auto[0]	202042	1			T24	17		T25	6		T1	1077
bins_for_gpio_bits[22]	auto[1]	auto[1]	4746696	1			T23	28		T24	564		T25	109
bins_for_gpio_bits[23]	auto[0]	auto[0]	6563165	1			T23	23		T24	147		T25	150
bins_for_gpio_bits[23]	auto[0]	auto[1]	201445	1			T24	25		T25	5		T1	1049
bins_for_gpio_bits[23]	auto[1]	auto[0]	201653	1			T24	25		T25	5		T1	1059
bins_for_gpio_bits[23]	auto[1]	auto[1]	4749698	1			T23	38		T24	513		T25	102
bins_for_gpio_bits[24]	auto[0]	auto[0]	6552171	1			T23	31		T24	151		T25	131
bins_for_gpio_bits[24]	auto[0]	auto[1]	201985	1			T24	18		T25	6		T1	1022
bins_for_gpio_bits[24]	auto[1]	auto[0]	202209	1			T24	17		T25	6		T1	1024
bins_for_gpio_bits[24]	auto[1]	auto[1]	4759596	1			T23	30		T24	524		T25	119
bins_for_gpio_bits[25]	auto[0]	auto[0]	6563920	1			T23	30		T24	169		T25	152
bins_for_gpio_bits[25]	auto[0]	auto[1]	201105	1			T24	24		T25	5		T1	991
bins_for_gpio_bits[25]	auto[1]	auto[0]	201302	1			T24	24		T25	5		T1	997
bins_for_gpio_bits[25]	auto[1]	auto[1]	4749634	1			T23	31		T24	493		T25	100
bins_for_gpio_bits[26]	auto[0]	auto[0]	6558844	1			T23	26		T24	145		T25	137
bins_for_gpio_bits[26]	auto[0]	auto[1]	201937	1			T24	20		T25	5		T1	1058
bins_for_gpio_bits[26]	auto[1]	auto[0]	202126	1			T24	20		T25	6		T1	1061
bins_for_gpio_bits[26]	auto[1]	auto[1]	4753054	1			T23	35		T24	525		T25	114
bins_for_gpio_bits[27]	auto[0]	auto[0]	6563561	1			T23	28		T24	140		T25	150
bins_for_gpio_bits[27]	auto[0]	auto[1]	201789	1			T24	18		T25	6		T1	988
bins_for_gpio_bits[27]	auto[1]	auto[0]	202017	1			T24	17		T25	7		T1	994
bins_for_gpio_bits[27]	auto[1]	auto[1]	4748594	1			T23	33		T24	535		T25	99
bins_for_gpio_bits[28]	auto[0]	auto[0]	6560120	1			T23	28		T24	160		T25	146
bins_for_gpio_bits[28]	auto[0]	auto[1]	200973	1			T24	21		T25	4		T1	986
bins_for_gpio_bits[28]	auto[1]	auto[0]	201151	1			T24	20		T25	4		T1	992
bins_for_gpio_bits[28]	auto[1]	auto[1]	4753717	1			T23	33		T24	509		T25	108
bins_for_gpio_bits[29]	auto[0]	auto[0]	6561040	1			T23	31		T24	164		T25	150
bins_for_gpio_bits[29]	auto[0]	auto[1]	201554	1			T24	21		T25	3		T1	1021
bins_for_gpio_bits[29]	auto[1]	auto[0]	201779	1			T24	21		T25	3		T1	1022
bins_for_gpio_bits[29]	auto[1]	auto[1]	4751588	1			T23	30		T24	504		T25	106
bins_for_gpio_bits[30]	auto[0]	auto[0]	6564122	1			T23	40		T24	160		T25	145
bins_for_gpio_bits[30]	auto[0]	auto[1]	201248	1			T24	25		T25	6		T1	1009
bins_for_gpio_bits[30]	auto[1]	auto[0]	201426	1			T24	24		T25	6		T1	1016
bins_for_gpio_bits[30]	auto[1]	auto[1]	4749165	1			T23	21		T24	501		T25	105
bins_for_gpio_bits[31]	auto[0]	auto[0]	6569102	1			T23	30		T24	183		T25	138
bins_for_gpio_bits[31]	auto[0]	auto[1]	201450	1			T24	27		T25	6		T1	1021
bins_for_gpio_bits[31]	auto[1]	auto[0]	201667	1			T24	27		T25	6		T1	1023
bins_for_gpio_bits[31]	auto[1]	auto[1]	4743742	1			T23	31		T24	473		T25	112