Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7044563 |
1 |
|
|
T23 |
75 |
|
T24 |
284 |
|
T25 |
220 |
| auto[1] |
4878841 |
1 |
|
|
T23 |
68 |
|
T24 |
476 |
|
T1 |
24658 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11302258 |
1 |
|
|
T23 |
142 |
|
T24 |
740 |
|
T25 |
220 |
| auto[1] |
621146 |
1 |
|
|
T23 |
1 |
|
T24 |
20 |
|
T1 |
3198 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7047565 |
1 |
|
|
T23 |
84 |
|
T24 |
370 |
|
T25 |
220 |
| auto[1] |
4875839 |
1 |
|
|
T23 |
59 |
|
T24 |
390 |
|
T1 |
23589 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2118764 |
1 |
|
|
T23 |
27 |
|
T24 |
112 |
|
T1 |
10154 |
| auto[1] |
auto[0] |
auto[1] |
308395 |
1 |
|
|
T23 |
1 |
|
T24 |
3 |
|
T1 |
1587 |
| auto[1] |
auto[1] |
auto[0] |
2135929 |
1 |
|
|
T23 |
31 |
|
T24 |
258 |
|
T1 |
10237 |
| auto[1] |
auto[1] |
auto[1] |
312751 |
1 |
|
|
T24 |
17 |
|
T1 |
1611 |
|
T11 |
2479 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7008584 |
1 |
|
|
T23 |
57 |
|
T24 |
359 |
|
T25 |
220 |
| auto[1] |
4914820 |
1 |
|
|
T23 |
86 |
|
T24 |
401 |
|
T1 |
23539 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11294615 |
1 |
|
|
T23 |
138 |
|
T24 |
737 |
|
T25 |
220 |
| auto[1] |
628789 |
1 |
|
|
T23 |
5 |
|
T24 |
23 |
|
T1 |
2974 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7001217 |
1 |
|
|
T23 |
83 |
|
T24 |
346 |
|
T25 |
220 |
| auto[1] |
4922187 |
1 |
|
|
T23 |
60 |
|
T24 |
414 |
|
T1 |
22991 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2130278 |
1 |
|
|
T23 |
19 |
|
T24 |
188 |
|
T1 |
10278 |
| auto[1] |
auto[0] |
auto[1] |
312109 |
1 |
|
|
T23 |
4 |
|
T24 |
9 |
|
T1 |
1617 |
| auto[1] |
auto[1] |
auto[0] |
2163120 |
1 |
|
|
T23 |
36 |
|
T24 |
203 |
|
T1 |
9739 |
| auto[1] |
auto[1] |
auto[1] |
316680 |
1 |
|
|
T23 |
1 |
|
T24 |
14 |
|
T1 |
1357 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7002985 |
1 |
|
|
T23 |
50 |
|
T24 |
378 |
|
T25 |
220 |
| auto[1] |
4920419 |
1 |
|
|
T23 |
93 |
|
T24 |
382 |
|
T1 |
24202 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11300605 |
1 |
|
|
T23 |
142 |
|
T24 |
743 |
|
T25 |
220 |
| auto[1] |
622799 |
1 |
|
|
T23 |
1 |
|
T24 |
17 |
|
T1 |
3102 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7029475 |
1 |
|
|
T23 |
77 |
|
T24 |
434 |
|
T25 |
220 |
| auto[1] |
4893929 |
1 |
|
|
T23 |
66 |
|
T24 |
326 |
|
T1 |
23461 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2130131 |
1 |
|
|
T23 |
32 |
|
T24 |
120 |
|
T1 |
9917 |
| auto[1] |
auto[0] |
auto[1] |
310717 |
1 |
|
|
T23 |
1 |
|
T24 |
3 |
|
T1 |
1540 |
| auto[1] |
auto[1] |
auto[0] |
2140999 |
1 |
|
|
T23 |
33 |
|
T24 |
189 |
|
T1 |
10442 |
| auto[1] |
auto[1] |
auto[1] |
312082 |
1 |
|
|
T24 |
14 |
|
T1 |
1562 |
|
T11 |
2268 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6996800 |
1 |
|
|
T23 |
89 |
|
T24 |
363 |
|
T25 |
220 |
| auto[1] |
4926604 |
1 |
|
|
T23 |
54 |
|
T24 |
397 |
|
T1 |
22400 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11296933 |
1 |
|
|
T23 |
142 |
|
T24 |
743 |
|
T25 |
220 |
| auto[1] |
626471 |
1 |
|
|
T23 |
1 |
|
T24 |
17 |
|
T1 |
3126 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7015775 |
1 |
|
|
T23 |
118 |
|
T24 |
266 |
|
T25 |
220 |
| auto[1] |
4907629 |
1 |
|
|
T23 |
25 |
|
T24 |
494 |
|
T1 |
23716 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2141506 |
1 |
|
|
T23 |
17 |
|
T24 |
232 |
|
T1 |
11131 |
| auto[1] |
auto[0] |
auto[1] |
312507 |
1 |
|
|
T24 |
6 |
|
T1 |
1722 |
|
T11 |
2283 |
| auto[1] |
auto[1] |
auto[0] |
2139652 |
1 |
|
|
T23 |
7 |
|
T24 |
245 |
|
T1 |
9459 |
| auto[1] |
auto[1] |
auto[1] |
313964 |
1 |
|
|
T23 |
1 |
|
T24 |
11 |
|
T1 |
1404 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7064548 |
1 |
|
|
T23 |
67 |
|
T24 |
406 |
|
T25 |
220 |
| auto[1] |
4858856 |
1 |
|
|
T23 |
76 |
|
T24 |
354 |
|
T1 |
23335 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11299103 |
1 |
|
|
T23 |
139 |
|
T24 |
737 |
|
T25 |
220 |
| auto[1] |
624301 |
1 |
|
|
T23 |
4 |
|
T24 |
23 |
|
T1 |
3341 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7026580 |
1 |
|
|
T23 |
62 |
|
T24 |
260 |
|
T25 |
220 |
| auto[1] |
4896824 |
1 |
|
|
T23 |
81 |
|
T24 |
500 |
|
T1 |
25848 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2160663 |
1 |
|
|
T23 |
42 |
|
T24 |
265 |
|
T1 |
11259 |
| auto[1] |
auto[0] |
auto[1] |
317403 |
1 |
|
|
T23 |
3 |
|
T24 |
14 |
|
T1 |
1684 |
| auto[1] |
auto[1] |
auto[0] |
2111860 |
1 |
|
|
T23 |
35 |
|
T24 |
212 |
|
T1 |
11248 |
| auto[1] |
auto[1] |
auto[1] |
306898 |
1 |
|
|
T23 |
1 |
|
T24 |
9 |
|
T1 |
1657 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7025602 |
1 |
|
|
T23 |
87 |
|
T24 |
479 |
|
T25 |
220 |
| auto[1] |
4897802 |
1 |
|
|
T23 |
56 |
|
T24 |
281 |
|
T1 |
22718 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11294583 |
1 |
|
|
T23 |
140 |
|
T24 |
743 |
|
T25 |
220 |
| auto[1] |
628821 |
1 |
|
|
T23 |
3 |
|
T24 |
17 |
|
T1 |
3067 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6994181 |
1 |
|
|
T23 |
71 |
|
T24 |
336 |
|
T25 |
220 |
| auto[1] |
4929223 |
1 |
|
|
T23 |
72 |
|
T24 |
424 |
|
T1 |
23613 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2142835 |
1 |
|
|
T23 |
39 |
|
T24 |
238 |
|
T1 |
10488 |
| auto[1] |
auto[0] |
auto[1] |
312221 |
1 |
|
|
T23 |
2 |
|
T24 |
8 |
|
T1 |
1562 |
| auto[1] |
auto[1] |
auto[0] |
2157567 |
1 |
|
|
T23 |
30 |
|
T24 |
169 |
|
T1 |
10058 |
| auto[1] |
auto[1] |
auto[1] |
316600 |
1 |
|
|
T23 |
1 |
|
T24 |
9 |
|
T1 |
1505 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7040842 |
1 |
|
|
T23 |
91 |
|
T24 |
408 |
|
T25 |
220 |
| auto[1] |
4882562 |
1 |
|
|
T23 |
52 |
|
T24 |
352 |
|
T1 |
23514 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11306895 |
1 |
|
|
T23 |
140 |
|
T24 |
743 |
|
T25 |
220 |
| auto[1] |
616509 |
1 |
|
|
T23 |
3 |
|
T24 |
17 |
|
T1 |
3083 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7074179 |
1 |
|
|
T23 |
66 |
|
T24 |
367 |
|
T25 |
220 |
| auto[1] |
4849225 |
1 |
|
|
T23 |
77 |
|
T24 |
393 |
|
T1 |
23839 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2130856 |
1 |
|
|
T23 |
49 |
|
T24 |
207 |
|
T1 |
10075 |
| auto[1] |
auto[0] |
auto[1] |
310369 |
1 |
|
|
T24 |
9 |
|
T1 |
1548 |
|
T11 |
2298 |
| auto[1] |
auto[1] |
auto[0] |
2101860 |
1 |
|
|
T23 |
25 |
|
T24 |
169 |
|
T1 |
10681 |
| auto[1] |
auto[1] |
auto[1] |
306140 |
1 |
|
|
T23 |
3 |
|
T24 |
8 |
|
T1 |
1535 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7026343 |
1 |
|
|
T23 |
82 |
|
T24 |
406 |
|
T25 |
220 |
| auto[1] |
4897061 |
1 |
|
|
T23 |
61 |
|
T24 |
354 |
|
T1 |
24042 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11296852 |
1 |
|
|
T23 |
138 |
|
T24 |
750 |
|
T25 |
220 |
| auto[1] |
626552 |
1 |
|
|
T23 |
5 |
|
T24 |
10 |
|
T1 |
3206 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6999295 |
1 |
|
|
T23 |
44 |
|
T24 |
539 |
|
T25 |
220 |
| auto[1] |
4924109 |
1 |
|
|
T23 |
99 |
|
T24 |
221 |
|
T1 |
23794 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2141947 |
1 |
|
|
T23 |
44 |
|
T24 |
114 |
|
T1 |
10641 |
| auto[1] |
auto[0] |
auto[1] |
311773 |
1 |
|
|
T23 |
2 |
|
T24 |
7 |
|
T1 |
1709 |
| auto[1] |
auto[1] |
auto[0] |
2155610 |
1 |
|
|
T23 |
50 |
|
T24 |
97 |
|
T1 |
9947 |
| auto[1] |
auto[1] |
auto[1] |
314779 |
1 |
|
|
T23 |
3 |
|
T24 |
3 |
|
T1 |
1497 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7012049 |
1 |
|
|
T23 |
79 |
|
T24 |
451 |
|
T25 |
220 |
| auto[1] |
4911355 |
1 |
|
|
T23 |
64 |
|
T24 |
309 |
|
T1 |
24601 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11296476 |
1 |
|
|
T23 |
139 |
|
T24 |
745 |
|
T25 |
220 |
| auto[1] |
626928 |
1 |
|
|
T23 |
4 |
|
T24 |
15 |
|
T1 |
3166 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7007831 |
1 |
|
|
T23 |
76 |
|
T24 |
481 |
|
T25 |
220 |
| auto[1] |
4915573 |
1 |
|
|
T23 |
67 |
|
T24 |
279 |
|
T1 |
24012 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2135522 |
1 |
|
|
T23 |
31 |
|
T24 |
142 |
|
T1 |
10699 |
| auto[1] |
auto[0] |
auto[1] |
311155 |
1 |
|
|
T24 |
9 |
|
T1 |
1618 |
|
T11 |
2205 |
| auto[1] |
auto[1] |
auto[0] |
2153123 |
1 |
|
|
T23 |
32 |
|
T24 |
122 |
|
T1 |
10147 |
| auto[1] |
auto[1] |
auto[1] |
315773 |
1 |
|
|
T23 |
4 |
|
T24 |
6 |
|
T1 |
1548 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7020497 |
1 |
|
|
T23 |
86 |
|
T24 |
566 |
|
T25 |
220 |
| auto[1] |
4902907 |
1 |
|
|
T23 |
57 |
|
T24 |
194 |
|
T1 |
23239 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11294271 |
1 |
|
|
T23 |
136 |
|
T24 |
741 |
|
T25 |
220 |
| auto[1] |
629133 |
1 |
|
|
T23 |
7 |
|
T24 |
19 |
|
T1 |
3223 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7002447 |
1 |
|
|
T23 |
29 |
|
T24 |
322 |
|
T25 |
220 |
| auto[1] |
4920957 |
1 |
|
|
T23 |
114 |
|
T24 |
438 |
|
T1 |
25194 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2155501 |
1 |
|
|
T23 |
52 |
|
T24 |
329 |
|
T1 |
10968 |
| auto[1] |
auto[0] |
auto[1] |
317254 |
1 |
|
|
T23 |
5 |
|
T24 |
15 |
|
T1 |
1658 |
| auto[1] |
auto[1] |
auto[0] |
2136323 |
1 |
|
|
T23 |
55 |
|
T24 |
90 |
|
T1 |
11003 |
| auto[1] |
auto[1] |
auto[1] |
311879 |
1 |
|
|
T23 |
2 |
|
T24 |
4 |
|
T1 |
1565 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7052916 |
1 |
|
|
T23 |
60 |
|
T24 |
377 |
|
T25 |
220 |
| auto[1] |
4870488 |
1 |
|
|
T23 |
83 |
|
T24 |
383 |
|
T1 |
23707 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11297607 |
1 |
|
|
T23 |
139 |
|
T24 |
750 |
|
T25 |
220 |
| auto[1] |
625797 |
1 |
|
|
T23 |
4 |
|
T24 |
10 |
|
T1 |
3168 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7019945 |
1 |
|
|
T23 |
61 |
|
T24 |
507 |
|
T25 |
220 |
| auto[1] |
4903459 |
1 |
|
|
T23 |
82 |
|
T24 |
253 |
|
T1 |
24304 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2145666 |
1 |
|
|
T23 |
36 |
|
T24 |
94 |
|
T1 |
11057 |
| auto[1] |
auto[0] |
auto[1] |
314412 |
1 |
|
|
T23 |
1 |
|
T24 |
3 |
|
T1 |
1636 |
| auto[1] |
auto[1] |
auto[0] |
2131996 |
1 |
|
|
T23 |
42 |
|
T24 |
149 |
|
T1 |
10079 |
| auto[1] |
auto[1] |
auto[1] |
311385 |
1 |
|
|
T23 |
3 |
|
T24 |
7 |
|
T1 |
1532 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7035760 |
1 |
|
|
T23 |
93 |
|
T24 |
349 |
|
T25 |
220 |
| auto[1] |
4887644 |
1 |
|
|
T23 |
50 |
|
T24 |
411 |
|
T1 |
23493 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11303812 |
1 |
|
|
T23 |
139 |
|
T24 |
749 |
|
T25 |
220 |
| auto[1] |
619592 |
1 |
|
|
T23 |
4 |
|
T24 |
11 |
|
T1 |
3128 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7053741 |
1 |
|
|
T23 |
83 |
|
T24 |
459 |
|
T25 |
220 |
| auto[1] |
4869663 |
1 |
|
|
T23 |
60 |
|
T24 |
301 |
|
T1 |
24154 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2123999 |
1 |
|
|
T23 |
19 |
|
T24 |
152 |
|
T1 |
9964 |
| auto[1] |
auto[0] |
auto[1] |
310084 |
1 |
|
|
T23 |
1 |
|
T24 |
3 |
|
T1 |
1486 |
| auto[1] |
auto[1] |
auto[0] |
2126072 |
1 |
|
|
T23 |
37 |
|
T24 |
138 |
|
T1 |
11062 |
| auto[1] |
auto[1] |
auto[1] |
309508 |
1 |
|
|
T23 |
3 |
|
T24 |
8 |
|
T1 |
1642 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7015653 |
1 |
|
|
T23 |
85 |
|
T24 |
350 |
|
T25 |
220 |
| auto[1] |
4907751 |
1 |
|
|
T23 |
58 |
|
T24 |
410 |
|
T1 |
24057 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11299792 |
1 |
|
|
T23 |
139 |
|
T24 |
745 |
|
T25 |
220 |
| auto[1] |
623612 |
1 |
|
|
T23 |
4 |
|
T24 |
15 |
|
T1 |
3101 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7030685 |
1 |
|
|
T23 |
61 |
|
T24 |
421 |
|
T25 |
220 |
| auto[1] |
4892719 |
1 |
|
|
T23 |
82 |
|
T24 |
339 |
|
T1 |
24122 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2138667 |
1 |
|
|
T23 |
43 |
|
T24 |
131 |
|
T1 |
10156 |
| auto[1] |
auto[0] |
auto[1] |
312293 |
1 |
|
|
T23 |
3 |
|
T24 |
10 |
|
T1 |
1488 |
| auto[1] |
auto[1] |
auto[0] |
2130440 |
1 |
|
|
T23 |
35 |
|
T24 |
193 |
|
T1 |
10865 |
| auto[1] |
auto[1] |
auto[1] |
311319 |
1 |
|
|
T23 |
1 |
|
T24 |
5 |
|
T1 |
1613 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7014397 |
1 |
|
|
T23 |
63 |
|
T24 |
394 |
|
T25 |
220 |
| auto[1] |
4909007 |
1 |
|
|
T23 |
80 |
|
T24 |
366 |
|
T1 |
21683 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11293966 |
1 |
|
|
T23 |
140 |
|
T24 |
753 |
|
T25 |
220 |
| auto[1] |
629438 |
1 |
|
|
T23 |
3 |
|
T24 |
7 |
|
T1 |
2742 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6988871 |
1 |
|
|
T23 |
70 |
|
T24 |
317 |
|
T25 |
220 |
| auto[1] |
4934533 |
1 |
|
|
T23 |
73 |
|
T24 |
443 |
|
T1 |
21418 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2140461 |
1 |
|
|
T23 |
36 |
|
T24 |
251 |
|
T1 |
9906 |
| auto[1] |
auto[0] |
auto[1] |
312468 |
1 |
|
|
T23 |
1 |
|
T24 |
3 |
|
T1 |
1495 |
| auto[1] |
auto[1] |
auto[0] |
2164634 |
1 |
|
|
T23 |
34 |
|
T24 |
185 |
|
T1 |
8770 |
| auto[1] |
auto[1] |
auto[1] |
316970 |
1 |
|
|
T23 |
2 |
|
T24 |
4 |
|
T1 |
1247 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7028174 |
1 |
|
|
T23 |
77 |
|
T24 |
366 |
|
T25 |
220 |
| auto[1] |
4895230 |
1 |
|
|
T23 |
66 |
|
T24 |
394 |
|
T1 |
22575 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11299456 |
1 |
|
|
T23 |
140 |
|
T24 |
745 |
|
T25 |
220 |
| auto[1] |
623948 |
1 |
|
|
T23 |
3 |
|
T24 |
15 |
|
T1 |
2999 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7023506 |
1 |
|
|
T23 |
84 |
|
T24 |
426 |
|
T25 |
220 |
| auto[1] |
4899898 |
1 |
|
|
T23 |
59 |
|
T24 |
334 |
|
T1 |
23545 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2150814 |
1 |
|
|
T23 |
30 |
|
T24 |
133 |
|
T1 |
10604 |
| auto[1] |
auto[0] |
auto[1] |
314406 |
1 |
|
|
T23 |
1 |
|
T24 |
8 |
|
T1 |
1610 |
| auto[1] |
auto[1] |
auto[0] |
2125136 |
1 |
|
|
T23 |
26 |
|
T24 |
186 |
|
T1 |
9942 |
| auto[1] |
auto[1] |
auto[1] |
309542 |
1 |
|
|
T23 |
2 |
|
T24 |
7 |
|
T1 |
1389 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7053873 |
1 |
|
|
T23 |
55 |
|
T24 |
476 |
|
T25 |
220 |
| auto[1] |
4869531 |
1 |
|
|
T23 |
88 |
|
T24 |
284 |
|
T1 |
22387 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11299578 |
1 |
|
|
T23 |
141 |
|
T24 |
751 |
|
T25 |
220 |
| auto[1] |
623826 |
1 |
|
|
T23 |
2 |
|
T24 |
9 |
|
T1 |
3177 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7026608 |
1 |
|
|
T23 |
102 |
|
T24 |
515 |
|
T25 |
220 |
| auto[1] |
4896796 |
1 |
|
|
T23 |
41 |
|
T24 |
245 |
|
T1 |
23902 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2149229 |
1 |
|
|
T23 |
16 |
|
T24 |
146 |
|
T1 |
10591 |
| auto[1] |
auto[0] |
auto[1] |
314571 |
1 |
|
|
T23 |
2 |
|
T24 |
6 |
|
T1 |
1672 |
| auto[1] |
auto[1] |
auto[0] |
2123741 |
1 |
|
|
T23 |
23 |
|
T24 |
90 |
|
T1 |
10134 |
| auto[1] |
auto[1] |
auto[1] |
309255 |
1 |
|
|
T24 |
3 |
|
T1 |
1505 |
|
T11 |
2512 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7018411 |
1 |
|
|
T23 |
87 |
|
T24 |
430 |
|
T25 |
220 |
| auto[1] |
4904993 |
1 |
|
|
T23 |
56 |
|
T24 |
330 |
|
T1 |
24162 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11296297 |
1 |
|
|
T23 |
141 |
|
T24 |
740 |
|
T25 |
220 |
| auto[1] |
627107 |
1 |
|
|
T23 |
2 |
|
T24 |
20 |
|
T1 |
3101 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7012843 |
1 |
|
|
T23 |
93 |
|
T24 |
301 |
|
T25 |
220 |
| auto[1] |
4910561 |
1 |
|
|
T23 |
50 |
|
T24 |
459 |
|
T1 |
23468 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2130854 |
1 |
|
|
T23 |
26 |
|
T24 |
241 |
|
T1 |
9980 |
| auto[1] |
auto[0] |
auto[1] |
310992 |
1 |
|
|
T23 |
1 |
|
T24 |
14 |
|
T1 |
1488 |
| auto[1] |
auto[1] |
auto[0] |
2152600 |
1 |
|
|
T23 |
22 |
|
T24 |
198 |
|
T1 |
10387 |
| auto[1] |
auto[1] |
auto[1] |
316115 |
1 |
|
|
T23 |
1 |
|
T24 |
6 |
|
T1 |
1613 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7058128 |
1 |
|
|
T23 |
59 |
|
T24 |
303 |
|
T25 |
220 |
| auto[1] |
4865276 |
1 |
|
|
T23 |
84 |
|
T24 |
457 |
|
T1 |
24749 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11301296 |
1 |
|
|
T23 |
140 |
|
T24 |
750 |
|
T25 |
220 |
| auto[1] |
622108 |
1 |
|
|
T23 |
3 |
|
T24 |
10 |
|
T1 |
3419 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7040511 |
1 |
|
|
T23 |
105 |
|
T24 |
466 |
|
T25 |
220 |
| auto[1] |
4882893 |
1 |
|
|
T23 |
38 |
|
T24 |
294 |
|
T1 |
26095 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2152898 |
1 |
|
|
T23 |
11 |
|
T24 |
99 |
|
T1 |
10708 |
| auto[1] |
auto[0] |
auto[1] |
314669 |
1 |
|
|
T23 |
1 |
|
T24 |
1 |
|
T1 |
1606 |
| auto[1] |
auto[1] |
auto[0] |
2107887 |
1 |
|
|
T23 |
24 |
|
T24 |
185 |
|
T1 |
11968 |
| auto[1] |
auto[1] |
auto[1] |
307439 |
1 |
|
|
T23 |
2 |
|
T24 |
9 |
|
T1 |
1813 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7036697 |
1 |
|
|
T23 |
96 |
|
T24 |
523 |
|
T25 |
220 |
| auto[1] |
4886707 |
1 |
|
|
T23 |
47 |
|
T24 |
237 |
|
T1 |
22269 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11297070 |
1 |
|
|
T23 |
142 |
|
T24 |
733 |
|
T25 |
220 |
| auto[1] |
626334 |
1 |
|
|
T23 |
1 |
|
T24 |
27 |
|
T1 |
3260 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7006049 |
1 |
|
|
T23 |
88 |
|
T24 |
301 |
|
T25 |
220 |
| auto[1] |
4917355 |
1 |
|
|
T23 |
55 |
|
T24 |
459 |
|
T1 |
24642 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2145148 |
1 |
|
|
T23 |
26 |
|
T24 |
306 |
|
T1 |
11581 |
| auto[1] |
auto[0] |
auto[1] |
313473 |
1 |
|
|
T24 |
21 |
|
T1 |
1740 |
|
T11 |
2323 |
| auto[1] |
auto[1] |
auto[0] |
2145873 |
1 |
|
|
T23 |
28 |
|
T24 |
126 |
|
T1 |
9801 |
| auto[1] |
auto[1] |
auto[1] |
312861 |
1 |
|
|
T23 |
1 |
|
T24 |
6 |
|
T1 |
1520 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7069482 |
1 |
|
|
T23 |
72 |
|
T24 |
354 |
|
T25 |
220 |
| auto[1] |
4853922 |
1 |
|
|
T23 |
71 |
|
T24 |
406 |
|
T1 |
23031 |