Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7045185 |
1 |
|
|
T23 |
69 |
|
T24 |
306 |
|
T25 |
220 |
| auto[1] |
4878219 |
1 |
|
|
T23 |
74 |
|
T24 |
454 |
|
T1 |
22932 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11301066 |
1 |
|
|
T23 |
141 |
|
T24 |
747 |
|
T25 |
220 |
| auto[1] |
622338 |
1 |
|
|
T23 |
2 |
|
T24 |
13 |
|
T1 |
3028 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7045988 |
1 |
|
|
T23 |
103 |
|
T24 |
360 |
|
T25 |
220 |
| auto[1] |
4877416 |
1 |
|
|
T23 |
40 |
|
T24 |
400 |
|
T1 |
23319 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2147341 |
1 |
|
|
T23 |
14 |
|
T24 |
154 |
|
T1 |
10551 |
| auto[1] |
auto[0] |
auto[1] |
314884 |
1 |
|
|
T23 |
1 |
|
T24 |
5 |
|
T1 |
1527 |
| auto[1] |
auto[1] |
auto[0] |
2107737 |
1 |
|
|
T23 |
24 |
|
T24 |
233 |
|
T1 |
9740 |
| auto[1] |
auto[1] |
auto[1] |
307454 |
1 |
|
|
T23 |
1 |
|
T24 |
8 |
|
T1 |
1501 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |