Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7026749 |
1 |
|
|
T23 |
68 |
|
T24 |
302 |
|
T25 |
220 |
| auto[1] |
4896655 |
1 |
|
|
T23 |
75 |
|
T24 |
458 |
|
T1 |
24585 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11307060 |
1 |
|
|
T23 |
140 |
|
T24 |
750 |
|
T25 |
220 |
| auto[1] |
616344 |
1 |
|
|
T23 |
3 |
|
T24 |
10 |
|
T1 |
3034 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7075831 |
1 |
|
|
T23 |
58 |
|
T24 |
475 |
|
T25 |
220 |
| auto[1] |
4847573 |
1 |
|
|
T23 |
85 |
|
T24 |
285 |
|
T1 |
22813 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2128231 |
1 |
|
|
T23 |
40 |
|
T24 |
103 |
|
T1 |
9221 |
| auto[1] |
auto[0] |
auto[1] |
309566 |
1 |
|
|
T23 |
1 |
|
T24 |
7 |
|
T1 |
1321 |
| auto[1] |
auto[1] |
auto[0] |
2102998 |
1 |
|
|
T23 |
42 |
|
T24 |
172 |
|
T1 |
10558 |
| auto[1] |
auto[1] |
auto[1] |
306778 |
1 |
|
|
T23 |
2 |
|
T24 |
3 |
|
T1 |
1713 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |