Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7038399 |
1 |
|
|
T23 |
56 |
|
T24 |
300 |
|
T25 |
220 |
| auto[1] |
4885005 |
1 |
|
|
T23 |
87 |
|
T24 |
460 |
|
T1 |
23664 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11296881 |
1 |
|
|
T23 |
141 |
|
T24 |
746 |
|
T25 |
220 |
| auto[1] |
626523 |
1 |
|
|
T23 |
2 |
|
T24 |
14 |
|
T1 |
3068 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7015058 |
1 |
|
|
T23 |
79 |
|
T24 |
383 |
|
T25 |
220 |
| auto[1] |
4908346 |
1 |
|
|
T23 |
64 |
|
T24 |
377 |
|
T1 |
23143 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2154705 |
1 |
|
|
T23 |
18 |
|
T24 |
132 |
|
T1 |
10271 |
| auto[1] |
auto[0] |
auto[1] |
314641 |
1 |
|
|
T23 |
1 |
|
T24 |
4 |
|
T1 |
1550 |
| auto[1] |
auto[1] |
auto[0] |
2127118 |
1 |
|
|
T23 |
44 |
|
T24 |
231 |
|
T1 |
9804 |
| auto[1] |
auto[1] |
auto[1] |
311882 |
1 |
|
|
T23 |
1 |
|
T24 |
10 |
|
T1 |
1518 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |