Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7011771 |
1 |
|
|
T23 |
60 |
|
T24 |
298 |
|
T25 |
220 |
| auto[1] |
4911633 |
1 |
|
|
T23 |
83 |
|
T24 |
462 |
|
T1 |
24613 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11295396 |
1 |
|
|
T23 |
140 |
|
T24 |
733 |
|
T25 |
220 |
| auto[1] |
628008 |
1 |
|
|
T23 |
3 |
|
T24 |
27 |
|
T1 |
3342 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6999912 |
1 |
|
|
T23 |
75 |
|
T24 |
273 |
|
T25 |
220 |
| auto[1] |
4923492 |
1 |
|
|
T23 |
68 |
|
T24 |
487 |
|
T1 |
25262 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2152039 |
1 |
|
|
T23 |
30 |
|
T24 |
200 |
|
T1 |
10341 |
| auto[1] |
auto[0] |
auto[1] |
315722 |
1 |
|
|
T23 |
1 |
|
T24 |
10 |
|
T1 |
1598 |
| auto[1] |
auto[1] |
auto[0] |
2143445 |
1 |
|
|
T23 |
35 |
|
T24 |
260 |
|
T1 |
11579 |
| auto[1] |
auto[1] |
auto[1] |
312286 |
1 |
|
|
T23 |
2 |
|
T24 |
17 |
|
T1 |
1744 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |