Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7003182 |
1 |
|
|
T23 |
79 |
|
T24 |
337 |
|
T25 |
220 |
| auto[1] |
4920222 |
1 |
|
|
T23 |
64 |
|
T24 |
423 |
|
T1 |
24348 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11295826 |
1 |
|
|
T23 |
140 |
|
T24 |
744 |
|
T25 |
220 |
| auto[1] |
627578 |
1 |
|
|
T23 |
3 |
|
T24 |
16 |
|
T1 |
2956 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7007339 |
1 |
|
|
T23 |
94 |
|
T24 |
332 |
|
T25 |
220 |
| auto[1] |
4916065 |
1 |
|
|
T23 |
49 |
|
T24 |
428 |
|
T1 |
22394 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2128851 |
1 |
|
|
T23 |
29 |
|
T24 |
189 |
|
T1 |
9634 |
| auto[1] |
auto[0] |
auto[1] |
310421 |
1 |
|
|
T23 |
1 |
|
T24 |
9 |
|
T1 |
1495 |
| auto[1] |
auto[1] |
auto[0] |
2159636 |
1 |
|
|
T23 |
17 |
|
T24 |
223 |
|
T1 |
9804 |
| auto[1] |
auto[1] |
auto[1] |
317157 |
1 |
|
|
T23 |
2 |
|
T24 |
7 |
|
T1 |
1461 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |