Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7044563 |
1 |
|
|
T23 |
75 |
|
T24 |
284 |
|
T25 |
220 |
| auto[1] |
4878841 |
1 |
|
|
T23 |
68 |
|
T24 |
476 |
|
T1 |
24658 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9839764 |
1 |
|
|
T23 |
91 |
|
T24 |
484 |
|
T25 |
220 |
| auto[1] |
2083640 |
1 |
|
|
T23 |
52 |
|
T24 |
276 |
|
T1 |
9091 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7039335 |
1 |
|
|
T23 |
67 |
|
T24 |
365 |
|
T25 |
220 |
| auto[1] |
4884069 |
1 |
|
|
T23 |
76 |
|
T24 |
395 |
|
T1 |
23588 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1407000 |
1 |
|
|
T23 |
11 |
|
T24 |
53 |
|
T1 |
7029 |
| auto[1] |
auto[0] |
auto[1] |
1042862 |
1 |
|
|
T23 |
36 |
|
T24 |
68 |
|
T1 |
4492 |
| auto[1] |
auto[1] |
auto[0] |
1393429 |
1 |
|
|
T23 |
13 |
|
T24 |
66 |
|
T1 |
7468 |
| auto[1] |
auto[1] |
auto[1] |
1040778 |
1 |
|
|
T23 |
16 |
|
T24 |
208 |
|
T1 |
4599 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |