Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7008584 |
1 |
|
|
T23 |
57 |
|
T24 |
359 |
|
T25 |
220 |
| auto[1] |
4914820 |
1 |
|
|
T23 |
86 |
|
T24 |
401 |
|
T1 |
23539 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9824312 |
1 |
|
|
T23 |
99 |
|
T24 |
599 |
|
T25 |
220 |
| auto[1] |
2099092 |
1 |
|
|
T23 |
44 |
|
T24 |
161 |
|
T1 |
8714 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7008786 |
1 |
|
|
T23 |
41 |
|
T24 |
553 |
|
T25 |
220 |
| auto[1] |
4914618 |
1 |
|
|
T23 |
102 |
|
T24 |
207 |
|
T1 |
22510 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1397314 |
1 |
|
|
T23 |
18 |
|
T24 |
34 |
|
T1 |
7528 |
| auto[1] |
auto[0] |
auto[1] |
1048659 |
1 |
|
|
T23 |
29 |
|
T24 |
77 |
|
T1 |
4827 |
| auto[1] |
auto[1] |
auto[0] |
1418212 |
1 |
|
|
T23 |
40 |
|
T24 |
12 |
|
T1 |
6268 |
| auto[1] |
auto[1] |
auto[1] |
1050433 |
1 |
|
|
T23 |
15 |
|
T24 |
84 |
|
T1 |
3887 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |