Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7002985 |
1 |
|
|
T23 |
50 |
|
T24 |
378 |
|
T25 |
220 |
| auto[1] |
4920419 |
1 |
|
|
T23 |
93 |
|
T24 |
382 |
|
T1 |
24202 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9844404 |
1 |
|
|
T23 |
119 |
|
T24 |
456 |
|
T25 |
220 |
| auto[1] |
2079000 |
1 |
|
|
T23 |
24 |
|
T24 |
304 |
|
T1 |
9445 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7058622 |
1 |
|
|
T23 |
85 |
|
T24 |
371 |
|
T25 |
220 |
| auto[1] |
4864782 |
1 |
|
|
T23 |
58 |
|
T24 |
389 |
|
T1 |
24455 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1390755 |
1 |
|
|
T23 |
11 |
|
T24 |
31 |
|
T1 |
7175 |
| auto[1] |
auto[0] |
auto[1] |
1035862 |
1 |
|
|
T23 |
11 |
|
T24 |
169 |
|
T1 |
4715 |
| auto[1] |
auto[1] |
auto[0] |
1395027 |
1 |
|
|
T23 |
23 |
|
T24 |
54 |
|
T1 |
7835 |
| auto[1] |
auto[1] |
auto[1] |
1043138 |
1 |
|
|
T23 |
13 |
|
T24 |
135 |
|
T1 |
4730 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |