Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6996800 |
1 |
|
|
T23 |
89 |
|
T24 |
363 |
|
T25 |
220 |
| auto[1] |
4926604 |
1 |
|
|
T23 |
54 |
|
T24 |
397 |
|
T1 |
22400 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9836009 |
1 |
|
|
T23 |
102 |
|
T24 |
459 |
|
T25 |
220 |
| auto[1] |
2087395 |
1 |
|
|
T23 |
41 |
|
T24 |
301 |
|
T1 |
9384 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7040158 |
1 |
|
|
T23 |
61 |
|
T24 |
395 |
|
T25 |
220 |
| auto[1] |
4883246 |
1 |
|
|
T23 |
82 |
|
T24 |
365 |
|
T1 |
25295 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1391907 |
1 |
|
|
T23 |
29 |
|
T24 |
27 |
|
T1 |
9105 |
| auto[1] |
auto[0] |
auto[1] |
1036751 |
1 |
|
|
T23 |
22 |
|
T24 |
149 |
|
T1 |
5164 |
| auto[1] |
auto[1] |
auto[0] |
1403944 |
1 |
|
|
T23 |
12 |
|
T24 |
37 |
|
T1 |
6806 |
| auto[1] |
auto[1] |
auto[1] |
1050644 |
1 |
|
|
T23 |
19 |
|
T24 |
152 |
|
T1 |
4220 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |