Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7064548 |
1 |
|
|
T23 |
67 |
|
T24 |
406 |
|
T25 |
220 |
| auto[1] |
4858856 |
1 |
|
|
T23 |
76 |
|
T24 |
354 |
|
T1 |
23335 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9829386 |
1 |
|
|
T23 |
66 |
|
T24 |
444 |
|
T25 |
220 |
| auto[1] |
2094018 |
1 |
|
|
T23 |
77 |
|
T24 |
316 |
|
T1 |
9605 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7021714 |
1 |
|
|
T23 |
24 |
|
T24 |
386 |
|
T25 |
220 |
| auto[1] |
4901690 |
1 |
|
|
T23 |
119 |
|
T24 |
374 |
|
T1 |
24274 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1420307 |
1 |
|
|
T23 |
19 |
|
T24 |
23 |
|
T1 |
7571 |
| auto[1] |
auto[0] |
auto[1] |
1059116 |
1 |
|
|
T23 |
38 |
|
T24 |
165 |
|
T1 |
4683 |
| auto[1] |
auto[1] |
auto[0] |
1387365 |
1 |
|
|
T23 |
23 |
|
T24 |
35 |
|
T1 |
7098 |
| auto[1] |
auto[1] |
auto[1] |
1034902 |
1 |
|
|
T23 |
39 |
|
T24 |
151 |
|
T1 |
4922 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |