Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11304562 |
1 |
|
|
T23 |
139 |
|
T24 |
743 |
|
T25 |
220 |
| auto[1] |
618842 |
1 |
|
|
T23 |
4 |
|
T24 |
17 |
|
T1 |
2898 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7063785 |
1 |
|
|
T23 |
113 |
|
T24 |
303 |
|
T25 |
220 |
| auto[1] |
4859619 |
1 |
|
|
T23 |
30 |
|
T24 |
457 |
|
T1 |
22798 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2131961 |
1 |
|
|
T23 |
14 |
|
T24 |
231 |
|
T1 |
10030 |
| auto[1] |
auto[0] |
auto[1] |
312133 |
1 |
|
|
T23 |
4 |
|
T24 |
10 |
|
T1 |
1464 |
| auto[1] |
auto[1] |
auto[0] |
2108816 |
1 |
|
|
T23 |
12 |
|
T24 |
209 |
|
T1 |
9870 |
| auto[1] |
auto[1] |
auto[1] |
306709 |
1 |
|
|
T24 |
7 |
|
T1 |
1434 |
|
T11 |
2454 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |