Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7025602 |
1 |
|
|
T23 |
87 |
|
T24 |
479 |
|
T25 |
220 |
| auto[1] |
4897802 |
1 |
|
|
T23 |
56 |
|
T24 |
281 |
|
T1 |
22718 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9834834 |
1 |
|
|
T23 |
133 |
|
T24 |
591 |
|
T25 |
220 |
| auto[1] |
2088570 |
1 |
|
|
T23 |
10 |
|
T24 |
169 |
|
T1 |
9801 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7030604 |
1 |
|
|
T23 |
100 |
|
T24 |
548 |
|
T25 |
220 |
| auto[1] |
4892800 |
1 |
|
|
T23 |
43 |
|
T24 |
212 |
|
T1 |
25576 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1407638 |
1 |
|
|
T23 |
26 |
|
T24 |
34 |
|
T1 |
8639 |
| auto[1] |
auto[0] |
auto[1] |
1049126 |
1 |
|
|
T23 |
10 |
|
T24 |
134 |
|
T1 |
5254 |
| auto[1] |
auto[1] |
auto[0] |
1396592 |
1 |
|
|
T23 |
7 |
|
T24 |
9 |
|
T1 |
7136 |
| auto[1] |
auto[1] |
auto[1] |
1039444 |
1 |
|
|
T24 |
35 |
|
T1 |
4547 |
|
T11 |
9413 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |