Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7040842 |
1 |
|
|
T23 |
91 |
|
T24 |
408 |
|
T25 |
220 |
| auto[1] |
4882562 |
1 |
|
|
T23 |
52 |
|
T24 |
352 |
|
T1 |
23514 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9829245 |
1 |
|
|
T23 |
92 |
|
T24 |
566 |
|
T25 |
220 |
| auto[1] |
2094159 |
1 |
|
|
T23 |
51 |
|
T24 |
194 |
|
T1 |
9529 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7024404 |
1 |
|
|
T23 |
62 |
|
T24 |
504 |
|
T25 |
220 |
| auto[1] |
4899000 |
1 |
|
|
T23 |
81 |
|
T24 |
256 |
|
T1 |
24022 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1410917 |
1 |
|
|
T23 |
17 |
|
T24 |
39 |
|
T1 |
7073 |
| auto[1] |
auto[0] |
auto[1] |
1052841 |
1 |
|
|
T23 |
28 |
|
T24 |
61 |
|
T1 |
5019 |
| auto[1] |
auto[1] |
auto[0] |
1393924 |
1 |
|
|
T23 |
13 |
|
T24 |
23 |
|
T1 |
7420 |
| auto[1] |
auto[1] |
auto[1] |
1041318 |
1 |
|
|
T23 |
23 |
|
T24 |
133 |
|
T1 |
4510 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |