Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7026343 |
1 |
|
|
T23 |
82 |
|
T24 |
406 |
|
T25 |
220 |
| auto[1] |
4897061 |
1 |
|
|
T23 |
61 |
|
T24 |
354 |
|
T1 |
24042 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9828572 |
1 |
|
|
T23 |
96 |
|
T24 |
500 |
|
T25 |
220 |
| auto[1] |
2094832 |
1 |
|
|
T23 |
47 |
|
T24 |
260 |
|
T1 |
10047 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7017332 |
1 |
|
|
T23 |
38 |
|
T24 |
434 |
|
T25 |
220 |
| auto[1] |
4906072 |
1 |
|
|
T23 |
105 |
|
T24 |
326 |
|
T1 |
25128 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1406677 |
1 |
|
|
T23 |
30 |
|
T24 |
20 |
|
T1 |
7680 |
| auto[1] |
auto[0] |
auto[1] |
1049270 |
1 |
|
|
T23 |
26 |
|
T24 |
123 |
|
T1 |
5196 |
| auto[1] |
auto[1] |
auto[0] |
1404563 |
1 |
|
|
T23 |
28 |
|
T24 |
46 |
|
T1 |
7401 |
| auto[1] |
auto[1] |
auto[1] |
1045562 |
1 |
|
|
T23 |
21 |
|
T24 |
137 |
|
T1 |
4851 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |