Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7012049 |
1 |
|
|
T23 |
79 |
|
T24 |
451 |
|
T25 |
220 |
| auto[1] |
4911355 |
1 |
|
|
T23 |
64 |
|
T24 |
309 |
|
T1 |
24601 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9833275 |
1 |
|
|
T23 |
121 |
|
T24 |
403 |
|
T25 |
220 |
| auto[1] |
2090129 |
1 |
|
|
T23 |
22 |
|
T24 |
357 |
|
T1 |
10095 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7031522 |
1 |
|
|
T23 |
93 |
|
T24 |
276 |
|
T25 |
220 |
| auto[1] |
4891882 |
1 |
|
|
T23 |
50 |
|
T24 |
484 |
|
T1 |
25635 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1398398 |
1 |
|
|
T23 |
17 |
|
T24 |
104 |
|
T1 |
7543 |
| auto[1] |
auto[0] |
auto[1] |
1043883 |
1 |
|
|
T23 |
7 |
|
T24 |
215 |
|
T1 |
4732 |
| auto[1] |
auto[1] |
auto[0] |
1403355 |
1 |
|
|
T23 |
11 |
|
T24 |
23 |
|
T1 |
7997 |
| auto[1] |
auto[1] |
auto[1] |
1046246 |
1 |
|
|
T23 |
15 |
|
T24 |
142 |
|
T1 |
5363 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |