Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7020497 |
1 |
|
|
T23 |
86 |
|
T24 |
566 |
|
T25 |
220 |
| auto[1] |
4902907 |
1 |
|
|
T23 |
57 |
|
T24 |
194 |
|
T1 |
23239 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9827571 |
1 |
|
|
T23 |
77 |
|
T24 |
466 |
|
T25 |
220 |
| auto[1] |
2095833 |
1 |
|
|
T23 |
66 |
|
T24 |
294 |
|
T1 |
9958 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7010372 |
1 |
|
|
T23 |
40 |
|
T24 |
392 |
|
T25 |
220 |
| auto[1] |
4913032 |
1 |
|
|
T23 |
103 |
|
T24 |
368 |
|
T1 |
25876 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1403006 |
1 |
|
|
T23 |
20 |
|
T24 |
62 |
|
T1 |
7762 |
| auto[1] |
auto[0] |
auto[1] |
1046247 |
1 |
|
|
T23 |
31 |
|
T24 |
221 |
|
T1 |
5055 |
| auto[1] |
auto[1] |
auto[0] |
1414193 |
1 |
|
|
T23 |
17 |
|
T24 |
12 |
|
T1 |
8156 |
| auto[1] |
auto[1] |
auto[1] |
1049586 |
1 |
|
|
T23 |
35 |
|
T24 |
73 |
|
T1 |
4903 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |