Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7052916 |
1 |
|
|
T23 |
60 |
|
T24 |
377 |
|
T25 |
220 |
| auto[1] |
4870488 |
1 |
|
|
T23 |
83 |
|
T24 |
383 |
|
T1 |
23707 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9826424 |
1 |
|
|
T23 |
103 |
|
T24 |
415 |
|
T25 |
220 |
| auto[1] |
2096980 |
1 |
|
|
T23 |
40 |
|
T24 |
345 |
|
T1 |
8876 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7021645 |
1 |
|
|
T23 |
43 |
|
T24 |
337 |
|
T25 |
220 |
| auto[1] |
4901759 |
1 |
|
|
T23 |
100 |
|
T24 |
423 |
|
T1 |
22773 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1412711 |
1 |
|
|
T23 |
20 |
|
T24 |
22 |
|
T1 |
7276 |
| auto[1] |
auto[0] |
auto[1] |
1057217 |
1 |
|
|
T23 |
26 |
|
T24 |
152 |
|
T1 |
4533 |
| auto[1] |
auto[1] |
auto[0] |
1392068 |
1 |
|
|
T23 |
40 |
|
T24 |
56 |
|
T1 |
6621 |
| auto[1] |
auto[1] |
auto[1] |
1039763 |
1 |
|
|
T23 |
14 |
|
T24 |
193 |
|
T1 |
4343 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |