Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7035760 |
1 |
|
|
T23 |
93 |
|
T24 |
349 |
|
T25 |
220 |
| auto[1] |
4887644 |
1 |
|
|
T23 |
50 |
|
T24 |
411 |
|
T1 |
23493 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9829641 |
1 |
|
|
T23 |
101 |
|
T24 |
442 |
|
T25 |
220 |
| auto[1] |
2093763 |
1 |
|
|
T23 |
42 |
|
T24 |
318 |
|
T1 |
9028 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7021377 |
1 |
|
|
T23 |
56 |
|
T24 |
365 |
|
T25 |
220 |
| auto[1] |
4902027 |
1 |
|
|
T23 |
87 |
|
T24 |
395 |
|
T1 |
23697 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1409183 |
1 |
|
|
T23 |
39 |
|
T24 |
32 |
|
T1 |
7791 |
| auto[1] |
auto[0] |
auto[1] |
1053331 |
1 |
|
|
T23 |
36 |
|
T24 |
148 |
|
T1 |
4711 |
| auto[1] |
auto[1] |
auto[0] |
1399081 |
1 |
|
|
T23 |
6 |
|
T24 |
45 |
|
T1 |
6878 |
| auto[1] |
auto[1] |
auto[1] |
1040432 |
1 |
|
|
T23 |
6 |
|
T24 |
170 |
|
T1 |
4317 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |