Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7015653 |
1 |
|
|
T23 |
85 |
|
T24 |
350 |
|
T25 |
220 |
| auto[1] |
4907751 |
1 |
|
|
T23 |
58 |
|
T24 |
410 |
|
T1 |
24057 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9833960 |
1 |
|
|
T23 |
100 |
|
T24 |
403 |
|
T25 |
220 |
| auto[1] |
2089444 |
1 |
|
|
T23 |
43 |
|
T24 |
357 |
|
T1 |
8947 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7030076 |
1 |
|
|
T23 |
75 |
|
T24 |
312 |
|
T25 |
220 |
| auto[1] |
4893328 |
1 |
|
|
T23 |
68 |
|
T24 |
448 |
|
T1 |
23169 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1409511 |
1 |
|
|
T23 |
18 |
|
T24 |
27 |
|
T1 |
6956 |
| auto[1] |
auto[0] |
auto[1] |
1049150 |
1 |
|
|
T23 |
30 |
|
T24 |
171 |
|
T1 |
4398 |
| auto[1] |
auto[1] |
auto[0] |
1394373 |
1 |
|
|
T23 |
7 |
|
T24 |
64 |
|
T1 |
7266 |
| auto[1] |
auto[1] |
auto[1] |
1040294 |
1 |
|
|
T23 |
13 |
|
T24 |
186 |
|
T1 |
4549 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |