Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7014397 |
1 |
|
|
T23 |
63 |
|
T24 |
394 |
|
T25 |
220 |
| auto[1] |
4909007 |
1 |
|
|
T23 |
80 |
|
T24 |
366 |
|
T1 |
21683 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9832425 |
1 |
|
|
T23 |
102 |
|
T24 |
404 |
|
T25 |
220 |
| auto[1] |
2090979 |
1 |
|
|
T23 |
41 |
|
T24 |
356 |
|
T1 |
9292 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7033954 |
1 |
|
|
T23 |
38 |
|
T24 |
317 |
|
T25 |
220 |
| auto[1] |
4889450 |
1 |
|
|
T23 |
105 |
|
T24 |
443 |
|
T1 |
23178 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1401512 |
1 |
|
|
T23 |
39 |
|
T24 |
43 |
|
T1 |
7139 |
| auto[1] |
auto[0] |
auto[1] |
1048085 |
1 |
|
|
T23 |
10 |
|
T24 |
214 |
|
T1 |
4606 |
| auto[1] |
auto[1] |
auto[0] |
1396959 |
1 |
|
|
T23 |
25 |
|
T24 |
44 |
|
T1 |
6747 |
| auto[1] |
auto[1] |
auto[1] |
1042894 |
1 |
|
|
T23 |
31 |
|
T24 |
142 |
|
T1 |
4686 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |