Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7028174 |
1 |
|
|
T23 |
77 |
|
T24 |
366 |
|
T25 |
220 |
| auto[1] |
4895230 |
1 |
|
|
T23 |
66 |
|
T24 |
394 |
|
T1 |
22575 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9824784 |
1 |
|
|
T23 |
115 |
|
T24 |
458 |
|
T25 |
220 |
| auto[1] |
2098620 |
1 |
|
|
T23 |
28 |
|
T24 |
302 |
|
T1 |
9849 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7014884 |
1 |
|
|
T23 |
50 |
|
T24 |
330 |
|
T25 |
220 |
| auto[1] |
4908520 |
1 |
|
|
T23 |
93 |
|
T24 |
430 |
|
T1 |
25021 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1397153 |
1 |
|
|
T23 |
44 |
|
T24 |
40 |
|
T1 |
8762 |
| auto[1] |
auto[0] |
auto[1] |
1049363 |
1 |
|
|
T23 |
8 |
|
T24 |
147 |
|
T1 |
5468 |
| auto[1] |
auto[1] |
auto[0] |
1412747 |
1 |
|
|
T23 |
21 |
|
T24 |
88 |
|
T1 |
6410 |
| auto[1] |
auto[1] |
auto[1] |
1049257 |
1 |
|
|
T23 |
20 |
|
T24 |
155 |
|
T1 |
4381 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |