Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7026399 |
1 |
|
|
T23 |
61 |
|
T24 |
348 |
|
T25 |
220 |
| auto[1] |
4897005 |
1 |
|
|
T23 |
82 |
|
T24 |
412 |
|
T1 |
22850 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11298469 |
1 |
|
|
T23 |
141 |
|
T24 |
750 |
|
T25 |
220 |
| auto[1] |
624935 |
1 |
|
|
T23 |
2 |
|
T24 |
10 |
|
T1 |
3039 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7030834 |
1 |
|
|
T23 |
96 |
|
T24 |
409 |
|
T25 |
220 |
| auto[1] |
4892570 |
1 |
|
|
T23 |
47 |
|
T24 |
351 |
|
T1 |
23236 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2138076 |
1 |
|
|
T23 |
23 |
|
T24 |
167 |
|
T1 |
10395 |
| auto[1] |
auto[0] |
auto[1] |
313773 |
1 |
|
|
T23 |
1 |
|
T24 |
5 |
|
T1 |
1668 |
| auto[1] |
auto[1] |
auto[0] |
2129559 |
1 |
|
|
T23 |
22 |
|
T24 |
174 |
|
T1 |
9802 |
| auto[1] |
auto[1] |
auto[1] |
311162 |
1 |
|
|
T23 |
1 |
|
T24 |
5 |
|
T1 |
1371 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |