Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7053873 |
1 |
|
|
T23 |
55 |
|
T24 |
476 |
|
T25 |
220 |
| auto[1] |
4869531 |
1 |
|
|
T23 |
88 |
|
T24 |
284 |
|
T1 |
22387 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9844008 |
1 |
|
|
T23 |
109 |
|
T24 |
381 |
|
T25 |
220 |
| auto[1] |
2079396 |
1 |
|
|
T23 |
34 |
|
T24 |
379 |
|
T1 |
8821 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7048127 |
1 |
|
|
T23 |
86 |
|
T24 |
327 |
|
T25 |
220 |
| auto[1] |
4875277 |
1 |
|
|
T23 |
57 |
|
T24 |
433 |
|
T1 |
22162 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1412395 |
1 |
|
|
T23 |
10 |
|
T24 |
42 |
|
T1 |
7635 |
| auto[1] |
auto[0] |
auto[1] |
1044735 |
1 |
|
|
T23 |
14 |
|
T24 |
231 |
|
T1 |
5108 |
| auto[1] |
auto[1] |
auto[0] |
1383486 |
1 |
|
|
T23 |
13 |
|
T24 |
12 |
|
T1 |
5706 |
| auto[1] |
auto[1] |
auto[1] |
1034661 |
1 |
|
|
T23 |
20 |
|
T24 |
148 |
|
T1 |
3713 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |