Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7018411 |
1 |
|
|
T23 |
87 |
|
T24 |
430 |
|
T25 |
220 |
| auto[1] |
4904993 |
1 |
|
|
T23 |
56 |
|
T24 |
330 |
|
T1 |
24162 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9829646 |
1 |
|
|
T23 |
115 |
|
T24 |
422 |
|
T25 |
220 |
| auto[1] |
2093758 |
1 |
|
|
T23 |
28 |
|
T24 |
338 |
|
T1 |
9611 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7019290 |
1 |
|
|
T23 |
85 |
|
T24 |
359 |
|
T25 |
220 |
| auto[1] |
4904114 |
1 |
|
|
T23 |
58 |
|
T24 |
401 |
|
T1 |
24479 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1399396 |
1 |
|
|
T23 |
17 |
|
T24 |
32 |
|
T1 |
7480 |
| auto[1] |
auto[0] |
auto[1] |
1043475 |
1 |
|
|
T23 |
6 |
|
T24 |
163 |
|
T1 |
4839 |
| auto[1] |
auto[1] |
auto[0] |
1410960 |
1 |
|
|
T23 |
13 |
|
T24 |
31 |
|
T1 |
7388 |
| auto[1] |
auto[1] |
auto[1] |
1050283 |
1 |
|
|
T23 |
22 |
|
T24 |
175 |
|
T1 |
4772 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |