Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7058128 |
1 |
|
|
T23 |
59 |
|
T24 |
303 |
|
T25 |
220 |
| auto[1] |
4865276 |
1 |
|
|
T23 |
84 |
|
T24 |
457 |
|
T1 |
24749 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9828132 |
1 |
|
|
T23 |
126 |
|
T24 |
440 |
|
T25 |
220 |
| auto[1] |
2095272 |
1 |
|
|
T23 |
17 |
|
T24 |
320 |
|
T1 |
9529 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7022658 |
1 |
|
|
T23 |
85 |
|
T24 |
368 |
|
T25 |
220 |
| auto[1] |
4900746 |
1 |
|
|
T23 |
58 |
|
T24 |
392 |
|
T1 |
24574 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1417588 |
1 |
|
|
T23 |
11 |
|
T24 |
30 |
|
T1 |
7521 |
| auto[1] |
auto[0] |
auto[1] |
1052401 |
1 |
|
|
T23 |
4 |
|
T24 |
123 |
|
T1 |
4860 |
| auto[1] |
auto[1] |
auto[0] |
1387886 |
1 |
|
|
T23 |
30 |
|
T24 |
42 |
|
T1 |
7524 |
| auto[1] |
auto[1] |
auto[1] |
1042871 |
1 |
|
|
T23 |
13 |
|
T24 |
197 |
|
T1 |
4669 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |