Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7042943 |
1 |
|
|
T23 |
74 |
|
T24 |
327 |
|
T25 |
220 |
| auto[1] |
4880461 |
1 |
|
|
T23 |
69 |
|
T24 |
433 |
|
T1 |
23887 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11298907 |
1 |
|
|
T23 |
143 |
|
T24 |
748 |
|
T25 |
220 |
| auto[1] |
624497 |
1 |
|
|
T24 |
12 |
|
T1 |
3083 |
|
T11 |
4441 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7021723 |
1 |
|
|
T23 |
100 |
|
T24 |
406 |
|
T25 |
220 |
| auto[1] |
4901681 |
1 |
|
|
T23 |
43 |
|
T24 |
354 |
|
T1 |
23538 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2153125 |
1 |
|
|
T23 |
25 |
|
T24 |
132 |
|
T1 |
10807 |
| auto[1] |
auto[0] |
auto[1] |
314823 |
1 |
|
|
T24 |
3 |
|
T1 |
1666 |
|
T11 |
2255 |
| auto[1] |
auto[1] |
auto[0] |
2124059 |
1 |
|
|
T23 |
18 |
|
T24 |
210 |
|
T1 |
9648 |
| auto[1] |
auto[1] |
auto[1] |
309674 |
1 |
|
|
T24 |
9 |
|
T1 |
1417 |
|
T11 |
2186 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |