Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7025741 |
1 |
|
|
T23 |
76 |
|
T24 |
301 |
|
T25 |
220 |
| auto[1] |
4897663 |
1 |
|
|
T23 |
67 |
|
T24 |
459 |
|
T1 |
24468 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11301717 |
1 |
|
|
T23 |
140 |
|
T24 |
740 |
|
T25 |
220 |
| auto[1] |
621687 |
1 |
|
|
T23 |
3 |
|
T24 |
20 |
|
T1 |
3138 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7046597 |
1 |
|
|
T23 |
61 |
|
T24 |
323 |
|
T25 |
220 |
| auto[1] |
4876807 |
1 |
|
|
T23 |
82 |
|
T24 |
437 |
|
T1 |
24500 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2124850 |
1 |
|
|
T23 |
34 |
|
T24 |
165 |
|
T1 |
11078 |
| auto[1] |
auto[0] |
auto[1] |
310662 |
1 |
|
|
T23 |
2 |
|
T24 |
6 |
|
T1 |
1617 |
| auto[1] |
auto[1] |
auto[0] |
2130270 |
1 |
|
|
T23 |
45 |
|
T24 |
252 |
|
T1 |
10284 |
| auto[1] |
auto[1] |
auto[1] |
311025 |
1 |
|
|
T23 |
1 |
|
T24 |
14 |
|
T1 |
1521 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |