Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7041753 |
1 |
|
|
T23 |
55 |
|
T24 |
380 |
|
T25 |
220 |
| auto[1] |
4881651 |
1 |
|
|
T23 |
88 |
|
T24 |
380 |
|
T1 |
24039 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11301956 |
1 |
|
|
T23 |
141 |
|
T24 |
740 |
|
T25 |
220 |
| auto[1] |
621448 |
1 |
|
|
T23 |
2 |
|
T24 |
20 |
|
T1 |
3324 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7045249 |
1 |
|
|
T23 |
74 |
|
T24 |
432 |
|
T25 |
220 |
| auto[1] |
4878155 |
1 |
|
|
T23 |
69 |
|
T24 |
328 |
|
T1 |
24660 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2143357 |
1 |
|
|
T23 |
20 |
|
T24 |
164 |
|
T1 |
11070 |
| auto[1] |
auto[0] |
auto[1] |
313027 |
1 |
|
|
T24 |
11 |
|
T1 |
1796 |
|
T11 |
2323 |
| auto[1] |
auto[1] |
auto[0] |
2113350 |
1 |
|
|
T23 |
47 |
|
T24 |
144 |
|
T1 |
10266 |
| auto[1] |
auto[1] |
auto[1] |
308421 |
1 |
|
|
T23 |
2 |
|
T24 |
9 |
|
T1 |
1528 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |