Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7052623 |
1 |
|
|
T23 |
82 |
|
T24 |
400 |
|
T25 |
220 |
| auto[1] |
4870781 |
1 |
|
|
T23 |
61 |
|
T24 |
360 |
|
T1 |
24662 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11304596 |
1 |
|
|
T23 |
140 |
|
T24 |
738 |
|
T25 |
220 |
| auto[1] |
618808 |
1 |
|
|
T23 |
3 |
|
T24 |
22 |
|
T1 |
3199 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7063675 |
1 |
|
|
T23 |
105 |
|
T24 |
341 |
|
T25 |
220 |
| auto[1] |
4859729 |
1 |
|
|
T23 |
38 |
|
T24 |
419 |
|
T1 |
24277 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2142594 |
1 |
|
|
T23 |
19 |
|
T24 |
194 |
|
T1 |
11076 |
| auto[1] |
auto[0] |
auto[1] |
312915 |
1 |
|
|
T23 |
2 |
|
T24 |
10 |
|
T1 |
1612 |
| auto[1] |
auto[1] |
auto[0] |
2098327 |
1 |
|
|
T23 |
16 |
|
T24 |
203 |
|
T1 |
10002 |
| auto[1] |
auto[1] |
auto[1] |
305893 |
1 |
|
|
T23 |
1 |
|
T24 |
12 |
|
T1 |
1587 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |