Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 938
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T764 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1508687955 Jun 13 12:43:43 PM PDT 24 Jun 13 12:43:44 PM PDT 24 61646086 ps
T765 /workspace/coverage/cover_reg_top/17.gpio_intr_test.1837504521 Jun 13 12:44:29 PM PDT 24 Jun 13 12:44:30 PM PDT 24 12706690 ps
T766 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1776002576 Jun 13 12:44:15 PM PDT 24 Jun 13 12:44:16 PM PDT 24 120269508 ps
T84 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1126103954 Jun 13 12:44:30 PM PDT 24 Jun 13 12:44:31 PM PDT 24 169063277 ps
T95 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3611295343 Jun 13 12:44:17 PM PDT 24 Jun 13 12:44:18 PM PDT 24 19206786 ps
T85 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1667626368 Jun 13 12:43:53 PM PDT 24 Jun 13 12:43:54 PM PDT 24 55497818 ps
T96 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1138250721 Jun 13 12:44:09 PM PDT 24 Jun 13 12:44:10 PM PDT 24 122359413 ps
T767 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.3147335042 Jun 13 12:44:24 PM PDT 24 Jun 13 12:44:25 PM PDT 24 12320735 ps
T768 /workspace/coverage/cover_reg_top/8.gpio_intr_test.3469596461 Jun 13 12:44:09 PM PDT 24 Jun 13 12:44:10 PM PDT 24 12167610 ps
T769 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2257450524 Jun 13 12:43:48 PM PDT 24 Jun 13 12:43:52 PM PDT 24 255415886 ps
T770 /workspace/coverage/cover_reg_top/48.gpio_intr_test.2708992206 Jun 13 12:44:56 PM PDT 24 Jun 13 12:44:57 PM PDT 24 11770203 ps
T97 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2590459109 Jun 13 12:44:08 PM PDT 24 Jun 13 12:44:10 PM PDT 24 72226594 ps
T98 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3575441940 Jun 13 12:44:18 PM PDT 24 Jun 13 12:44:19 PM PDT 24 70862036 ps
T771 /workspace/coverage/cover_reg_top/47.gpio_intr_test.2331350012 Jun 13 12:44:43 PM PDT 24 Jun 13 12:44:45 PM PDT 24 14233752 ps
T772 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.499377240 Jun 13 12:44:22 PM PDT 24 Jun 13 12:44:24 PM PDT 24 93512315 ps
T86 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2443444976 Jun 13 12:44:28 PM PDT 24 Jun 13 12:44:29 PM PDT 24 14914718 ps
T773 /workspace/coverage/cover_reg_top/11.gpio_intr_test.840303459 Jun 13 12:44:22 PM PDT 24 Jun 13 12:44:23 PM PDT 24 26106055 ps
T774 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.1967245577 Jun 13 12:43:57 PM PDT 24 Jun 13 12:43:58 PM PDT 24 200016033 ps
T775 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.654178218 Jun 13 12:44:07 PM PDT 24 Jun 13 12:44:10 PM PDT 24 544895395 ps
T776 /workspace/coverage/cover_reg_top/0.gpio_intr_test.3286990423 Jun 13 12:43:49 PM PDT 24 Jun 13 12:43:50 PM PDT 24 12257092 ps
T777 /workspace/coverage/cover_reg_top/46.gpio_intr_test.959267175 Jun 13 12:44:42 PM PDT 24 Jun 13 12:44:43 PM PDT 24 20003979 ps
T778 /workspace/coverage/cover_reg_top/12.gpio_intr_test.1171542292 Jun 13 12:44:15 PM PDT 24 Jun 13 12:44:17 PM PDT 24 45843865 ps
T779 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2747119461 Jun 13 12:43:37 PM PDT 24 Jun 13 12:43:38 PM PDT 24 52277983 ps
T780 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.1180244240 Jun 13 12:43:47 PM PDT 24 Jun 13 12:43:48 PM PDT 24 57305826 ps
T42 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3573836221 Jun 13 12:44:21 PM PDT 24 Jun 13 12:44:22 PM PDT 24 48005191 ps
T781 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.1780251572 Jun 13 12:44:26 PM PDT 24 Jun 13 12:44:28 PM PDT 24 90534587 ps
T782 /workspace/coverage/cover_reg_top/31.gpio_intr_test.3391251323 Jun 13 12:44:44 PM PDT 24 Jun 13 12:44:46 PM PDT 24 21297776 ps
T783 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.456304933 Jun 13 12:44:17 PM PDT 24 Jun 13 12:44:20 PM PDT 24 126489245 ps
T43 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2832313566 Jun 13 12:44:07 PM PDT 24 Jun 13 12:44:08 PM PDT 24 90733893 ps
T784 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.369759448 Jun 13 12:44:18 PM PDT 24 Jun 13 12:44:20 PM PDT 24 33666471 ps
T785 /workspace/coverage/cover_reg_top/13.gpio_intr_test.216025859 Jun 13 12:44:16 PM PDT 24 Jun 13 12:44:18 PM PDT 24 31772236 ps
T786 /workspace/coverage/cover_reg_top/14.gpio_intr_test.628608995 Jun 13 12:44:24 PM PDT 24 Jun 13 12:44:25 PM PDT 24 31252495 ps
T787 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.529981048 Jun 13 12:44:24 PM PDT 24 Jun 13 12:44:27 PM PDT 24 230184634 ps
T788 /workspace/coverage/cover_reg_top/49.gpio_intr_test.3384033071 Jun 13 12:44:55 PM PDT 24 Jun 13 12:44:56 PM PDT 24 114543582 ps
T789 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.2662904348 Jun 13 12:44:15 PM PDT 24 Jun 13 12:44:16 PM PDT 24 15611538 ps
T790 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3441645849 Jun 13 12:44:35 PM PDT 24 Jun 13 12:44:37 PM PDT 24 46754539 ps
T791 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.3996405584 Jun 13 12:44:23 PM PDT 24 Jun 13 12:44:25 PM PDT 24 126919533 ps
T792 /workspace/coverage/cover_reg_top/9.gpio_intr_test.1087082690 Jun 13 12:44:09 PM PDT 24 Jun 13 12:44:10 PM PDT 24 37997876 ps
T793 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.941630034 Jun 13 12:44:33 PM PDT 24 Jun 13 12:44:35 PM PDT 24 123458180 ps
T794 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.3277614561 Jun 13 12:44:28 PM PDT 24 Jun 13 12:44:30 PM PDT 24 274557049 ps
T795 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1649384646 Jun 13 12:44:39 PM PDT 24 Jun 13 12:44:40 PM PDT 24 60586690 ps
T796 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1295173990 Jun 13 12:44:28 PM PDT 24 Jun 13 12:44:30 PM PDT 24 145582231 ps
T797 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.3570264672 Jun 13 12:44:08 PM PDT 24 Jun 13 12:44:11 PM PDT 24 178107689 ps
T798 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2332525468 Jun 13 12:43:54 PM PDT 24 Jun 13 12:43:55 PM PDT 24 82604099 ps
T799 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1495822674 Jun 13 12:44:36 PM PDT 24 Jun 13 12:44:38 PM PDT 24 109068687 ps
T800 /workspace/coverage/cover_reg_top/30.gpio_intr_test.2815430920 Jun 13 12:44:42 PM PDT 24 Jun 13 12:44:43 PM PDT 24 19208886 ps
T801 /workspace/coverage/cover_reg_top/5.gpio_intr_test.3938170180 Jun 13 12:44:03 PM PDT 24 Jun 13 12:44:04 PM PDT 24 47174751 ps
T87 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2505936692 Jun 13 12:43:48 PM PDT 24 Jun 13 12:43:49 PM PDT 24 25140835 ps
T802 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.2490027664 Jun 13 12:44:02 PM PDT 24 Jun 13 12:44:03 PM PDT 24 87016367 ps
T803 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2031314979 Jun 13 12:43:48 PM PDT 24 Jun 13 12:43:49 PM PDT 24 59527306 ps
T804 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2294382610 Jun 13 12:43:50 PM PDT 24 Jun 13 12:43:51 PM PDT 24 40048966 ps
T805 /workspace/coverage/cover_reg_top/20.gpio_intr_test.2973459581 Jun 13 12:44:35 PM PDT 24 Jun 13 12:44:36 PM PDT 24 12816215 ps
T806 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3976444881 Jun 13 12:43:41 PM PDT 24 Jun 13 12:43:43 PM PDT 24 285697876 ps
T807 /workspace/coverage/cover_reg_top/7.gpio_intr_test.2792602743 Jun 13 12:44:13 PM PDT 24 Jun 13 12:44:14 PM PDT 24 19948795 ps
T808 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.990595287 Jun 13 12:43:55 PM PDT 24 Jun 13 12:43:57 PM PDT 24 117772853 ps
T88 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2531757619 Jun 13 12:43:42 PM PDT 24 Jun 13 12:43:43 PM PDT 24 12493389 ps
T89 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.3029145133 Jun 13 12:43:58 PM PDT 24 Jun 13 12:44:01 PM PDT 24 324341289 ps
T809 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.470224862 Jun 13 12:43:56 PM PDT 24 Jun 13 12:43:57 PM PDT 24 125787679 ps
T810 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.544330171 Jun 13 12:43:50 PM PDT 24 Jun 13 12:43:51 PM PDT 24 18723837 ps
T811 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.342195161 Jun 13 12:43:49 PM PDT 24 Jun 13 12:43:50 PM PDT 24 15247077 ps
T812 /workspace/coverage/cover_reg_top/40.gpio_intr_test.2041690848 Jun 13 12:44:44 PM PDT 24 Jun 13 12:44:46 PM PDT 24 14161546 ps
T813 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.251161087 Jun 13 12:44:03 PM PDT 24 Jun 13 12:44:04 PM PDT 24 35661304 ps
T814 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1724516699 Jun 13 12:44:16 PM PDT 24 Jun 13 12:44:17 PM PDT 24 17677267 ps
T815 /workspace/coverage/cover_reg_top/37.gpio_intr_test.388013849 Jun 13 12:44:56 PM PDT 24 Jun 13 12:44:57 PM PDT 24 13103536 ps
T816 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1000780406 Jun 13 12:44:11 PM PDT 24 Jun 13 12:44:13 PM PDT 24 810361522 ps
T817 /workspace/coverage/cover_reg_top/26.gpio_intr_test.3853886469 Jun 13 12:44:42 PM PDT 24 Jun 13 12:44:43 PM PDT 24 14708777 ps
T818 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.706664749 Jun 13 12:44:28 PM PDT 24 Jun 13 12:44:30 PM PDT 24 19176325 ps
T90 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.415248837 Jun 13 12:44:30 PM PDT 24 Jun 13 12:44:31 PM PDT 24 18113598 ps
T819 /workspace/coverage/cover_reg_top/41.gpio_intr_test.2554106655 Jun 13 12:44:43 PM PDT 24 Jun 13 12:44:44 PM PDT 24 13230541 ps
T820 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2048244919 Jun 13 12:44:21 PM PDT 24 Jun 13 12:44:22 PM PDT 24 34563123 ps
T821 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3300882988 Jun 13 12:43:50 PM PDT 24 Jun 13 12:43:52 PM PDT 24 352828879 ps
T822 /workspace/coverage/cover_reg_top/39.gpio_intr_test.2923982086 Jun 13 12:44:43 PM PDT 24 Jun 13 12:44:45 PM PDT 24 17922146 ps
T823 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2304174000 Jun 13 12:44:23 PM PDT 24 Jun 13 12:44:25 PM PDT 24 124921194 ps
T824 /workspace/coverage/cover_reg_top/19.gpio_intr_test.1457250126 Jun 13 12:44:35 PM PDT 24 Jun 13 12:44:36 PM PDT 24 20444962 ps
T825 /workspace/coverage/cover_reg_top/24.gpio_intr_test.949213062 Jun 13 12:44:44 PM PDT 24 Jun 13 12:44:45 PM PDT 24 49210024 ps
T826 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.2699263902 Jun 13 12:44:02 PM PDT 24 Jun 13 12:44:03 PM PDT 24 16909269 ps
T827 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.450452702 Jun 13 12:44:30 PM PDT 24 Jun 13 12:44:32 PM PDT 24 63604620 ps
T828 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1638649716 Jun 13 12:44:28 PM PDT 24 Jun 13 12:44:30 PM PDT 24 92911097 ps
T829 /workspace/coverage/cover_reg_top/28.gpio_intr_test.3344426557 Jun 13 12:44:57 PM PDT 24 Jun 13 12:44:58 PM PDT 24 13620796 ps
T830 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1846143529 Jun 13 12:43:57 PM PDT 24 Jun 13 12:44:00 PM PDT 24 325314434 ps
T831 /workspace/coverage/cover_reg_top/21.gpio_intr_test.712673027 Jun 13 12:44:34 PM PDT 24 Jun 13 12:44:35 PM PDT 24 22273292 ps
T832 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3999896587 Jun 13 12:44:39 PM PDT 24 Jun 13 12:44:40 PM PDT 24 115869626 ps
T833 /workspace/coverage/cover_reg_top/33.gpio_intr_test.2148463836 Jun 13 12:44:42 PM PDT 24 Jun 13 12:44:44 PM PDT 24 28113157 ps
T834 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.493876290 Jun 13 12:44:00 PM PDT 24 Jun 13 12:44:02 PM PDT 24 85379403 ps
T835 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.3032516752 Jun 13 12:43:57 PM PDT 24 Jun 13 12:43:58 PM PDT 24 62605656 ps
T836 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3539949766 Jun 13 12:43:53 PM PDT 24 Jun 13 12:43:54 PM PDT 24 167996493 ps
T837 /workspace/coverage/cover_reg_top/3.gpio_intr_test.2282496337 Jun 13 12:43:57 PM PDT 24 Jun 13 12:43:58 PM PDT 24 18080121 ps
T838 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.443829841 Jun 13 12:44:08 PM PDT 24 Jun 13 12:44:09 PM PDT 24 13753431 ps
T839 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1647842574 Jun 13 12:43:32 PM PDT 24 Jun 13 12:43:34 PM PDT 24 267774912 ps
T840 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.3321793326 Jun 13 12:43:20 PM PDT 24 Jun 13 12:43:22 PM PDT 24 47560493 ps
T841 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1401779521 Jun 13 12:42:55 PM PDT 24 Jun 13 12:42:57 PM PDT 24 47729360 ps
T842 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2619923516 Jun 13 12:43:17 PM PDT 24 Jun 13 12:43:18 PM PDT 24 60891845 ps
T843 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3137927266 Jun 13 12:42:44 PM PDT 24 Jun 13 12:42:45 PM PDT 24 80065223 ps
T844 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3654069868 Jun 13 12:43:21 PM PDT 24 Jun 13 12:43:22 PM PDT 24 144627064 ps
T845 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.128548216 Jun 13 12:43:17 PM PDT 24 Jun 13 12:43:19 PM PDT 24 161140773 ps
T846 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1304915966 Jun 13 12:43:35 PM PDT 24 Jun 13 12:43:37 PM PDT 24 68543416 ps
T847 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3872978764 Jun 13 12:43:00 PM PDT 24 Jun 13 12:43:02 PM PDT 24 252686556 ps
T848 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3164250725 Jun 13 12:43:08 PM PDT 24 Jun 13 12:43:09 PM PDT 24 138277184 ps
T849 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.293264931 Jun 13 12:42:59 PM PDT 24 Jun 13 12:43:00 PM PDT 24 171943865 ps
T850 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1726295870 Jun 13 12:42:53 PM PDT 24 Jun 13 12:42:55 PM PDT 24 34816750 ps
T851 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2165058426 Jun 13 12:43:26 PM PDT 24 Jun 13 12:43:27 PM PDT 24 50180247 ps
T852 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.25637116 Jun 13 12:43:35 PM PDT 24 Jun 13 12:43:36 PM PDT 24 463387995 ps
T853 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3238972852 Jun 13 12:43:21 PM PDT 24 Jun 13 12:43:22 PM PDT 24 196904179 ps
T854 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.454533064 Jun 13 12:43:14 PM PDT 24 Jun 13 12:43:16 PM PDT 24 67243769 ps
T855 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.721979037 Jun 13 12:43:16 PM PDT 24 Jun 13 12:43:18 PM PDT 24 230592648 ps
T856 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1536466210 Jun 13 12:43:35 PM PDT 24 Jun 13 12:43:37 PM PDT 24 180736047 ps
T857 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.4164100187 Jun 13 12:43:08 PM PDT 24 Jun 13 12:43:10 PM PDT 24 51415161 ps
T858 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2726354110 Jun 13 12:42:55 PM PDT 24 Jun 13 12:42:56 PM PDT 24 296292790 ps
T859 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.54374823 Jun 13 12:43:35 PM PDT 24 Jun 13 12:43:37 PM PDT 24 274952237 ps
T860 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.67394864 Jun 13 12:43:21 PM PDT 24 Jun 13 12:43:23 PM PDT 24 52492092 ps
T861 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.595514854 Jun 13 12:42:55 PM PDT 24 Jun 13 12:42:57 PM PDT 24 71693068 ps
T862 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1936447460 Jun 13 12:43:14 PM PDT 24 Jun 13 12:43:15 PM PDT 24 56127049 ps
T863 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3470868365 Jun 13 12:43:01 PM PDT 24 Jun 13 12:43:03 PM PDT 24 323738968 ps
T864 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2667850963 Jun 13 12:43:37 PM PDT 24 Jun 13 12:43:38 PM PDT 24 65000004 ps
T865 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.447394907 Jun 13 12:42:59 PM PDT 24 Jun 13 12:43:00 PM PDT 24 65459734 ps
T866 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3546119218 Jun 13 12:43:21 PM PDT 24 Jun 13 12:43:22 PM PDT 24 61256912 ps
T867 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3889685111 Jun 13 12:43:30 PM PDT 24 Jun 13 12:43:31 PM PDT 24 89247958 ps
T868 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1541185198 Jun 13 12:43:22 PM PDT 24 Jun 13 12:43:24 PM PDT 24 225668994 ps
T869 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1297424224 Jun 13 12:42:34 PM PDT 24 Jun 13 12:42:36 PM PDT 24 78013885 ps
T870 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.654050256 Jun 13 12:42:32 PM PDT 24 Jun 13 12:42:34 PM PDT 24 164805884 ps
T871 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.602212459 Jun 13 12:42:35 PM PDT 24 Jun 13 12:42:37 PM PDT 24 261076064 ps
T872 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3389924190 Jun 13 12:42:46 PM PDT 24 Jun 13 12:42:47 PM PDT 24 30917629 ps
T873 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3475434775 Jun 13 12:43:28 PM PDT 24 Jun 13 12:43:29 PM PDT 24 26503222 ps
T874 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1037188793 Jun 13 12:43:21 PM PDT 24 Jun 13 12:43:22 PM PDT 24 90900636 ps
T875 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1204846783 Jun 13 12:43:38 PM PDT 24 Jun 13 12:43:39 PM PDT 24 27783755 ps
T876 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2962296516 Jun 13 12:42:58 PM PDT 24 Jun 13 12:43:00 PM PDT 24 243636530 ps
T877 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2696186082 Jun 13 12:43:28 PM PDT 24 Jun 13 12:43:30 PM PDT 24 173436733 ps
T878 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2686517056 Jun 13 12:43:29 PM PDT 24 Jun 13 12:43:30 PM PDT 24 439801181 ps
T879 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1740590095 Jun 13 12:43:15 PM PDT 24 Jun 13 12:43:17 PM PDT 24 130419188 ps
T880 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1046365601 Jun 13 12:43:19 PM PDT 24 Jun 13 12:43:20 PM PDT 24 218798518 ps
T881 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2624906323 Jun 13 12:43:26 PM PDT 24 Jun 13 12:43:27 PM PDT 24 37349081 ps
T882 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.589829431 Jun 13 12:43:15 PM PDT 24 Jun 13 12:43:16 PM PDT 24 73687568 ps
T883 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.127862054 Jun 13 12:43:00 PM PDT 24 Jun 13 12:43:02 PM PDT 24 130013193 ps
T884 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3128894376 Jun 13 12:43:35 PM PDT 24 Jun 13 12:43:36 PM PDT 24 42989954 ps
T885 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.4291682101 Jun 13 12:43:20 PM PDT 24 Jun 13 12:43:21 PM PDT 24 144167345 ps
T886 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1323051475 Jun 13 12:43:17 PM PDT 24 Jun 13 12:43:18 PM PDT 24 56335784 ps
T887 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2659781670 Jun 13 12:43:37 PM PDT 24 Jun 13 12:43:39 PM PDT 24 52797218 ps
T888 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2469976554 Jun 13 12:42:45 PM PDT 24 Jun 13 12:42:47 PM PDT 24 241716286 ps
T889 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2202563846 Jun 13 12:43:35 PM PDT 24 Jun 13 12:43:37 PM PDT 24 787653861 ps
T890 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1130439782 Jun 13 12:42:39 PM PDT 24 Jun 13 12:42:40 PM PDT 24 27474500 ps
T891 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3581356266 Jun 13 12:43:15 PM PDT 24 Jun 13 12:43:16 PM PDT 24 34622253 ps
T892 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2822589260 Jun 13 12:43:20 PM PDT 24 Jun 13 12:43:22 PM PDT 24 373063744 ps
T893 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.942263728 Jun 13 12:42:47 PM PDT 24 Jun 13 12:42:49 PM PDT 24 74646072 ps
T894 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.432221317 Jun 13 12:42:54 PM PDT 24 Jun 13 12:42:55 PM PDT 24 126726606 ps
T895 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.44881413 Jun 13 12:42:45 PM PDT 24 Jun 13 12:42:47 PM PDT 24 50264810 ps
T896 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2850948670 Jun 13 12:43:06 PM PDT 24 Jun 13 12:43:08 PM PDT 24 85217424 ps
T897 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2672540846 Jun 13 12:42:45 PM PDT 24 Jun 13 12:42:47 PM PDT 24 30545050 ps
T898 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3643312131 Jun 13 12:43:22 PM PDT 24 Jun 13 12:43:23 PM PDT 24 445834349 ps
T899 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1964205299 Jun 13 12:42:59 PM PDT 24 Jun 13 12:43:01 PM PDT 24 55018013 ps
T900 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1355681201 Jun 13 12:43:16 PM PDT 24 Jun 13 12:43:17 PM PDT 24 197098106 ps
T901 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.21429379 Jun 13 12:43:34 PM PDT 24 Jun 13 12:43:35 PM PDT 24 55986092 ps
T902 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2219596483 Jun 13 12:43:35 PM PDT 24 Jun 13 12:43:37 PM PDT 24 42663498 ps
T903 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2897826578 Jun 13 12:43:34 PM PDT 24 Jun 13 12:43:35 PM PDT 24 35140756 ps
T904 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1329964633 Jun 13 12:42:53 PM PDT 24 Jun 13 12:42:55 PM PDT 24 28986898 ps
T905 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2810087946 Jun 13 12:42:33 PM PDT 24 Jun 13 12:42:35 PM PDT 24 67084234 ps
T906 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1282013196 Jun 13 12:43:32 PM PDT 24 Jun 13 12:43:34 PM PDT 24 205277156 ps
T907 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1703757129 Jun 13 12:43:28 PM PDT 24 Jun 13 12:43:30 PM PDT 24 33982261 ps
T908 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3980008707 Jun 13 12:43:28 PM PDT 24 Jun 13 12:43:29 PM PDT 24 32975516 ps
T909 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.874367536 Jun 13 12:43:20 PM PDT 24 Jun 13 12:43:22 PM PDT 24 33752262 ps
T910 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3228091135 Jun 13 12:43:15 PM PDT 24 Jun 13 12:43:17 PM PDT 24 45346477 ps
T911 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.4032008568 Jun 13 12:42:33 PM PDT 24 Jun 13 12:42:35 PM PDT 24 161614797 ps
T912 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2773285643 Jun 13 12:43:15 PM PDT 24 Jun 13 12:43:17 PM PDT 24 24644855 ps
T913 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1628870923 Jun 13 12:43:20 PM PDT 24 Jun 13 12:43:22 PM PDT 24 97757847 ps
T914 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4013322473 Jun 13 12:43:13 PM PDT 24 Jun 13 12:43:14 PM PDT 24 52774059 ps
T915 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.802275554 Jun 13 12:43:36 PM PDT 24 Jun 13 12:43:38 PM PDT 24 102846083 ps
T916 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.355501567 Jun 13 12:43:15 PM PDT 24 Jun 13 12:43:16 PM PDT 24 465942466 ps
T917 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1040242180 Jun 13 12:43:15 PM PDT 24 Jun 13 12:43:16 PM PDT 24 70060044 ps
T918 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2714401497 Jun 13 12:42:55 PM PDT 24 Jun 13 12:42:56 PM PDT 24 80875026 ps
T919 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.588180948 Jun 13 12:43:00 PM PDT 24 Jun 13 12:43:02 PM PDT 24 72111148 ps
T920 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1585290789 Jun 13 12:43:13 PM PDT 24 Jun 13 12:43:15 PM PDT 24 112995563 ps
T921 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2420263190 Jun 13 12:42:44 PM PDT 24 Jun 13 12:42:45 PM PDT 24 147595690 ps
T922 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3966677971 Jun 13 12:42:32 PM PDT 24 Jun 13 12:42:33 PM PDT 24 33291009 ps
T923 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3631695978 Jun 13 12:42:53 PM PDT 24 Jun 13 12:42:55 PM PDT 24 92102784 ps
T924 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3154564858 Jun 13 12:43:00 PM PDT 24 Jun 13 12:43:02 PM PDT 24 56713443 ps
T925 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3247409871 Jun 13 12:43:07 PM PDT 24 Jun 13 12:43:09 PM PDT 24 113787957 ps
T926 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1903852845 Jun 13 12:42:40 PM PDT 24 Jun 13 12:42:42 PM PDT 24 62283350 ps
T927 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.834727254 Jun 13 12:43:22 PM PDT 24 Jun 13 12:43:23 PM PDT 24 35081848 ps
T928 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.779476110 Jun 13 12:42:35 PM PDT 24 Jun 13 12:42:36 PM PDT 24 45211653 ps
T929 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3989207023 Jun 13 12:43:00 PM PDT 24 Jun 13 12:43:02 PM PDT 24 286125820 ps
T930 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3521643321 Jun 13 12:42:47 PM PDT 24 Jun 13 12:42:49 PM PDT 24 311460653 ps
T931 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1798947799 Jun 13 12:42:52 PM PDT 24 Jun 13 12:42:53 PM PDT 24 34424949 ps
T932 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1584781254 Jun 13 12:42:34 PM PDT 24 Jun 13 12:42:36 PM PDT 24 69757489 ps
T933 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2244677042 Jun 13 12:42:53 PM PDT 24 Jun 13 12:42:54 PM PDT 24 118416399 ps
T934 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2857327837 Jun 13 12:42:44 PM PDT 24 Jun 13 12:42:46 PM PDT 24 128457247 ps
T935 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3409701243 Jun 13 12:43:35 PM PDT 24 Jun 13 12:43:36 PM PDT 24 71890695 ps
T936 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.917926191 Jun 13 12:43:34 PM PDT 24 Jun 13 12:43:36 PM PDT 24 210574354 ps
T937 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1857048011 Jun 13 12:43:28 PM PDT 24 Jun 13 12:43:29 PM PDT 24 32300431 ps
T938 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3034530352 Jun 13 12:42:59 PM PDT 24 Jun 13 12:43:01 PM PDT 24 169209907 ps

Test location /workspace/coverage/default/39.gpio_stress_all.4005064545
Short name T11
Test name
Test status
Simulation time 6872234516 ps
CPU time 108.65 seconds
Started Jun 13 12:48:32 PM PDT 24
Finished Jun 13 12:50:21 PM PDT 24
Peak memory 198056 kb
Host smart-f4e9ba34-e3b6-4311-8286-1b8f9719ebd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005064545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.4005064545
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.2189337559
Short name T28
Test name
Test status
Simulation time 38980654 ps
CPU time 1.62 seconds
Started Jun 13 01:53:35 PM PDT 24
Finished Jun 13 01:53:38 PM PDT 24
Peak memory 197928 kb
Host smart-4c887bd5-2b55-4dad-b765-76465f19cf03
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189337559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.2189337559
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.3240221994
Short name T4
Test name
Test status
Simulation time 206574986273 ps
CPU time 617.11 seconds
Started Jun 13 12:47:07 PM PDT 24
Finished Jun 13 12:57:24 PM PDT 24
Peak memory 198124 kb
Host smart-fb7e3080-7f24-46d0-8386-f01166fbd784
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3240221994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.3240221994
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.2299082741
Short name T34
Test name
Test status
Simulation time 126469171 ps
CPU time 0.8 seconds
Started Jun 13 12:45:40 PM PDT 24
Finished Jun 13 12:45:42 PM PDT 24
Peak memory 213468 kb
Host smart-bfe04e0f-d591-4edd-962b-7d48bd51d38c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299082741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.2299082741
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1044006472
Short name T75
Test name
Test status
Simulation time 33144307 ps
CPU time 0.76 seconds
Started Jun 13 12:43:43 PM PDT 24
Finished Jun 13 12:43:44 PM PDT 24
Peak memory 195496 kb
Host smart-c7821fd0-ffde-4ac2-a756-a05b9a198918
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044006472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.1044006472
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1422141049
Short name T39
Test name
Test status
Simulation time 89576556 ps
CPU time 1.14 seconds
Started Jun 13 12:44:33 PM PDT 24
Finished Jun 13 12:44:35 PM PDT 24
Peak memory 197792 kb
Host smart-22d47833-ac59-4e46-b054-0272d063e15a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422141049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.1422141049
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/19.gpio_alert_test.49212569
Short name T37
Test name
Test status
Simulation time 41973481 ps
CPU time 0.63 seconds
Started Jun 13 12:47:03 PM PDT 24
Finished Jun 13 12:47:04 PM PDT 24
Peak memory 193780 kb
Host smart-b5b57fc2-a16f-413e-a9c0-4140b3eaed59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49212569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.49212569
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1371311705
Short name T76
Test name
Test status
Simulation time 20436570 ps
CPU time 0.77 seconds
Started Jun 13 12:44:17 PM PDT 24
Finished Jun 13 12:44:18 PM PDT 24
Peak memory 195912 kb
Host smart-15c20cdd-f1cd-46a7-9ad9-57b11ce5b1f0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371311705 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.1371311705
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.4174585662
Short name T33
Test name
Test status
Simulation time 555044266 ps
CPU time 1.44 seconds
Started Jun 13 12:44:23 PM PDT 24
Finished Jun 13 12:44:25 PM PDT 24
Peak memory 197792 kb
Host smart-67c75819-2666-4928-aff3-c1b16eb9c8ae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174585662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.4174585662
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1545341935
Short name T32
Test name
Test status
Simulation time 172739000 ps
CPU time 1.54 seconds
Started Jun 13 12:44:17 PM PDT 24
Finished Jun 13 12:44:19 PM PDT 24
Peak memory 197656 kb
Host smart-507e5c9f-57d3-4ca9-b4d8-bf83313633e0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545341935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.1545341935
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1251034191
Short name T77
Test name
Test status
Simulation time 159854761 ps
CPU time 3.13 seconds
Started Jun 13 12:43:49 PM PDT 24
Finished Jun 13 12:43:52 PM PDT 24
Peak memory 197680 kb
Host smart-fcec72e2-4b15-4a55-bea3-5157637dfd99
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251034191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.1251034191
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.4006023693
Short name T749
Test name
Test status
Simulation time 17189292 ps
CPU time 0.62 seconds
Started Jun 13 12:43:43 PM PDT 24
Finished Jun 13 12:43:44 PM PDT 24
Peak memory 194312 kb
Host smart-519066eb-212c-45b1-b4ac-3e689d78b5e4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006023693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.4006023693
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1508687955
Short name T764
Test name
Test status
Simulation time 61646086 ps
CPU time 0.96 seconds
Started Jun 13 12:43:43 PM PDT 24
Finished Jun 13 12:43:44 PM PDT 24
Peak memory 197596 kb
Host smart-fa7efc00-97dc-40bd-8a2f-cbd15cfdba8b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508687955 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.1508687955
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1324339931
Short name T71
Test name
Test status
Simulation time 131755972 ps
CPU time 0.62 seconds
Started Jun 13 12:43:36 PM PDT 24
Finished Jun 13 12:43:37 PM PDT 24
Peak memory 194992 kb
Host smart-6fcb916a-4d5f-4407-8e24-fbf27e449fc7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324339931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.1324339931
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.3286990423
Short name T776
Test name
Test status
Simulation time 12257092 ps
CPU time 0.67 seconds
Started Jun 13 12:43:49 PM PDT 24
Finished Jun 13 12:43:50 PM PDT 24
Peak memory 193420 kb
Host smart-844700d3-7fc7-4e7a-9600-251ad14f8272
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286990423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.3286990423
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2747119461
Short name T779
Test name
Test status
Simulation time 52277983 ps
CPU time 0.62 seconds
Started Jun 13 12:43:37 PM PDT 24
Finished Jun 13 12:43:38 PM PDT 24
Peak memory 195164 kb
Host smart-46570577-cbbd-4bd8-9927-095bddea2c3e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747119461 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.2747119461
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2104082987
Short name T734
Test name
Test status
Simulation time 180148190 ps
CPU time 2.07 seconds
Started Jun 13 12:43:49 PM PDT 24
Finished Jun 13 12:43:51 PM PDT 24
Peak memory 197668 kb
Host smart-4c942703-0575-4194-b6db-7aa20f2a8352
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104082987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.2104082987
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.51392755
Short name T31
Test name
Test status
Simulation time 252235024 ps
CPU time 1.12 seconds
Started Jun 13 12:43:44 PM PDT 24
Finished Jun 13 12:43:45 PM PDT 24
Peak memory 197716 kb
Host smart-2d3d3804-b408-4068-ba1c-01a708e9f58c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51392755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_tl_intg_err.51392755
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2505936692
Short name T87
Test name
Test status
Simulation time 25140835 ps
CPU time 0.69 seconds
Started Jun 13 12:43:48 PM PDT 24
Finished Jun 13 12:43:49 PM PDT 24
Peak memory 194184 kb
Host smart-0f03c625-7fcc-482e-8b3a-8ebe2dcd8309
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505936692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.2505936692
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2257450524
Short name T769
Test name
Test status
Simulation time 255415886 ps
CPU time 2.97 seconds
Started Jun 13 12:43:48 PM PDT 24
Finished Jun 13 12:43:52 PM PDT 24
Peak memory 196524 kb
Host smart-5eaafb36-8bee-4a73-982d-272935caf225
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257450524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.2257450524
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.342195161
Short name T811
Test name
Test status
Simulation time 15247077 ps
CPU time 0.59 seconds
Started Jun 13 12:43:49 PM PDT 24
Finished Jun 13 12:43:50 PM PDT 24
Peak memory 194140 kb
Host smart-50592b29-621f-4212-ade4-78eac8afffea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342195161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.342195161
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.1785684546
Short name T719
Test name
Test status
Simulation time 27710613 ps
CPU time 0.8 seconds
Started Jun 13 12:43:43 PM PDT 24
Finished Jun 13 12:43:44 PM PDT 24
Peak memory 197664 kb
Host smart-5d3c4871-149d-4fab-9c2c-bfc3e4ca2ed1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785684546 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.1785684546
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2531757619
Short name T88
Test name
Test status
Simulation time 12493389 ps
CPU time 0.58 seconds
Started Jun 13 12:43:42 PM PDT 24
Finished Jun 13 12:43:43 PM PDT 24
Peak memory 193696 kb
Host smart-52ad2b16-4d9c-4d4e-a2af-e25aa4095791
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531757619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.2531757619
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.482111896
Short name T737
Test name
Test status
Simulation time 37973035 ps
CPU time 0.62 seconds
Started Jun 13 12:43:49 PM PDT 24
Finished Jun 13 12:43:50 PM PDT 24
Peak memory 194148 kb
Host smart-1c9491de-1416-4040-8a87-938693d3efd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482111896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.482111896
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.544330171
Short name T810
Test name
Test status
Simulation time 18723837 ps
CPU time 0.72 seconds
Started Jun 13 12:43:50 PM PDT 24
Finished Jun 13 12:43:51 PM PDT 24
Peak memory 195372 kb
Host smart-8c499cc6-922b-4727-be92-e8ade5916ade
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544330171 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.gpio_same_csr_outstanding.544330171
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.360655832
Short name T736
Test name
Test status
Simulation time 34091243 ps
CPU time 1.1 seconds
Started Jun 13 12:43:48 PM PDT 24
Finished Jun 13 12:43:49 PM PDT 24
Peak memory 197604 kb
Host smart-182bd3b1-18d5-40aa-9a74-6d37680d8994
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360655832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.360655832
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3976444881
Short name T806
Test name
Test status
Simulation time 285697876 ps
CPU time 1.18 seconds
Started Jun 13 12:43:41 PM PDT 24
Finished Jun 13 12:43:43 PM PDT 24
Peak memory 197656 kb
Host smart-95a8c638-1766-4a35-a835-504e38569c35
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976444881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.3976444881
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2566836112
Short name T763
Test name
Test status
Simulation time 19078609 ps
CPU time 1.02 seconds
Started Jun 13 12:44:16 PM PDT 24
Finished Jun 13 12:44:17 PM PDT 24
Peak memory 197624 kb
Host smart-a40af650-cb63-4cd9-8f33-fc2e8171ac0c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566836112 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.2566836112
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3946676399
Short name T80
Test name
Test status
Simulation time 17751867 ps
CPU time 0.61 seconds
Started Jun 13 12:44:18 PM PDT 24
Finished Jun 13 12:44:19 PM PDT 24
Peak memory 194424 kb
Host smart-b59d7da5-1129-4699-a375-c580771feb56
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946676399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.3946676399
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.3678114662
Short name T758
Test name
Test status
Simulation time 25555549 ps
CPU time 0.63 seconds
Started Jun 13 12:44:17 PM PDT 24
Finished Jun 13 12:44:18 PM PDT 24
Peak memory 194128 kb
Host smart-45c6bd52-041e-4e5a-888c-25da535cef47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678114662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.3678114662
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.4186016621
Short name T752
Test name
Test status
Simulation time 421556015 ps
CPU time 1.73 seconds
Started Jun 13 12:44:15 PM PDT 24
Finished Jun 13 12:44:17 PM PDT 24
Peak memory 197752 kb
Host smart-1ca3751c-863c-44f5-a3b5-daa2fa52658e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186016621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.4186016621
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.1048245278
Short name T735
Test name
Test status
Simulation time 27722437 ps
CPU time 0.87 seconds
Started Jun 13 12:44:19 PM PDT 24
Finished Jun 13 12:44:20 PM PDT 24
Peak memory 197676 kb
Host smart-6bd209ca-f7a5-4e0e-a55a-ec6e2687061c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048245278 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.1048245278
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.2662904348
Short name T789
Test name
Test status
Simulation time 15611538 ps
CPU time 0.66 seconds
Started Jun 13 12:44:15 PM PDT 24
Finished Jun 13 12:44:16 PM PDT 24
Peak memory 194276 kb
Host smart-5a986026-a768-4eeb-a5ef-5d9729df1b37
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662904348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.2662904348
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.840303459
Short name T773
Test name
Test status
Simulation time 26106055 ps
CPU time 0.62 seconds
Started Jun 13 12:44:22 PM PDT 24
Finished Jun 13 12:44:23 PM PDT 24
Peak memory 193500 kb
Host smart-5882596c-c9ca-478f-9f8c-3c6161debb26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840303459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.840303459
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3611295343
Short name T95
Test name
Test status
Simulation time 19206786 ps
CPU time 0.91 seconds
Started Jun 13 12:44:17 PM PDT 24
Finished Jun 13 12:44:18 PM PDT 24
Peak memory 196148 kb
Host smart-dd7f40d7-6537-4cee-aaac-b52687685770
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611295343 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.3611295343
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.3810550195
Short name T713
Test name
Test status
Simulation time 100993328 ps
CPU time 2.28 seconds
Started Jun 13 12:44:15 PM PDT 24
Finished Jun 13 12:44:18 PM PDT 24
Peak memory 197732 kb
Host smart-16c00c63-134a-44cd-bf25-217b029a9ba5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810550195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.3810550195
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1377843005
Short name T40
Test name
Test status
Simulation time 114449178 ps
CPU time 1.49 seconds
Started Jun 13 12:44:16 PM PDT 24
Finished Jun 13 12:44:19 PM PDT 24
Peak memory 197624 kb
Host smart-d86cc4a3-1439-4e52-84af-68b149ec3de2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377843005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.1377843005
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1776002576
Short name T766
Test name
Test status
Simulation time 120269508 ps
CPU time 0.86 seconds
Started Jun 13 12:44:15 PM PDT 24
Finished Jun 13 12:44:16 PM PDT 24
Peak memory 197616 kb
Host smart-e0ab8572-4f7b-407a-b848-7e61339df8d5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776002576 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.1776002576
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1724516699
Short name T814
Test name
Test status
Simulation time 17677267 ps
CPU time 0.61 seconds
Started Jun 13 12:44:16 PM PDT 24
Finished Jun 13 12:44:17 PM PDT 24
Peak memory 194232 kb
Host smart-cd2bd8c8-7a71-41d9-83b1-5d0cf966d53c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724516699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.1724516699
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.1171542292
Short name T778
Test name
Test status
Simulation time 45843865 ps
CPU time 0.59 seconds
Started Jun 13 12:44:15 PM PDT 24
Finished Jun 13 12:44:17 PM PDT 24
Peak memory 193964 kb
Host smart-d5f0e04f-347b-4235-866a-7a3a1b54ce97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171542292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.1171542292
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3575441940
Short name T98
Test name
Test status
Simulation time 70862036 ps
CPU time 0.91 seconds
Started Jun 13 12:44:18 PM PDT 24
Finished Jun 13 12:44:19 PM PDT 24
Peak memory 197624 kb
Host smart-ea3f8ab2-4fb6-428a-b2e0-8943e171530b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575441940 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.3575441940
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.4091349339
Short name T756
Test name
Test status
Simulation time 351311413 ps
CPU time 1.83 seconds
Started Jun 13 12:44:16 PM PDT 24
Finished Jun 13 12:44:18 PM PDT 24
Peak memory 197772 kb
Host smart-d7170225-d072-40a7-baf2-50bba343f88b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091349339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.4091349339
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.3246787690
Short name T100
Test name
Test status
Simulation time 57363472 ps
CPU time 0.95 seconds
Started Jun 13 12:44:16 PM PDT 24
Finished Jun 13 12:44:17 PM PDT 24
Peak memory 196612 kb
Host smart-68baa684-a729-4e21-a821-af0ba136d12e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246787690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.3246787690
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1590280140
Short name T727
Test name
Test status
Simulation time 42252819 ps
CPU time 0.81 seconds
Started Jun 13 12:44:16 PM PDT 24
Finished Jun 13 12:44:17 PM PDT 24
Peak memory 197436 kb
Host smart-4f9c0430-44cc-4342-b3c8-4f712cff7e55
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590280140 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.1590280140
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.4245452266
Short name T81
Test name
Test status
Simulation time 11751651 ps
CPU time 0.6 seconds
Started Jun 13 12:44:18 PM PDT 24
Finished Jun 13 12:44:19 PM PDT 24
Peak memory 192908 kb
Host smart-26321af4-437a-4f43-a9f6-a0bdee1dee7b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245452266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.4245452266
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.216025859
Short name T785
Test name
Test status
Simulation time 31772236 ps
CPU time 0.65 seconds
Started Jun 13 12:44:16 PM PDT 24
Finished Jun 13 12:44:18 PM PDT 24
Peak memory 194160 kb
Host smart-5c50ef57-1f14-4c81-8750-ba60c377c382
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216025859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.216025859
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.369759448
Short name T784
Test name
Test status
Simulation time 33666471 ps
CPU time 0.89 seconds
Started Jun 13 12:44:18 PM PDT 24
Finished Jun 13 12:44:20 PM PDT 24
Peak memory 196788 kb
Host smart-35da6b5d-b3ca-48d6-b7e6-1a438be46caf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369759448 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 13.gpio_same_csr_outstanding.369759448
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.456304933
Short name T783
Test name
Test status
Simulation time 126489245 ps
CPU time 2.93 seconds
Started Jun 13 12:44:17 PM PDT 24
Finished Jun 13 12:44:20 PM PDT 24
Peak memory 197808 kb
Host smart-3f4c0256-63a1-465f-abf9-7ba3c4434ce6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456304933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.456304933
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2258467541
Short name T41
Test name
Test status
Simulation time 97206561 ps
CPU time 1.36 seconds
Started Jun 13 12:44:18 PM PDT 24
Finished Jun 13 12:44:20 PM PDT 24
Peak memory 197784 kb
Host smart-8e5a7d50-769f-4960-8246-14c0ebfeb7ea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258467541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.2258467541
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.499377240
Short name T772
Test name
Test status
Simulation time 93512315 ps
CPU time 1.07 seconds
Started Jun 13 12:44:22 PM PDT 24
Finished Jun 13 12:44:24 PM PDT 24
Peak memory 197624 kb
Host smart-0e342b03-f767-4cdb-bc1d-5cf80b7ecc32
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499377240 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.499377240
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1833954980
Short name T72
Test name
Test status
Simulation time 29879825 ps
CPU time 0.56 seconds
Started Jun 13 12:44:21 PM PDT 24
Finished Jun 13 12:44:22 PM PDT 24
Peak memory 192932 kb
Host smart-2ddfefa8-8b22-4ceb-807b-578e7b83e5d5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833954980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.1833954980
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.628608995
Short name T786
Test name
Test status
Simulation time 31252495 ps
CPU time 0.6 seconds
Started Jun 13 12:44:24 PM PDT 24
Finished Jun 13 12:44:25 PM PDT 24
Peak memory 193980 kb
Host smart-1075defb-b6ec-4444-aca4-755908794b10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628608995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.628608995
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2304174000
Short name T823
Test name
Test status
Simulation time 124921194 ps
CPU time 0.83 seconds
Started Jun 13 12:44:23 PM PDT 24
Finished Jun 13 12:44:25 PM PDT 24
Peak memory 196108 kb
Host smart-eb87cf22-430d-43b2-af3a-62da06c72298
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304174000 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.2304174000
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.529981048
Short name T787
Test name
Test status
Simulation time 230184634 ps
CPU time 2.63 seconds
Started Jun 13 12:44:24 PM PDT 24
Finished Jun 13 12:44:27 PM PDT 24
Peak memory 197772 kb
Host smart-065c7ec6-a903-4fd5-b1d0-b95b6f86193c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529981048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.529981048
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2048244919
Short name T820
Test name
Test status
Simulation time 34563123 ps
CPU time 0.97 seconds
Started Jun 13 12:44:21 PM PDT 24
Finished Jun 13 12:44:22 PM PDT 24
Peak memory 197600 kb
Host smart-9e776596-1987-49aa-8660-2b99bb9040ba
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048244919 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.2048244919
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.3147335042
Short name T767
Test name
Test status
Simulation time 12320735 ps
CPU time 0.58 seconds
Started Jun 13 12:44:24 PM PDT 24
Finished Jun 13 12:44:25 PM PDT 24
Peak memory 194936 kb
Host smart-366b02fb-bd44-453d-b7e8-586652245a68
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147335042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.3147335042
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.614888359
Short name T733
Test name
Test status
Simulation time 70847491 ps
CPU time 0.56 seconds
Started Jun 13 12:44:25 PM PDT 24
Finished Jun 13 12:44:26 PM PDT 24
Peak memory 193372 kb
Host smart-d139c8de-89af-45c5-b4b6-fd55f10618db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614888359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.614888359
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.3996405584
Short name T791
Test name
Test status
Simulation time 126919533 ps
CPU time 0.62 seconds
Started Jun 13 12:44:23 PM PDT 24
Finished Jun 13 12:44:25 PM PDT 24
Peak memory 193948 kb
Host smart-788bab97-3731-4069-ab1c-a803f3d9b908
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996405584 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.3996405584
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.3100084520
Short name T729
Test name
Test status
Simulation time 108322101 ps
CPU time 2.27 seconds
Started Jun 13 12:44:24 PM PDT 24
Finished Jun 13 12:44:27 PM PDT 24
Peak memory 197712 kb
Host smart-76da582d-9029-4611-98f4-3e82b6c02b96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100084520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.3100084520
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3573836221
Short name T42
Test name
Test status
Simulation time 48005191 ps
CPU time 0.9 seconds
Started Jun 13 12:44:21 PM PDT 24
Finished Jun 13 12:44:22 PM PDT 24
Peak memory 196752 kb
Host smart-bd58b1cd-ea9d-4439-93f8-a758afdc6530
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573836221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.3573836221
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1295173990
Short name T796
Test name
Test status
Simulation time 145582231 ps
CPU time 0.96 seconds
Started Jun 13 12:44:28 PM PDT 24
Finished Jun 13 12:44:30 PM PDT 24
Peak memory 197684 kb
Host smart-34ecb9ed-ae00-47cd-ac85-c5145f086c9f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295173990 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.1295173990
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1126103954
Short name T84
Test name
Test status
Simulation time 169063277 ps
CPU time 0.58 seconds
Started Jun 13 12:44:30 PM PDT 24
Finished Jun 13 12:44:31 PM PDT 24
Peak memory 193012 kb
Host smart-c855d012-10d6-4e59-b854-678fd07bd81b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126103954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.1126103954
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.2238856773
Short name T715
Test name
Test status
Simulation time 13260984 ps
CPU time 0.59 seconds
Started Jun 13 12:44:29 PM PDT 24
Finished Jun 13 12:44:30 PM PDT 24
Peak memory 193316 kb
Host smart-4f392e18-0d24-4bba-8aaa-c3252f04687b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238856773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.2238856773
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1702970488
Short name T93
Test name
Test status
Simulation time 52001444 ps
CPU time 0.71 seconds
Started Jun 13 12:44:28 PM PDT 24
Finished Jun 13 12:44:29 PM PDT 24
Peak memory 195700 kb
Host smart-f958eb48-4b69-48af-8fae-a9efec131906
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702970488 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.1702970488
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1638649716
Short name T828
Test name
Test status
Simulation time 92911097 ps
CPU time 1.43 seconds
Started Jun 13 12:44:28 PM PDT 24
Finished Jun 13 12:44:30 PM PDT 24
Peak memory 197852 kb
Host smart-2a4f6302-b6be-4f5e-ac33-7c911bc5065c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638649716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1638649716
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.941630034
Short name T793
Test name
Test status
Simulation time 123458180 ps
CPU time 1.43 seconds
Started Jun 13 12:44:33 PM PDT 24
Finished Jun 13 12:44:35 PM PDT 24
Peak memory 197812 kb
Host smart-16d31f13-db57-4592-8f38-23a0cd40e359
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941630034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.gpio_tl_intg_err.941630034
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.1799036601
Short name T738
Test name
Test status
Simulation time 56605306 ps
CPU time 0.85 seconds
Started Jun 13 12:44:29 PM PDT 24
Finished Jun 13 12:44:30 PM PDT 24
Peak memory 197628 kb
Host smart-d2e9392f-46fe-4bd4-a8c3-080b43caca01
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799036601 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.1799036601
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.415248837
Short name T90
Test name
Test status
Simulation time 18113598 ps
CPU time 0.59 seconds
Started Jun 13 12:44:30 PM PDT 24
Finished Jun 13 12:44:31 PM PDT 24
Peak memory 194340 kb
Host smart-46eb3159-c288-4539-bc73-fe5d9e619e3c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415248837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio
_csr_rw.415248837
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.1837504521
Short name T765
Test name
Test status
Simulation time 12706690 ps
CPU time 0.6 seconds
Started Jun 13 12:44:29 PM PDT 24
Finished Jun 13 12:44:30 PM PDT 24
Peak memory 193320 kb
Host smart-1cbb7547-fc25-4d2c-af57-7b8d2a874022
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837504521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.1837504521
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.1952876447
Short name T78
Test name
Test status
Simulation time 20549331 ps
CPU time 0.8 seconds
Started Jun 13 12:44:33 PM PDT 24
Finished Jun 13 12:44:34 PM PDT 24
Peak memory 196216 kb
Host smart-8427c5b5-f39f-4f3d-81ea-73c613966208
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952876447 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.1952876447
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.450452702
Short name T827
Test name
Test status
Simulation time 63604620 ps
CPU time 1.37 seconds
Started Jun 13 12:44:30 PM PDT 24
Finished Jun 13 12:44:32 PM PDT 24
Peak memory 197664 kb
Host smart-10f14fdc-ea6f-4c4d-b00a-f37cb2ceef9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450452702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.450452702
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.823681419
Short name T747
Test name
Test status
Simulation time 48063230 ps
CPU time 0.63 seconds
Started Jun 13 12:44:27 PM PDT 24
Finished Jun 13 12:44:28 PM PDT 24
Peak memory 196176 kb
Host smart-88ea3218-ad4a-4c81-994d-c3bcc7395a03
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823681419 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.823681419
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2443444976
Short name T86
Test name
Test status
Simulation time 14914718 ps
CPU time 0.6 seconds
Started Jun 13 12:44:28 PM PDT 24
Finished Jun 13 12:44:29 PM PDT 24
Peak memory 194636 kb
Host smart-eeef862c-a0df-4da7-9137-3619481936ae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443444976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.2443444976
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.4066032392
Short name T745
Test name
Test status
Simulation time 12080343 ps
CPU time 0.58 seconds
Started Jun 13 12:44:37 PM PDT 24
Finished Jun 13 12:44:38 PM PDT 24
Peak memory 193352 kb
Host smart-32d70cc4-1e16-4197-9a9e-aac4adda3625
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066032392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.4066032392
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.706664749
Short name T818
Test name
Test status
Simulation time 19176325 ps
CPU time 0.65 seconds
Started Jun 13 12:44:28 PM PDT 24
Finished Jun 13 12:44:30 PM PDT 24
Peak memory 194572 kb
Host smart-884f684b-2a03-4926-bb9e-dddc3393c19a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706664749 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 18.gpio_same_csr_outstanding.706664749
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.1780251572
Short name T781
Test name
Test status
Simulation time 90534587 ps
CPU time 1.55 seconds
Started Jun 13 12:44:26 PM PDT 24
Finished Jun 13 12:44:28 PM PDT 24
Peak memory 197808 kb
Host smart-17706c89-abf3-4d30-bdc0-29ae16e5e3b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780251572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.1780251572
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.3277614561
Short name T794
Test name
Test status
Simulation time 274557049 ps
CPU time 0.91 seconds
Started Jun 13 12:44:28 PM PDT 24
Finished Jun 13 12:44:30 PM PDT 24
Peak memory 196796 kb
Host smart-3ea2ef5c-5245-447d-9645-9ded93e4e5cf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277614561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.3277614561
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3999896587
Short name T832
Test name
Test status
Simulation time 115869626 ps
CPU time 0.72 seconds
Started Jun 13 12:44:39 PM PDT 24
Finished Jun 13 12:44:40 PM PDT 24
Peak memory 197604 kb
Host smart-3e0b5a77-9ebc-4ed6-bc73-c977e97ba43e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999896587 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.3999896587
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.573135121
Short name T74
Test name
Test status
Simulation time 69131207 ps
CPU time 0.61 seconds
Started Jun 13 12:44:36 PM PDT 24
Finished Jun 13 12:44:37 PM PDT 24
Peak memory 194200 kb
Host smart-aa673285-d672-4fc4-9c10-dac702dee7ef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573135121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio
_csr_rw.573135121
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.1457250126
Short name T824
Test name
Test status
Simulation time 20444962 ps
CPU time 0.61 seconds
Started Jun 13 12:44:35 PM PDT 24
Finished Jun 13 12:44:36 PM PDT 24
Peak memory 193308 kb
Host smart-bbff9a4f-c41f-4f2e-8db2-a716baea253d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457250126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1457250126
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1649384646
Short name T795
Test name
Test status
Simulation time 60586690 ps
CPU time 0.75 seconds
Started Jun 13 12:44:39 PM PDT 24
Finished Jun 13 12:44:40 PM PDT 24
Peak memory 195504 kb
Host smart-57ca40b9-2fdd-472e-b332-b057b03e988f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649384646 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.1649384646
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1495822674
Short name T799
Test name
Test status
Simulation time 109068687 ps
CPU time 1.96 seconds
Started Jun 13 12:44:36 PM PDT 24
Finished Jun 13 12:44:38 PM PDT 24
Peak memory 197772 kb
Host smart-45f6f966-f781-4900-827f-c6ff0d5e02f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495822674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.1495822674
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3441645849
Short name T790
Test name
Test status
Simulation time 46754539 ps
CPU time 0.93 seconds
Started Jun 13 12:44:35 PM PDT 24
Finished Jun 13 12:44:37 PM PDT 24
Peak memory 197528 kb
Host smart-b022d1ae-5503-4332-b65c-dacc9fbfb89a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441645849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.3441645849
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2294382610
Short name T804
Test name
Test status
Simulation time 40048966 ps
CPU time 0.76 seconds
Started Jun 13 12:43:50 PM PDT 24
Finished Jun 13 12:43:51 PM PDT 24
Peak memory 195372 kb
Host smart-bc6de5e6-fd44-4106-83ea-e8f499a4112c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294382610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.2294382610
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3675725640
Short name T761
Test name
Test status
Simulation time 35498765 ps
CPU time 1.4 seconds
Started Jun 13 12:43:55 PM PDT 24
Finished Jun 13 12:43:57 PM PDT 24
Peak memory 197784 kb
Host smart-b415f51c-3091-406c-a0bd-1471c93a973f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675725640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.3675725640
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.3032516752
Short name T835
Test name
Test status
Simulation time 62605656 ps
CPU time 0.63 seconds
Started Jun 13 12:43:57 PM PDT 24
Finished Jun 13 12:43:58 PM PDT 24
Peak memory 194224 kb
Host smart-1c81a753-aefa-4a1d-97ec-0ebc14a2fba5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032516752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.3032516752
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1231924222
Short name T732
Test name
Test status
Simulation time 134950235 ps
CPU time 0.88 seconds
Started Jun 13 12:43:48 PM PDT 24
Finished Jun 13 12:43:50 PM PDT 24
Peak memory 197616 kb
Host smart-7a0f0d3b-4dfd-4e0f-823f-8d0e8b72cdd2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231924222 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.1231924222
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2031314979
Short name T803
Test name
Test status
Simulation time 59527306 ps
CPU time 0.68 seconds
Started Jun 13 12:43:48 PM PDT 24
Finished Jun 13 12:43:49 PM PDT 24
Peak memory 194812 kb
Host smart-b9f94956-318b-4803-bcd5-d5b3946fb898
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031314979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.2031314979
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.3874316433
Short name T759
Test name
Test status
Simulation time 35497391 ps
CPU time 0.58 seconds
Started Jun 13 12:43:49 PM PDT 24
Finished Jun 13 12:43:50 PM PDT 24
Peak memory 193324 kb
Host smart-24c61166-1871-4e27-9c5a-b5f82eed1453
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874316433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.3874316433
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.1180244240
Short name T780
Test name
Test status
Simulation time 57305826 ps
CPU time 0.64 seconds
Started Jun 13 12:43:47 PM PDT 24
Finished Jun 13 12:43:48 PM PDT 24
Peak memory 194432 kb
Host smart-ecd574b6-c579-4600-8adc-d6d6970a09e6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180244240 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.1180244240
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1274687830
Short name T717
Test name
Test status
Simulation time 245917375 ps
CPU time 2.26 seconds
Started Jun 13 12:43:50 PM PDT 24
Finished Jun 13 12:43:52 PM PDT 24
Peak memory 197800 kb
Host smart-7ba982f2-50a6-4574-a72e-7540b4353224
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274687830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.1274687830
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3300882988
Short name T821
Test name
Test status
Simulation time 352828879 ps
CPU time 1.45 seconds
Started Jun 13 12:43:50 PM PDT 24
Finished Jun 13 12:43:52 PM PDT 24
Peak memory 197804 kb
Host smart-b6ac54b5-9656-4197-a476-587587c66616
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300882988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.3300882988
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.2973459581
Short name T805
Test name
Test status
Simulation time 12816215 ps
CPU time 0.59 seconds
Started Jun 13 12:44:35 PM PDT 24
Finished Jun 13 12:44:36 PM PDT 24
Peak memory 193380 kb
Host smart-54d4c142-216d-4c0a-a905-906f3b3a6a54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973459581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.2973459581
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.712673027
Short name T831
Test name
Test status
Simulation time 22273292 ps
CPU time 0.59 seconds
Started Jun 13 12:44:34 PM PDT 24
Finished Jun 13 12:44:35 PM PDT 24
Peak memory 193388 kb
Host smart-9188f081-5683-4f88-9c3c-7f0f3fd73c76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712673027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.712673027
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.2008979619
Short name T716
Test name
Test status
Simulation time 11573598 ps
CPU time 0.58 seconds
Started Jun 13 12:44:34 PM PDT 24
Finished Jun 13 12:44:35 PM PDT 24
Peak memory 193312 kb
Host smart-a9c98ed0-9a22-47a1-8b2f-f26b8644d6d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008979619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.2008979619
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.1909927815
Short name T725
Test name
Test status
Simulation time 39242941 ps
CPU time 0.57 seconds
Started Jun 13 12:44:43 PM PDT 24
Finished Jun 13 12:44:45 PM PDT 24
Peak memory 193396 kb
Host smart-1c7df962-6e46-4fbc-a854-57541247c97c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909927815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.1909927815
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.949213062
Short name T825
Test name
Test status
Simulation time 49210024 ps
CPU time 0.65 seconds
Started Jun 13 12:44:44 PM PDT 24
Finished Jun 13 12:44:45 PM PDT 24
Peak memory 194048 kb
Host smart-3871003e-1eac-4f60-8323-6d85dc4b1437
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949213062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.949213062
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.4040945313
Short name T722
Test name
Test status
Simulation time 20391178 ps
CPU time 0.57 seconds
Started Jun 13 12:44:55 PM PDT 24
Finished Jun 13 12:44:56 PM PDT 24
Peak memory 193396 kb
Host smart-c2b4db59-1fd1-48e0-898b-14cd49222d6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040945313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.4040945313
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.3853886469
Short name T817
Test name
Test status
Simulation time 14708777 ps
CPU time 0.6 seconds
Started Jun 13 12:44:42 PM PDT 24
Finished Jun 13 12:44:43 PM PDT 24
Peak memory 194052 kb
Host smart-ba61a44e-a697-49a5-a545-17a1c9efeca8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853886469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.3853886469
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.916125920
Short name T753
Test name
Test status
Simulation time 38164953 ps
CPU time 0.57 seconds
Started Jun 13 12:44:41 PM PDT 24
Finished Jun 13 12:44:42 PM PDT 24
Peak memory 193392 kb
Host smart-668e3126-1356-4476-98dd-804ee4cfa8be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916125920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.916125920
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.3344426557
Short name T829
Test name
Test status
Simulation time 13620796 ps
CPU time 0.6 seconds
Started Jun 13 12:44:57 PM PDT 24
Finished Jun 13 12:44:58 PM PDT 24
Peak memory 193456 kb
Host smart-dd530a9c-9cc8-42dd-a747-e5d6cba8cd8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344426557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.3344426557
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.3457372672
Short name T739
Test name
Test status
Simulation time 13026310 ps
CPU time 0.58 seconds
Started Jun 13 12:44:42 PM PDT 24
Finished Jun 13 12:44:42 PM PDT 24
Peak memory 193360 kb
Host smart-625c1a79-894a-47f3-99ac-d9af5d8879fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457372672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.3457372672
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1621589040
Short name T83
Test name
Test status
Simulation time 30669724 ps
CPU time 0.78 seconds
Started Jun 13 12:43:56 PM PDT 24
Finished Jun 13 12:43:57 PM PDT 24
Peak memory 195700 kb
Host smart-09ccffe5-2659-4d50-b82b-8461210805b5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621589040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.1621589040
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1846143529
Short name T830
Test name
Test status
Simulation time 325314434 ps
CPU time 2.51 seconds
Started Jun 13 12:43:57 PM PDT 24
Finished Jun 13 12:44:00 PM PDT 24
Peak memory 197764 kb
Host smart-512f6e07-4c43-433e-838b-026da27b2227
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846143529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.1846143529
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3494519117
Short name T744
Test name
Test status
Simulation time 16496961 ps
CPU time 0.67 seconds
Started Jun 13 12:43:58 PM PDT 24
Finished Jun 13 12:43:59 PM PDT 24
Peak memory 194464 kb
Host smart-4de45e12-f70f-482c-8e05-6e0c1bae2317
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494519117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.3494519117
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.218821674
Short name T723
Test name
Test status
Simulation time 343278341 ps
CPU time 1.29 seconds
Started Jun 13 12:43:56 PM PDT 24
Finished Jun 13 12:43:57 PM PDT 24
Peak memory 197880 kb
Host smart-3bac4086-151c-401b-91e6-3bd804921fff
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218821674 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.218821674
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1667626368
Short name T85
Test name
Test status
Simulation time 55497818 ps
CPU time 0.66 seconds
Started Jun 13 12:43:53 PM PDT 24
Finished Jun 13 12:43:54 PM PDT 24
Peak memory 194744 kb
Host smart-451fc470-f36a-45d8-add9-36c30725e6f0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667626368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.1667626368
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.2282496337
Short name T837
Test name
Test status
Simulation time 18080121 ps
CPU time 0.58 seconds
Started Jun 13 12:43:57 PM PDT 24
Finished Jun 13 12:43:58 PM PDT 24
Peak memory 194080 kb
Host smart-a1f82096-bb01-48ad-98bc-404aa8a097c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282496337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.2282496337
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.373809202
Short name T91
Test name
Test status
Simulation time 43729537 ps
CPU time 0.85 seconds
Started Jun 13 12:43:55 PM PDT 24
Finished Jun 13 12:43:56 PM PDT 24
Peak memory 195992 kb
Host smart-47be4ccd-e5e8-4642-9328-467b9e784a3b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373809202 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.gpio_same_csr_outstanding.373809202
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.493876290
Short name T834
Test name
Test status
Simulation time 85379403 ps
CPU time 2.29 seconds
Started Jun 13 12:44:00 PM PDT 24
Finished Jun 13 12:44:02 PM PDT 24
Peak memory 197808 kb
Host smart-1d7f0060-2062-4b13-a0f8-688509885545
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493876290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.493876290
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1757745299
Short name T754
Test name
Test status
Simulation time 83072493 ps
CPU time 1.18 seconds
Started Jun 13 12:43:58 PM PDT 24
Finished Jun 13 12:43:59 PM PDT 24
Peak memory 197804 kb
Host smart-0d3fd8c8-42c9-40de-9ccf-48cf15fd6547
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757745299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.1757745299
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.2815430920
Short name T800
Test name
Test status
Simulation time 19208886 ps
CPU time 0.6 seconds
Started Jun 13 12:44:42 PM PDT 24
Finished Jun 13 12:44:43 PM PDT 24
Peak memory 193392 kb
Host smart-9d843b1a-4721-4b82-84d3-baa5170b2125
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815430920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.2815430920
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.3391251323
Short name T782
Test name
Test status
Simulation time 21297776 ps
CPU time 0.61 seconds
Started Jun 13 12:44:44 PM PDT 24
Finished Jun 13 12:44:46 PM PDT 24
Peak memory 194060 kb
Host smart-f4ad15fd-02fd-434b-a835-61cf4f1f0315
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391251323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.3391251323
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.1072103076
Short name T718
Test name
Test status
Simulation time 18466111 ps
CPU time 0.65 seconds
Started Jun 13 12:44:44 PM PDT 24
Finished Jun 13 12:44:45 PM PDT 24
Peak memory 193480 kb
Host smart-f4ab6ebf-2c28-471e-9097-75d19a53b527
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072103076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.1072103076
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.2148463836
Short name T833
Test name
Test status
Simulation time 28113157 ps
CPU time 0.6 seconds
Started Jun 13 12:44:42 PM PDT 24
Finished Jun 13 12:44:44 PM PDT 24
Peak memory 194088 kb
Host smart-b3a3ba51-c074-446e-b64a-e6dcc5635a0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148463836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.2148463836
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.3140126056
Short name T751
Test name
Test status
Simulation time 16120569 ps
CPU time 0.6 seconds
Started Jun 13 12:44:44 PM PDT 24
Finished Jun 13 12:44:46 PM PDT 24
Peak memory 193388 kb
Host smart-d68c106b-e19d-428c-94a9-02c2a185c5e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140126056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.3140126056
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.106470191
Short name T724
Test name
Test status
Simulation time 46165585 ps
CPU time 0.62 seconds
Started Jun 13 12:44:42 PM PDT 24
Finished Jun 13 12:44:44 PM PDT 24
Peak memory 194016 kb
Host smart-026d44bd-8c99-47a3-838e-bfe4488bc52a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106470191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.106470191
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.4199780856
Short name T746
Test name
Test status
Simulation time 27385050 ps
CPU time 0.59 seconds
Started Jun 13 12:44:42 PM PDT 24
Finished Jun 13 12:44:44 PM PDT 24
Peak memory 194076 kb
Host smart-1a03c425-6e9e-4b47-adef-45a8e22d2f6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199780856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.4199780856
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.388013849
Short name T815
Test name
Test status
Simulation time 13103536 ps
CPU time 0.61 seconds
Started Jun 13 12:44:56 PM PDT 24
Finished Jun 13 12:44:57 PM PDT 24
Peak memory 194080 kb
Host smart-e3db455f-9d52-47a2-8188-b19952622e73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388013849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.388013849
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.1404114384
Short name T721
Test name
Test status
Simulation time 17956297 ps
CPU time 0.59 seconds
Started Jun 13 12:44:43 PM PDT 24
Finished Jun 13 12:44:45 PM PDT 24
Peak memory 193468 kb
Host smart-32325323-031f-4af1-a3d3-d392c30dc4b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404114384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.1404114384
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.2923982086
Short name T822
Test name
Test status
Simulation time 17922146 ps
CPU time 0.65 seconds
Started Jun 13 12:44:43 PM PDT 24
Finished Jun 13 12:44:45 PM PDT 24
Peak memory 193472 kb
Host smart-5a8bc66c-4a4d-43f2-8368-70fd1696e79d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923982086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.2923982086
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.1967245577
Short name T774
Test name
Test status
Simulation time 200016033 ps
CPU time 0.67 seconds
Started Jun 13 12:43:57 PM PDT 24
Finished Jun 13 12:43:58 PM PDT 24
Peak memory 194604 kb
Host smart-28e2164a-182e-4e61-bd2f-e5a5851490ad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967245577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.1967245577
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.3029145133
Short name T89
Test name
Test status
Simulation time 324341289 ps
CPU time 3.03 seconds
Started Jun 13 12:43:58 PM PDT 24
Finished Jun 13 12:44:01 PM PDT 24
Peak memory 196540 kb
Host smart-3b1bdd8b-ca56-46f1-ac10-13aeedd7742b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029145133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.3029145133
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.255085983
Short name T73
Test name
Test status
Simulation time 20754587 ps
CPU time 0.64 seconds
Started Jun 13 12:44:01 PM PDT 24
Finished Jun 13 12:44:01 PM PDT 24
Peak memory 194448 kb
Host smart-90d72537-d741-4aab-baf2-a735c5b5daeb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255085983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.255085983
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2332525468
Short name T798
Test name
Test status
Simulation time 82604099 ps
CPU time 0.79 seconds
Started Jun 13 12:43:54 PM PDT 24
Finished Jun 13 12:43:55 PM PDT 24
Peak memory 197624 kb
Host smart-348f952b-6767-4934-ada4-74274aa22d22
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332525468 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.2332525468
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1911299239
Short name T741
Test name
Test status
Simulation time 14335494 ps
CPU time 0.58 seconds
Started Jun 13 12:43:55 PM PDT 24
Finished Jun 13 12:43:56 PM PDT 24
Peak memory 194320 kb
Host smart-84a6d8a4-0dab-4f19-89e1-16fa3ffdbfc1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911299239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.1911299239
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.2663389321
Short name T743
Test name
Test status
Simulation time 39888552 ps
CPU time 0.59 seconds
Started Jun 13 12:43:58 PM PDT 24
Finished Jun 13 12:43:59 PM PDT 24
Peak memory 194088 kb
Host smart-f7ee9eda-7114-4999-ad42-2cb2a85556a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663389321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.2663389321
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.470224862
Short name T809
Test name
Test status
Simulation time 125787679 ps
CPU time 0.73 seconds
Started Jun 13 12:43:56 PM PDT 24
Finished Jun 13 12:43:57 PM PDT 24
Peak memory 195148 kb
Host smart-8d8e4a09-640c-4aa2-addc-f0198108203e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470224862 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.gpio_same_csr_outstanding.470224862
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.990595287
Short name T808
Test name
Test status
Simulation time 117772853 ps
CPU time 2.32 seconds
Started Jun 13 12:43:55 PM PDT 24
Finished Jun 13 12:43:57 PM PDT 24
Peak memory 197652 kb
Host smart-0c503bc5-ec8b-48bf-9ce9-babf7d21c19a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990595287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.990595287
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3539949766
Short name T836
Test name
Test status
Simulation time 167996493 ps
CPU time 0.89 seconds
Started Jun 13 12:43:53 PM PDT 24
Finished Jun 13 12:43:54 PM PDT 24
Peak memory 196948 kb
Host smart-b527563b-3a64-4347-81a9-a609f47cc24e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539949766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.3539949766
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.2041690848
Short name T812
Test name
Test status
Simulation time 14161546 ps
CPU time 0.64 seconds
Started Jun 13 12:44:44 PM PDT 24
Finished Jun 13 12:44:46 PM PDT 24
Peak memory 194084 kb
Host smart-826a13d8-be31-4fcf-b624-e61963ea9b48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041690848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.2041690848
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.2554106655
Short name T819
Test name
Test status
Simulation time 13230541 ps
CPU time 0.58 seconds
Started Jun 13 12:44:43 PM PDT 24
Finished Jun 13 12:44:44 PM PDT 24
Peak memory 194036 kb
Host smart-35b72cc4-ac99-4331-9d13-4fd22cb0b11d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554106655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.2554106655
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.3617576700
Short name T755
Test name
Test status
Simulation time 22234618 ps
CPU time 0.6 seconds
Started Jun 13 12:44:43 PM PDT 24
Finished Jun 13 12:44:44 PM PDT 24
Peak memory 193368 kb
Host smart-ded1fcee-a803-44a3-b3f2-a18ca881572c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617576700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.3617576700
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.1449552323
Short name T730
Test name
Test status
Simulation time 14637375 ps
CPU time 0.64 seconds
Started Jun 13 12:44:56 PM PDT 24
Finished Jun 13 12:44:58 PM PDT 24
Peak memory 194132 kb
Host smart-4dd436fd-1da1-4b4d-a045-81a0d8c382b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449552323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.1449552323
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.554871755
Short name T760
Test name
Test status
Simulation time 49531451 ps
CPU time 0.58 seconds
Started Jun 13 12:44:43 PM PDT 24
Finished Jun 13 12:44:45 PM PDT 24
Peak memory 193348 kb
Host smart-e911fdfd-9824-4a52-b21f-88b598bf4c1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554871755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.554871755
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.2680544277
Short name T757
Test name
Test status
Simulation time 95059715 ps
CPU time 0.57 seconds
Started Jun 13 12:44:55 PM PDT 24
Finished Jun 13 12:44:57 PM PDT 24
Peak memory 193384 kb
Host smart-cfd1022c-d6f0-4821-8d23-f5a4c8075aa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680544277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.2680544277
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.959267175
Short name T777
Test name
Test status
Simulation time 20003979 ps
CPU time 0.59 seconds
Started Jun 13 12:44:42 PM PDT 24
Finished Jun 13 12:44:43 PM PDT 24
Peak memory 193380 kb
Host smart-225e6092-d718-4a2c-b037-512cd416df20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959267175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.959267175
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.2331350012
Short name T771
Test name
Test status
Simulation time 14233752 ps
CPU time 0.65 seconds
Started Jun 13 12:44:43 PM PDT 24
Finished Jun 13 12:44:45 PM PDT 24
Peak memory 193988 kb
Host smart-f8c0fe0e-c8b5-42b8-a4dd-6d0fe98c21d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331350012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.2331350012
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.2708992206
Short name T770
Test name
Test status
Simulation time 11770203 ps
CPU time 0.6 seconds
Started Jun 13 12:44:56 PM PDT 24
Finished Jun 13 12:44:57 PM PDT 24
Peak memory 194160 kb
Host smart-5e2fdcc7-5885-4a8c-bf6a-30d924894c9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708992206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.2708992206
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.3384033071
Short name T788
Test name
Test status
Simulation time 114543582 ps
CPU time 0.61 seconds
Started Jun 13 12:44:55 PM PDT 24
Finished Jun 13 12:44:56 PM PDT 24
Peak memory 194084 kb
Host smart-a6276c52-f343-4da4-989e-11ca1c92f01b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384033071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.3384033071
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3093180426
Short name T748
Test name
Test status
Simulation time 15997890 ps
CPU time 0.68 seconds
Started Jun 13 12:44:03 PM PDT 24
Finished Jun 13 12:44:04 PM PDT 24
Peak memory 197308 kb
Host smart-de6b3b2d-3742-4536-8335-927f84351181
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093180426 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.3093180426
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.251161087
Short name T813
Test name
Test status
Simulation time 35661304 ps
CPU time 0.61 seconds
Started Jun 13 12:44:03 PM PDT 24
Finished Jun 13 12:44:04 PM PDT 24
Peak memory 194420 kb
Host smart-aa62a34f-38be-43af-9064-7ec284f83e25
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251161087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_
csr_rw.251161087
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.3938170180
Short name T801
Test name
Test status
Simulation time 47174751 ps
CPU time 0.66 seconds
Started Jun 13 12:44:03 PM PDT 24
Finished Jun 13 12:44:04 PM PDT 24
Peak memory 194008 kb
Host smart-82f7ff85-fa86-4bab-9632-2dc65c104206
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938170180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.3938170180
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.1242013446
Short name T92
Test name
Test status
Simulation time 127821969 ps
CPU time 0.68 seconds
Started Jun 13 12:44:03 PM PDT 24
Finished Jun 13 12:44:04 PM PDT 24
Peak memory 194568 kb
Host smart-726379f6-a7cf-46c2-9b3a-b40915cd4da4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242013446 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.1242013446
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.883769783
Short name T714
Test name
Test status
Simulation time 45849869 ps
CPU time 1.23 seconds
Started Jun 13 12:44:01 PM PDT 24
Finished Jun 13 12:44:03 PM PDT 24
Peak memory 197780 kb
Host smart-3a80c9d6-826a-482b-8a05-a47c92ac8987
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883769783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.883769783
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.2490027664
Short name T802
Test name
Test status
Simulation time 87016367 ps
CPU time 0.94 seconds
Started Jun 13 12:44:02 PM PDT 24
Finished Jun 13 12:44:03 PM PDT 24
Peak memory 196912 kb
Host smart-99f55b2e-67d6-49e2-9147-c55969525ed6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490027664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.2490027664
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2662466682
Short name T742
Test name
Test status
Simulation time 142694750 ps
CPU time 1.83 seconds
Started Jun 13 12:44:03 PM PDT 24
Finished Jun 13 12:44:06 PM PDT 24
Peak memory 197812 kb
Host smart-4a888707-5813-49b0-b4b7-5df1be307e63
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662466682 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.2662466682
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2410297694
Short name T99
Test name
Test status
Simulation time 46194316 ps
CPU time 0.63 seconds
Started Jun 13 12:44:02 PM PDT 24
Finished Jun 13 12:44:03 PM PDT 24
Peak memory 195296 kb
Host smart-7928219f-7993-495c-9af5-c11c921cc0c0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410297694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.2410297694
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.2426790884
Short name T726
Test name
Test status
Simulation time 11058370 ps
CPU time 0.64 seconds
Started Jun 13 12:44:03 PM PDT 24
Finished Jun 13 12:44:04 PM PDT 24
Peak memory 193480 kb
Host smart-587da04c-bd41-4f09-91e6-98c2d3e5669b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426790884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.2426790884
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.2699263902
Short name T826
Test name
Test status
Simulation time 16909269 ps
CPU time 0.68 seconds
Started Jun 13 12:44:02 PM PDT 24
Finished Jun 13 12:44:03 PM PDT 24
Peak memory 194644 kb
Host smart-23c03f1b-70e4-4916-8931-29e8e9614dac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699263902 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.2699263902
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.579306487
Short name T728
Test name
Test status
Simulation time 45612533 ps
CPU time 1.29 seconds
Started Jun 13 12:44:03 PM PDT 24
Finished Jun 13 12:44:05 PM PDT 24
Peak memory 197760 kb
Host smart-9a1ce59f-3df9-4b62-be94-eaed96351768
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579306487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.579306487
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.81341352
Short name T44
Test name
Test status
Simulation time 210356903 ps
CPU time 1.17 seconds
Started Jun 13 12:44:04 PM PDT 24
Finished Jun 13 12:44:06 PM PDT 24
Peak memory 197820 kb
Host smart-d859d8d7-6270-4ca9-8196-522d9e430746
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81341352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
6.gpio_tl_intg_err.81341352
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.3715699138
Short name T731
Test name
Test status
Simulation time 33331764 ps
CPU time 0.91 seconds
Started Jun 13 12:44:03 PM PDT 24
Finished Jun 13 12:44:04 PM PDT 24
Peak memory 197656 kb
Host smart-f1d1fb11-5227-484a-93bb-ecab5afa071d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715699138 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.3715699138
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.4036236023
Short name T79
Test name
Test status
Simulation time 37044197 ps
CPU time 0.6 seconds
Started Jun 13 12:44:02 PM PDT 24
Finished Jun 13 12:44:03 PM PDT 24
Peak memory 193052 kb
Host smart-c1753ff2-708c-478d-89fc-6c556c05f558
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036236023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.4036236023
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.2792602743
Short name T807
Test name
Test status
Simulation time 19948795 ps
CPU time 0.63 seconds
Started Jun 13 12:44:13 PM PDT 24
Finished Jun 13 12:44:14 PM PDT 24
Peak memory 193520 kb
Host smart-4aae77c6-4eaf-4aa4-a72b-58c745e3eab9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792602743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.2792602743
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3972795910
Short name T94
Test name
Test status
Simulation time 21275892 ps
CPU time 0.63 seconds
Started Jun 13 12:44:03 PM PDT 24
Finished Jun 13 12:44:04 PM PDT 24
Peak memory 194424 kb
Host smart-7413398d-0022-4a55-8752-4a76c120c857
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972795910 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.3972795910
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.800171730
Short name T750
Test name
Test status
Simulation time 322969111 ps
CPU time 1.93 seconds
Started Jun 13 12:44:03 PM PDT 24
Finished Jun 13 12:44:05 PM PDT 24
Peak memory 197764 kb
Host smart-08257119-9271-4352-978d-82ab8bce5cdd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800171730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.800171730
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.4079339157
Short name T762
Test name
Test status
Simulation time 78096996 ps
CPU time 1.19 seconds
Started Jun 13 12:44:02 PM PDT 24
Finished Jun 13 12:44:04 PM PDT 24
Peak memory 197764 kb
Host smart-139e6838-eaaf-4741-be43-06caf1fba499
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079339157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.4079339157
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3453055205
Short name T740
Test name
Test status
Simulation time 120059064 ps
CPU time 0.89 seconds
Started Jun 13 12:44:08 PM PDT 24
Finished Jun 13 12:44:10 PM PDT 24
Peak memory 197504 kb
Host smart-eb976604-d7ad-40fb-8647-2549ccb9ffcf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453055205 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.3453055205
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.443829841
Short name T838
Test name
Test status
Simulation time 13753431 ps
CPU time 0.6 seconds
Started Jun 13 12:44:08 PM PDT 24
Finished Jun 13 12:44:09 PM PDT 24
Peak memory 194668 kb
Host smart-863eb8c8-169d-4dd7-8ba9-5f54861e70a6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443829841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_
csr_rw.443829841
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.3469596461
Short name T768
Test name
Test status
Simulation time 12167610 ps
CPU time 0.58 seconds
Started Jun 13 12:44:09 PM PDT 24
Finished Jun 13 12:44:10 PM PDT 24
Peak memory 193388 kb
Host smart-84a17477-c4ed-476a-8b23-c191e653a3cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469596461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.3469596461
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1138250721
Short name T96
Test name
Test status
Simulation time 122359413 ps
CPU time 0.75 seconds
Started Jun 13 12:44:09 PM PDT 24
Finished Jun 13 12:44:10 PM PDT 24
Peak memory 195540 kb
Host smart-a7c98b04-22eb-473d-bb0a-a8c743407c9c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138250721 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.1138250721
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.3570264672
Short name T797
Test name
Test status
Simulation time 178107689 ps
CPU time 2.62 seconds
Started Jun 13 12:44:08 PM PDT 24
Finished Jun 13 12:44:11 PM PDT 24
Peak memory 197800 kb
Host smart-49377aa3-b60b-4531-86e4-198bee36cf11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570264672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.3570264672
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2832313566
Short name T43
Test name
Test status
Simulation time 90733893 ps
CPU time 1.19 seconds
Started Jun 13 12:44:07 PM PDT 24
Finished Jun 13 12:44:08 PM PDT 24
Peak memory 197776 kb
Host smart-400f8ba4-5f66-4d8b-91e1-3a5baefe1306
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832313566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.2832313566
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.4071589224
Short name T720
Test name
Test status
Simulation time 385080666 ps
CPU time 1.62 seconds
Started Jun 13 12:44:13 PM PDT 24
Finished Jun 13 12:44:15 PM PDT 24
Peak memory 197872 kb
Host smart-ca9dbcc3-ccd9-485a-828a-c4150b0dc8a0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071589224 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.4071589224
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.4078263248
Short name T82
Test name
Test status
Simulation time 17171475 ps
CPU time 0.6 seconds
Started Jun 13 12:44:07 PM PDT 24
Finished Jun 13 12:44:08 PM PDT 24
Peak memory 194064 kb
Host smart-655ddff0-0fa1-4e2d-97e4-312a7cd7e6e0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078263248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.4078263248
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.1087082690
Short name T792
Test name
Test status
Simulation time 37997876 ps
CPU time 0.57 seconds
Started Jun 13 12:44:09 PM PDT 24
Finished Jun 13 12:44:10 PM PDT 24
Peak memory 193324 kb
Host smart-90f34f85-5588-4a06-be04-cd31ec6d7f08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087082690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.1087082690
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2590459109
Short name T97
Test name
Test status
Simulation time 72226594 ps
CPU time 0.89 seconds
Started Jun 13 12:44:08 PM PDT 24
Finished Jun 13 12:44:10 PM PDT 24
Peak memory 196100 kb
Host smart-45883c51-ba53-403d-b680-739a3ca82669
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590459109 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.2590459109
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.654178218
Short name T775
Test name
Test status
Simulation time 544895395 ps
CPU time 2.87 seconds
Started Jun 13 12:44:07 PM PDT 24
Finished Jun 13 12:44:10 PM PDT 24
Peak memory 197712 kb
Host smart-cb4e0635-c7e7-42f5-b983-4b6abdbc1c29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654178218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.654178218
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1000780406
Short name T816
Test name
Test status
Simulation time 810361522 ps
CPU time 1.5 seconds
Started Jun 13 12:44:11 PM PDT 24
Finished Jun 13 12:44:13 PM PDT 24
Peak memory 197820 kb
Host smart-81953534-bac2-4e09-b0e0-9d046773b265
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000780406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.1000780406
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.536413424
Short name T679
Test name
Test status
Simulation time 29075270 ps
CPU time 0.57 seconds
Started Jun 13 12:45:42 PM PDT 24
Finished Jun 13 12:45:43 PM PDT 24
Peak memory 193756 kb
Host smart-ad3bd869-7e4c-4599-b46f-9187c0533cea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536413424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.536413424
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.2086330927
Short name T364
Test name
Test status
Simulation time 42374387 ps
CPU time 0.91 seconds
Started Jun 13 12:45:46 PM PDT 24
Finished Jun 13 12:45:47 PM PDT 24
Peak memory 197152 kb
Host smart-c45d98ad-496b-49d2-b9e6-8cc77d7f1b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086330927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.2086330927
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.3045192601
Short name T706
Test name
Test status
Simulation time 436056656 ps
CPU time 3.72 seconds
Started Jun 13 12:45:34 PM PDT 24
Finished Jun 13 12:45:38 PM PDT 24
Peak memory 195648 kb
Host smart-96e9fd01-af9b-466c-bbfe-5573ad9b0ff9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045192601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.3045192601
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.405984459
Short name T585
Test name
Test status
Simulation time 204606686 ps
CPU time 0.72 seconds
Started Jun 13 12:45:40 PM PDT 24
Finished Jun 13 12:45:42 PM PDT 24
Peak memory 194680 kb
Host smart-450e85a5-698c-4e55-a357-44e07deb56ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405984459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.405984459
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.1086079489
Short name T592
Test name
Test status
Simulation time 193456599 ps
CPU time 1.37 seconds
Started Jun 13 12:45:33 PM PDT 24
Finished Jun 13 12:45:35 PM PDT 24
Peak memory 195744 kb
Host smart-07d98d89-dee9-42ee-8f40-9770c29adf78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086079489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.1086079489
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.987646451
Short name T50
Test name
Test status
Simulation time 148469627 ps
CPU time 1.69 seconds
Started Jun 13 12:45:33 PM PDT 24
Finished Jun 13 12:45:36 PM PDT 24
Peak memory 197964 kb
Host smart-fef930e3-86a0-4afe-b0ea-22b5241b4974
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987646451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.gpio_intr_with_filter_rand_intr_event.987646451
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.1587085322
Short name T446
Test name
Test status
Simulation time 137053170 ps
CPU time 1.24 seconds
Started Jun 13 12:45:33 PM PDT 24
Finished Jun 13 12:45:35 PM PDT 24
Peak memory 195872 kb
Host smart-55b62010-d7fd-44c7-a639-60e3bb624863
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587085322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
1587085322
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.825572279
Short name T644
Test name
Test status
Simulation time 90010577 ps
CPU time 1.06 seconds
Started Jun 13 12:45:32 PM PDT 24
Finished Jun 13 12:45:33 PM PDT 24
Peak memory 195756 kb
Host smart-5603cc06-0e45-4083-9059-fd66485edd53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825572279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.825572279
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.1184580081
Short name T134
Test name
Test status
Simulation time 94648346 ps
CPU time 0.77 seconds
Started Jun 13 12:45:41 PM PDT 24
Finished Jun 13 12:45:42 PM PDT 24
Peak memory 195340 kb
Host smart-a694362c-a59a-4832-bd49-10f7fad5467e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184580081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.1184580081
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.1570009267
Short name T641
Test name
Test status
Simulation time 61511692 ps
CPU time 2.73 seconds
Started Jun 13 12:45:36 PM PDT 24
Finished Jun 13 12:45:39 PM PDT 24
Peak memory 197908 kb
Host smart-e7d0dd58-7643-45a6-8a00-10fadb8714ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570009267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.1570009267
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.3545192492
Short name T46
Test name
Test status
Simulation time 322787255 ps
CPU time 0.91 seconds
Started Jun 13 12:45:40 PM PDT 24
Finished Jun 13 12:45:42 PM PDT 24
Peak memory 214752 kb
Host smart-29589f2e-9d8f-448d-8fb4-60b66236796b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545192492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.3545192492
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.3791025248
Short name T524
Test name
Test status
Simulation time 67799235 ps
CPU time 1.22 seconds
Started Jun 13 12:45:35 PM PDT 24
Finished Jun 13 12:45:37 PM PDT 24
Peak memory 195412 kb
Host smart-2338cdba-4290-4abd-a68b-0d0e282eeb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791025248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.3791025248
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.992445971
Short name T424
Test name
Test status
Simulation time 321741406 ps
CPU time 1.29 seconds
Started Jun 13 12:45:33 PM PDT 24
Finished Jun 13 12:45:35 PM PDT 24
Peak memory 196788 kb
Host smart-74c837f9-1e6b-4b5c-b688-4488cd26cdb7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992445971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.992445971
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.3846154714
Short name T2
Test name
Test status
Simulation time 7532405577 ps
CPU time 81.12 seconds
Started Jun 13 12:45:43 PM PDT 24
Finished Jun 13 12:47:04 PM PDT 24
Peak memory 191676 kb
Host smart-8c106656-49e2-4cd4-91f9-86429d6478d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846154714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.3846154714
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.1111229753
Short name T294
Test name
Test status
Simulation time 16123725 ps
CPU time 0.6 seconds
Started Jun 13 12:45:39 PM PDT 24
Finished Jun 13 12:45:40 PM PDT 24
Peak memory 193772 kb
Host smart-0b8fe6fc-5239-4a61-a565-a3264bc895df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111229753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.1111229753
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.1313857292
Short name T497
Test name
Test status
Simulation time 67649482 ps
CPU time 0.66 seconds
Started Jun 13 12:45:46 PM PDT 24
Finished Jun 13 12:45:46 PM PDT 24
Peak memory 194668 kb
Host smart-0eb8baa6-aaed-40e7-a9ff-5075fc8af051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313857292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.1313857292
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.817290993
Short name T209
Test name
Test status
Simulation time 1192687419 ps
CPU time 13.94 seconds
Started Jun 13 12:45:40 PM PDT 24
Finished Jun 13 12:45:55 PM PDT 24
Peak memory 197012 kb
Host smart-3504c6d4-5145-468c-8f2a-b586a79c103f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817290993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stress
.817290993
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.1244493538
Short name T239
Test name
Test status
Simulation time 74763752 ps
CPU time 0.9 seconds
Started Jun 13 12:45:45 PM PDT 24
Finished Jun 13 12:45:46 PM PDT 24
Peak memory 196988 kb
Host smart-2c207a99-b617-4ebc-834b-99e4edff8047
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244493538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.1244493538
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.408093551
Short name T373
Test name
Test status
Simulation time 41013649 ps
CPU time 1.13 seconds
Started Jun 13 12:45:44 PM PDT 24
Finished Jun 13 12:45:45 PM PDT 24
Peak memory 196548 kb
Host smart-59a54010-323a-4064-9e4c-052db6028283
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408093551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.408093551
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.4139509101
Short name T258
Test name
Test status
Simulation time 37836706 ps
CPU time 1.55 seconds
Started Jun 13 12:45:41 PM PDT 24
Finished Jun 13 12:45:43 PM PDT 24
Peak memory 196260 kb
Host smart-e78f040a-f9cc-4fe1-a5f9-e20db462859e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139509101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.4139509101
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.429700653
Short name T653
Test name
Test status
Simulation time 401879989 ps
CPU time 2.81 seconds
Started Jun 13 12:45:38 PM PDT 24
Finished Jun 13 12:45:41 PM PDT 24
Peak memory 197048 kb
Host smart-24b2a7c1-87f7-4702-9bf1-69796c3de9ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429700653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.429700653
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.1915002105
Short name T120
Test name
Test status
Simulation time 64188639 ps
CPU time 0.88 seconds
Started Jun 13 12:45:41 PM PDT 24
Finished Jun 13 12:45:42 PM PDT 24
Peak memory 196992 kb
Host smart-cd8ab18f-97dd-4792-ba6e-2142d65e52d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915002105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.1915002105
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.3207931689
Short name T186
Test name
Test status
Simulation time 17137658 ps
CPU time 0.64 seconds
Started Jun 13 12:45:45 PM PDT 24
Finished Jun 13 12:45:46 PM PDT 24
Peak memory 194120 kb
Host smart-d32cc20b-3921-4f4d-aff1-856fd73139f4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207931689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.3207931689
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.1292123265
Short name T145
Test name
Test status
Simulation time 528888677 ps
CPU time 4.26 seconds
Started Jun 13 12:45:40 PM PDT 24
Finished Jun 13 12:45:45 PM PDT 24
Peak memory 197840 kb
Host smart-e1a618ac-5b01-4bbf-a10c-2477dbcd7da6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292123265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.1292123265
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_smoke.3629495218
Short name T268
Test name
Test status
Simulation time 346410848 ps
CPU time 1.42 seconds
Started Jun 13 12:45:45 PM PDT 24
Finished Jun 13 12:45:47 PM PDT 24
Peak memory 197924 kb
Host smart-b68a679f-47c0-45aa-ac76-ff2860def7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629495218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.3629495218
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.922600926
Short name T388
Test name
Test status
Simulation time 45229560 ps
CPU time 0.97 seconds
Started Jun 13 12:45:39 PM PDT 24
Finished Jun 13 12:45:41 PM PDT 24
Peak memory 196864 kb
Host smart-9aa59513-a165-4a9a-a7d8-bad9b3cffa59
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922600926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.922600926
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.3013066065
Short name T19
Test name
Test status
Simulation time 13324223791 ps
CPU time 171.3 seconds
Started Jun 13 12:45:45 PM PDT 24
Finished Jun 13 12:48:37 PM PDT 24
Peak memory 198004 kb
Host smart-43474d7c-f346-4c4f-93f4-5df0077eb3dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013066065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.3013066065
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.1456320163
Short name T453
Test name
Test status
Simulation time 33063544 ps
CPU time 0.57 seconds
Started Jun 13 12:46:35 PM PDT 24
Finished Jun 13 12:46:35 PM PDT 24
Peak memory 193764 kb
Host smart-720041c6-6bab-44a0-91e5-ec893d18040e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456320163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.1456320163
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.1457452632
Short name T104
Test name
Test status
Simulation time 22180943 ps
CPU time 0.75 seconds
Started Jun 13 12:46:22 PM PDT 24
Finished Jun 13 12:46:23 PM PDT 24
Peak memory 195132 kb
Host smart-25c7c7a2-1635-48d5-80ac-a7cc7c7389f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457452632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.1457452632
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.1778525431
Short name T543
Test name
Test status
Simulation time 1140937748 ps
CPU time 21.86 seconds
Started Jun 13 12:46:22 PM PDT 24
Finished Jun 13 12:46:44 PM PDT 24
Peak memory 195448 kb
Host smart-5d875bb4-5367-456e-b062-c26feaa135aa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778525431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.1778525431
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.3740420230
Short name T386
Test name
Test status
Simulation time 343211793 ps
CPU time 1.16 seconds
Started Jun 13 12:46:21 PM PDT 24
Finished Jun 13 12:46:22 PM PDT 24
Peak memory 197852 kb
Host smart-77718bd0-7c1d-45a7-aecf-c5b3dc99d500
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740420230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.3740420230
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.2031140752
Short name T276
Test name
Test status
Simulation time 78144403 ps
CPU time 1.38 seconds
Started Jun 13 12:46:23 PM PDT 24
Finished Jun 13 12:46:25 PM PDT 24
Peak memory 198016 kb
Host smart-465e2eb8-8991-471d-98f2-88d24a616e07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031140752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.2031140752
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.2083730048
Short name T189
Test name
Test status
Simulation time 260928587 ps
CPU time 2.86 seconds
Started Jun 13 12:46:22 PM PDT 24
Finished Jun 13 12:46:26 PM PDT 24
Peak memory 197984 kb
Host smart-dee49cef-6229-486c-a596-eca871ed0934
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083730048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.2083730048
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.1022618539
Short name T707
Test name
Test status
Simulation time 29618968 ps
CPU time 0.86 seconds
Started Jun 13 12:46:24 PM PDT 24
Finished Jun 13 12:46:26 PM PDT 24
Peak memory 194248 kb
Host smart-6ef24014-e687-48f5-87c4-c2cf7b091e84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022618539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.1022618539
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.4055425474
Short name T516
Test name
Test status
Simulation time 252789734 ps
CPU time 1.27 seconds
Started Jun 13 12:46:21 PM PDT 24
Finished Jun 13 12:46:23 PM PDT 24
Peak memory 196968 kb
Host smart-36036153-f014-4d30-92c9-0e275d94179d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055425474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.4055425474
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.4135408167
Short name T558
Test name
Test status
Simulation time 85563331 ps
CPU time 0.97 seconds
Started Jun 13 12:46:22 PM PDT 24
Finished Jun 13 12:46:24 PM PDT 24
Peak memory 195908 kb
Host smart-6aff8e7b-5396-49f2-8112-68144ba95427
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135408167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.4135408167
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.4012526254
Short name T10
Test name
Test status
Simulation time 585550801 ps
CPU time 2.49 seconds
Started Jun 13 12:46:24 PM PDT 24
Finished Jun 13 12:46:27 PM PDT 24
Peak memory 197912 kb
Host smart-f485758f-8db9-4ed3-bda5-baf81baf7c78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012526254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.4012526254
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.207706982
Short name T288
Test name
Test status
Simulation time 45285037 ps
CPU time 0.96 seconds
Started Jun 13 12:46:23 PM PDT 24
Finished Jun 13 12:46:24 PM PDT 24
Peak memory 196100 kb
Host smart-78167e6b-f80e-4587-8ed5-8d0cfd6dbd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207706982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.207706982
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.2572335024
Short name T703
Test name
Test status
Simulation time 226609490 ps
CPU time 1.16 seconds
Started Jun 13 12:46:23 PM PDT 24
Finished Jun 13 12:46:24 PM PDT 24
Peak memory 195720 kb
Host smart-299fdbb4-5e61-42c1-aee3-1792cb6d3599
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572335024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.2572335024
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.1490067951
Short name T532
Test name
Test status
Simulation time 36305923167 ps
CPU time 85.16 seconds
Started Jun 13 12:46:35 PM PDT 24
Finished Jun 13 12:48:01 PM PDT 24
Peak memory 198032 kb
Host smart-878d0822-2521-46d9-8cea-4078c66b637a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490067951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.1490067951
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.690181708
Short name T342
Test name
Test status
Simulation time 13673394 ps
CPU time 0.58 seconds
Started Jun 13 12:46:32 PM PDT 24
Finished Jun 13 12:46:33 PM PDT 24
Peak memory 194452 kb
Host smart-15c624f7-e7a8-489a-968e-a0313f8a314a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690181708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.690181708
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.1799260885
Short name T176
Test name
Test status
Simulation time 80007011 ps
CPU time 0.89 seconds
Started Jun 13 12:46:36 PM PDT 24
Finished Jun 13 12:46:37 PM PDT 24
Peak memory 195108 kb
Host smart-c899afbd-b5d2-4e8e-a916-b91cf9ca2df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799260885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.1799260885
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.2328806412
Short name T548
Test name
Test status
Simulation time 404894165 ps
CPU time 14.94 seconds
Started Jun 13 12:46:32 PM PDT 24
Finished Jun 13 12:46:47 PM PDT 24
Peak memory 196948 kb
Host smart-ef1584a7-04f3-4d80-83b3-a3ad53c7b9f8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328806412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.2328806412
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.2595899267
Short name T115
Test name
Test status
Simulation time 119338151 ps
CPU time 0.79 seconds
Started Jun 13 12:46:35 PM PDT 24
Finished Jun 13 12:46:36 PM PDT 24
Peak memory 195620 kb
Host smart-b6152de1-cfb5-4cdb-a3b4-23576e35beb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595899267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.2595899267
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.86347449
Short name T473
Test name
Test status
Simulation time 121161100 ps
CPU time 0.84 seconds
Started Jun 13 12:46:28 PM PDT 24
Finished Jun 13 12:46:29 PM PDT 24
Peak memory 196124 kb
Host smart-5eccd949-cdee-4751-a07a-3c57ee083c25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86347449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.86347449
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.1324854073
Short name T279
Test name
Test status
Simulation time 50508345 ps
CPU time 1.18 seconds
Started Jun 13 12:46:29 PM PDT 24
Finished Jun 13 12:46:31 PM PDT 24
Peak memory 197300 kb
Host smart-3265d1e6-e4c0-4e27-8d1b-9910564da435
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324854073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.1324854073
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.4143782206
Short name T502
Test name
Test status
Simulation time 107595328 ps
CPU time 1.13 seconds
Started Jun 13 12:46:32 PM PDT 24
Finished Jun 13 12:46:34 PM PDT 24
Peak memory 195600 kb
Host smart-64e52c4b-fd9a-49ab-8918-bd14fa4856ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143782206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.4143782206
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.4192359812
Short name T619
Test name
Test status
Simulation time 27638135 ps
CPU time 1.05 seconds
Started Jun 13 12:46:31 PM PDT 24
Finished Jun 13 12:46:33 PM PDT 24
Peak memory 195932 kb
Host smart-6044ff21-7ee8-4a32-b89f-9aa5f927a009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192359812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.4192359812
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.4288421117
Short name T65
Test name
Test status
Simulation time 30183205 ps
CPU time 0.91 seconds
Started Jun 13 12:46:31 PM PDT 24
Finished Jun 13 12:46:33 PM PDT 24
Peak memory 195740 kb
Host smart-23829c43-6d75-4853-a298-676036e9c514
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288421117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.4288421117
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.4240766062
Short name T359
Test name
Test status
Simulation time 1438836146 ps
CPU time 4.47 seconds
Started Jun 13 12:46:35 PM PDT 24
Finished Jun 13 12:46:40 PM PDT 24
Peak memory 197928 kb
Host smart-bf8b99a8-89bb-4587-8b9d-4e9550a18efe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240766062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.4240766062
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.1622851147
Short name T426
Test name
Test status
Simulation time 134647498 ps
CPU time 1.03 seconds
Started Jun 13 12:46:30 PM PDT 24
Finished Jun 13 12:46:32 PM PDT 24
Peak memory 195480 kb
Host smart-03fee387-4a5c-454d-9253-dc72cbcc4a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622851147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.1622851147
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.2822862772
Short name T306
Test name
Test status
Simulation time 197694816 ps
CPU time 1.06 seconds
Started Jun 13 12:46:32 PM PDT 24
Finished Jun 13 12:46:34 PM PDT 24
Peak memory 195716 kb
Host smart-6b8c0fa1-e78c-4483-a2b5-f0f78851b3c7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822862772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.2822862772
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.1246651778
Short name T508
Test name
Test status
Simulation time 21230174962 ps
CPU time 119.08 seconds
Started Jun 13 12:46:31 PM PDT 24
Finished Jun 13 12:48:30 PM PDT 24
Peak memory 197992 kb
Host smart-6dd2a2fa-ffae-4bd2-b7ec-8e2443d340de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246651778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.1246651778
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.2009645773
Short name T475
Test name
Test status
Simulation time 14074714 ps
CPU time 0.59 seconds
Started Jun 13 12:46:36 PM PDT 24
Finished Jun 13 12:46:37 PM PDT 24
Peak memory 193760 kb
Host smart-e1e56eb3-8a62-4a93-aabd-1e6ba3848b91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009645773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.2009645773
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.652705421
Short name T493
Test name
Test status
Simulation time 93697528 ps
CPU time 0.76 seconds
Started Jun 13 12:46:28 PM PDT 24
Finished Jun 13 12:46:29 PM PDT 24
Peak memory 195168 kb
Host smart-de2a8148-d40d-4c4f-825a-f598a88c3c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652705421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.652705421
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.197059253
Short name T140
Test name
Test status
Simulation time 2013798126 ps
CPU time 26.04 seconds
Started Jun 13 12:46:35 PM PDT 24
Finished Jun 13 12:47:02 PM PDT 24
Peak memory 196756 kb
Host smart-2bf85dda-7dcd-4d17-966c-cd5b0c744195
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197059253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stres
s.197059253
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.3626706065
Short name T305
Test name
Test status
Simulation time 261077133 ps
CPU time 0.96 seconds
Started Jun 13 12:46:38 PM PDT 24
Finished Jun 13 12:46:39 PM PDT 24
Peak memory 196992 kb
Host smart-d68e5ab5-aa6d-4284-bfe5-bfcb4d19d8b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626706065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.3626706065
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.2042643724
Short name T113
Test name
Test status
Simulation time 17734628 ps
CPU time 0.69 seconds
Started Jun 13 12:46:32 PM PDT 24
Finished Jun 13 12:46:34 PM PDT 24
Peak memory 194852 kb
Host smart-62920b4d-1caf-458f-8cde-b63887c3e77f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042643724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.2042643724
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.1345577182
Short name T389
Test name
Test status
Simulation time 258281378 ps
CPU time 1.19 seconds
Started Jun 13 12:46:32 PM PDT 24
Finished Jun 13 12:46:34 PM PDT 24
Peak memory 197476 kb
Host smart-93c156aa-4288-4191-b87a-1fc502918933
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345577182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.1345577182
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.3986315352
Short name T544
Test name
Test status
Simulation time 409918941 ps
CPU time 2.14 seconds
Started Jun 13 12:46:30 PM PDT 24
Finished Jun 13 12:46:33 PM PDT 24
Peak memory 196120 kb
Host smart-4aa4d701-e078-4e43-af1d-beedb7f39547
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986315352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.3986315352
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.2073734548
Short name T378
Test name
Test status
Simulation time 271551033 ps
CPU time 1.25 seconds
Started Jun 13 12:46:31 PM PDT 24
Finished Jun 13 12:46:33 PM PDT 24
Peak memory 196032 kb
Host smart-69689690-93bf-4806-b019-136a57ffb65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073734548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.2073734548
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.3544337777
Short name T51
Test name
Test status
Simulation time 29027771 ps
CPU time 1.13 seconds
Started Jun 13 12:46:35 PM PDT 24
Finished Jun 13 12:46:37 PM PDT 24
Peak memory 195832 kb
Host smart-46e7a3c6-99f6-41e7-a2cd-d91b153e1481
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544337777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.3544337777
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.1851365069
Short name T647
Test name
Test status
Simulation time 434535518 ps
CPU time 5.09 seconds
Started Jun 13 12:46:40 PM PDT 24
Finished Jun 13 12:46:46 PM PDT 24
Peak memory 197988 kb
Host smart-98a41cb8-5dce-4208-b49c-99646e04b6a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851365069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.1851365069
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.1958314519
Short name T608
Test name
Test status
Simulation time 56298624 ps
CPU time 0.82 seconds
Started Jun 13 12:46:32 PM PDT 24
Finished Jun 13 12:46:34 PM PDT 24
Peak memory 195776 kb
Host smart-78790bcb-b481-4651-81d1-8da5c6a49248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958314519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.1958314519
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.3494330646
Short name T351
Test name
Test status
Simulation time 89239386 ps
CPU time 1.32 seconds
Started Jun 13 12:46:31 PM PDT 24
Finished Jun 13 12:46:33 PM PDT 24
Peak memory 196728 kb
Host smart-a7bc90cd-8114-4cef-92d2-104c14b03164
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494330646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.3494330646
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.2532050218
Short name T155
Test name
Test status
Simulation time 6412346523 ps
CPU time 153.18 seconds
Started Jun 13 12:46:39 PM PDT 24
Finished Jun 13 12:49:13 PM PDT 24
Peak memory 198076 kb
Host smart-7eff87c8-a697-47d0-b789-5c2bdad0fc52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532050218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.2532050218
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.3174612351
Short name T552
Test name
Test status
Simulation time 18784741 ps
CPU time 0.58 seconds
Started Jun 13 12:46:37 PM PDT 24
Finished Jun 13 12:46:38 PM PDT 24
Peak memory 194460 kb
Host smart-c531360b-28ea-4488-be26-d32007767a58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174612351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.3174612351
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.599275669
Short name T158
Test name
Test status
Simulation time 18584519 ps
CPU time 0.73 seconds
Started Jun 13 12:46:35 PM PDT 24
Finished Jun 13 12:46:37 PM PDT 24
Peak memory 194008 kb
Host smart-dc85e930-7e5e-4639-8ed1-81544c8a1535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599275669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.599275669
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.1147454474
Short name T633
Test name
Test status
Simulation time 356347188 ps
CPU time 9.58 seconds
Started Jun 13 12:46:38 PM PDT 24
Finished Jun 13 12:46:48 PM PDT 24
Peak memory 195500 kb
Host smart-5db5bf0d-d726-4f94-94e8-026103cfbf43
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147454474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.1147454474
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.284482197
Short name T318
Test name
Test status
Simulation time 76013283 ps
CPU time 0.9 seconds
Started Jun 13 12:46:38 PM PDT 24
Finished Jun 13 12:46:39 PM PDT 24
Peak memory 196008 kb
Host smart-2b84337e-b6a4-4ca5-a0e0-fbf782ed6bb4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284482197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.284482197
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.2620287078
Short name T671
Test name
Test status
Simulation time 53598655 ps
CPU time 1.33 seconds
Started Jun 13 12:46:38 PM PDT 24
Finished Jun 13 12:46:40 PM PDT 24
Peak memory 195784 kb
Host smart-129855c3-f1ca-4366-b80e-0e312e5203cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620287078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.2620287078
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.1740581826
Short name T170
Test name
Test status
Simulation time 102137618 ps
CPU time 2.24 seconds
Started Jun 13 12:46:37 PM PDT 24
Finished Jun 13 12:46:39 PM PDT 24
Peak memory 197960 kb
Host smart-d4a8547b-f109-4d13-aa7a-9f91e79a1e9d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740581826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.1740581826
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.723243560
Short name T536
Test name
Test status
Simulation time 48757364 ps
CPU time 1.58 seconds
Started Jun 13 12:46:40 PM PDT 24
Finished Jun 13 12:46:42 PM PDT 24
Peak memory 196068 kb
Host smart-8ea64c95-a1d5-4383-84a0-b487854c1376
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723243560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger.
723243560
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.1457192245
Short name T230
Test name
Test status
Simulation time 104080629 ps
CPU time 1.16 seconds
Started Jun 13 12:46:38 PM PDT 24
Finished Jun 13 12:46:39 PM PDT 24
Peak memory 196696 kb
Host smart-547a40af-d4a4-43be-b574-a604e7acc2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457192245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.1457192245
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.3892408893
Short name T478
Test name
Test status
Simulation time 30382299 ps
CPU time 0.71 seconds
Started Jun 13 12:46:38 PM PDT 24
Finished Jun 13 12:46:39 PM PDT 24
Peak memory 195172 kb
Host smart-db991748-1989-4a47-99c7-a1e60f811442
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892408893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.3892408893
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.2730208517
Short name T636
Test name
Test status
Simulation time 262076796 ps
CPU time 2.04 seconds
Started Jun 13 12:46:39 PM PDT 24
Finished Jun 13 12:46:42 PM PDT 24
Peak memory 197908 kb
Host smart-3568d7bb-8208-462e-8fbd-81c6e7dbd692
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730208517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.2730208517
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.2420826177
Short name T509
Test name
Test status
Simulation time 152019218 ps
CPU time 1.18 seconds
Started Jun 13 12:46:38 PM PDT 24
Finished Jun 13 12:46:39 PM PDT 24
Peak memory 196488 kb
Host smart-0af151bf-02a6-4737-af0a-b1dce4f2347c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420826177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.2420826177
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.1993457904
Short name T240
Test name
Test status
Simulation time 104426847 ps
CPU time 0.92 seconds
Started Jun 13 12:46:38 PM PDT 24
Finished Jun 13 12:46:40 PM PDT 24
Peak memory 195256 kb
Host smart-a5a23ed5-bc7a-407a-888f-db1132de0d73
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993457904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.1993457904
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.2491744715
Short name T527
Test name
Test status
Simulation time 27929935638 ps
CPU time 186.21 seconds
Started Jun 13 12:46:40 PM PDT 24
Finished Jun 13 12:49:47 PM PDT 24
Peak memory 198096 kb
Host smart-ebaa574c-60f0-4910-a36d-bf8dc5d0be3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491744715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.2491744715
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.56388180
Short name T58
Test name
Test status
Simulation time 64525059915 ps
CPU time 1387.05 seconds
Started Jun 13 12:46:39 PM PDT 24
Finished Jun 13 01:09:47 PM PDT 24
Peak memory 198136 kb
Host smart-9a5c075c-9e24-4bbb-9731-a081d0c61ffd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=56388180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.56388180
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.2794816588
Short name T255
Test name
Test status
Simulation time 16594624 ps
CPU time 0.63 seconds
Started Jun 13 12:46:48 PM PDT 24
Finished Jun 13 12:46:49 PM PDT 24
Peak memory 194680 kb
Host smart-c486b8fe-46e8-48b2-8b92-2bc25ebd89f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794816588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.2794816588
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.2885393569
Short name T705
Test name
Test status
Simulation time 27242282 ps
CPU time 0.8 seconds
Started Jun 13 12:46:44 PM PDT 24
Finished Jun 13 12:46:46 PM PDT 24
Peak memory 195148 kb
Host smart-40e11e01-4071-40c9-bfed-7f8687fac2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885393569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.2885393569
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.2378537451
Short name T223
Test name
Test status
Simulation time 1856278257 ps
CPU time 26.18 seconds
Started Jun 13 12:46:44 PM PDT 24
Finished Jun 13 12:47:11 PM PDT 24
Peak memory 196668 kb
Host smart-926832e7-ab8a-453b-8eb5-0f1811b20b13
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378537451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.2378537451
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.1672481369
Short name T53
Test name
Test status
Simulation time 78125568 ps
CPU time 1.03 seconds
Started Jun 13 12:46:50 PM PDT 24
Finished Jun 13 12:46:52 PM PDT 24
Peak memory 196900 kb
Host smart-d9f043c1-c5b9-499f-bbc0-95fe6812af6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672481369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.1672481369
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.4006799744
Short name T428
Test name
Test status
Simulation time 688890232 ps
CPU time 1.42 seconds
Started Jun 13 12:46:45 PM PDT 24
Finished Jun 13 12:46:47 PM PDT 24
Peak memory 195704 kb
Host smart-2e33e249-63d9-4885-ae00-0de18c542250
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006799744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.4006799744
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.1592583573
Short name T27
Test name
Test status
Simulation time 28579864 ps
CPU time 1.41 seconds
Started Jun 13 12:46:46 PM PDT 24
Finished Jun 13 12:46:48 PM PDT 24
Peak memory 197980 kb
Host smart-f8876e79-97ef-431a-8801-9d8e7ba276d9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592583573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.1592583573
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.3027154534
Short name T442
Test name
Test status
Simulation time 175834736 ps
CPU time 2.29 seconds
Started Jun 13 12:46:43 PM PDT 24
Finished Jun 13 12:46:46 PM PDT 24
Peak memory 196508 kb
Host smart-7a8888ac-82dc-46ec-80a2-a28d74e11f5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027154534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.3027154534
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.489724290
Short name T654
Test name
Test status
Simulation time 87598447 ps
CPU time 1.21 seconds
Started Jun 13 12:46:46 PM PDT 24
Finished Jun 13 12:46:48 PM PDT 24
Peak memory 197036 kb
Host smart-e25c8c3d-5545-41b4-b035-19c67a6d45b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489724290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.489724290
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.3659208340
Short name T402
Test name
Test status
Simulation time 28331132 ps
CPU time 0.74 seconds
Started Jun 13 12:46:44 PM PDT 24
Finished Jun 13 12:46:45 PM PDT 24
Peak memory 194208 kb
Host smart-f5c4f2e8-8dd1-4d56-aff5-c787fbc03e58
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659208340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.3659208340
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.3432298580
Short name T463
Test name
Test status
Simulation time 401695687 ps
CPU time 3.45 seconds
Started Jun 13 12:46:46 PM PDT 24
Finished Jun 13 12:46:50 PM PDT 24
Peak memory 197888 kb
Host smart-dc5e4488-bf0d-4cba-8590-9a624b42789c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432298580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.3432298580
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.3368490956
Short name T430
Test name
Test status
Simulation time 186213956 ps
CPU time 1.52 seconds
Started Jun 13 12:46:41 PM PDT 24
Finished Jun 13 12:46:43 PM PDT 24
Peak memory 196696 kb
Host smart-71bb3199-6981-4e37-9dac-98b8a8984d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368490956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.3368490956
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.1155438797
Short name T665
Test name
Test status
Simulation time 164849146 ps
CPU time 1.14 seconds
Started Jun 13 12:46:35 PM PDT 24
Finished Jun 13 12:46:37 PM PDT 24
Peak memory 195452 kb
Host smart-ce5227d1-6000-48db-b954-9bee99368c75
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155438797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.1155438797
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.4099374013
Short name T474
Test name
Test status
Simulation time 4325188988 ps
CPU time 44.88 seconds
Started Jun 13 12:46:46 PM PDT 24
Finished Jun 13 12:47:31 PM PDT 24
Peak memory 198128 kb
Host smart-75ee47ee-49d8-4a1f-9baa-5af2e2ef15c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099374013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.4099374013
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.548880986
Short name T606
Test name
Test status
Simulation time 13868587 ps
CPU time 0.59 seconds
Started Jun 13 12:46:50 PM PDT 24
Finished Jun 13 12:46:51 PM PDT 24
Peak memory 194436 kb
Host smart-d1d6d0a6-efc0-451f-bcf7-abe11a1cb490
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548880986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.548880986
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.2576511752
Short name T568
Test name
Test status
Simulation time 153501849 ps
CPU time 0.87 seconds
Started Jun 13 12:46:49 PM PDT 24
Finished Jun 13 12:46:50 PM PDT 24
Peak memory 196256 kb
Host smart-5763d5b0-5895-4ea6-8f9a-de55a12058ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576511752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.2576511752
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.134049542
Short name T584
Test name
Test status
Simulation time 408596558 ps
CPU time 11.46 seconds
Started Jun 13 12:46:50 PM PDT 24
Finished Jun 13 12:47:02 PM PDT 24
Peak memory 196620 kb
Host smart-60b9af93-18e7-47e2-a58c-fe886b0705a8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134049542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stres
s.134049542
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.3226769898
Short name T681
Test name
Test status
Simulation time 311768670 ps
CPU time 1.05 seconds
Started Jun 13 12:46:48 PM PDT 24
Finished Jun 13 12:46:50 PM PDT 24
Peak memory 196288 kb
Host smart-0c1056a4-c61b-49e7-abfc-415d27546ab4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226769898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.3226769898
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.2276453588
Short name T394
Test name
Test status
Simulation time 23151452 ps
CPU time 0.74 seconds
Started Jun 13 12:46:51 PM PDT 24
Finished Jun 13 12:46:53 PM PDT 24
Peak memory 195368 kb
Host smart-25ad2f54-5269-44ce-b503-729eddc0953f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276453588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.2276453588
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.460160911
Short name T261
Test name
Test status
Simulation time 90502381 ps
CPU time 3.65 seconds
Started Jun 13 12:46:49 PM PDT 24
Finished Jun 13 12:46:54 PM PDT 24
Peak memory 197988 kb
Host smart-4d7755e0-2618-46b6-8fda-ecbc2049c65b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460160911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.gpio_intr_with_filter_rand_intr_event.460160911
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.43145296
Short name T174
Test name
Test status
Simulation time 403832444 ps
CPU time 2.1 seconds
Started Jun 13 12:46:53 PM PDT 24
Finished Jun 13 12:46:55 PM PDT 24
Peak memory 196224 kb
Host smart-c6d21d1f-b42a-4b76-8ce2-8d8367f72665
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43145296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger.43145296
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.2248275486
Short name T198
Test name
Test status
Simulation time 254047668 ps
CPU time 1.1 seconds
Started Jun 13 12:46:45 PM PDT 24
Finished Jun 13 12:46:47 PM PDT 24
Peak memory 195780 kb
Host smart-a77a4cb5-2418-4a68-bb1e-e251fb61d94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248275486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.2248275486
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3699763959
Short name T179
Test name
Test status
Simulation time 70290864 ps
CPU time 1.25 seconds
Started Jun 13 12:46:46 PM PDT 24
Finished Jun 13 12:46:49 PM PDT 24
Peak memory 196988 kb
Host smart-450d9d68-acb2-4adf-bbdd-7b7583ad5524
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699763959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3699763959
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.3971385742
Short name T330
Test name
Test status
Simulation time 160811931 ps
CPU time 2 seconds
Started Jun 13 12:46:49 PM PDT 24
Finished Jun 13 12:46:52 PM PDT 24
Peak memory 197900 kb
Host smart-586ecf56-ecd7-42d6-93b4-dba6822b6209
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971385742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.3971385742
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.4004464384
Short name T611
Test name
Test status
Simulation time 114165930 ps
CPU time 1.46 seconds
Started Jun 13 12:46:48 PM PDT 24
Finished Jun 13 12:46:50 PM PDT 24
Peak memory 198028 kb
Host smart-862c7da4-d9c8-49b1-9b25-e0966ea830b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004464384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.4004464384
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.1546114765
Short name T663
Test name
Test status
Simulation time 55395260 ps
CPU time 1.02 seconds
Started Jun 13 12:46:50 PM PDT 24
Finished Jun 13 12:46:52 PM PDT 24
Peak memory 196284 kb
Host smart-1f4dee81-ee63-43b9-8085-c87c99d1aa70
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546114765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.1546114765
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.1170784337
Short name T417
Test name
Test status
Simulation time 23042490480 ps
CPU time 128.15 seconds
Started Jun 13 12:46:51 PM PDT 24
Finished Jun 13 12:49:00 PM PDT 24
Peak memory 197976 kb
Host smart-c5e16fcd-aa2a-42bc-b6f3-21a721192fde
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170784337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.1170784337
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.3101924870
Short name T437
Test name
Test status
Simulation time 14655594 ps
CPU time 0.59 seconds
Started Jun 13 12:46:52 PM PDT 24
Finished Jun 13 12:46:53 PM PDT 24
Peak memory 194472 kb
Host smart-e80d502f-b1de-4d9b-9190-02dc6e15fedf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101924870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.3101924870
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.525660785
Short name T237
Test name
Test status
Simulation time 13467659 ps
CPU time 0.61 seconds
Started Jun 13 12:46:51 PM PDT 24
Finished Jun 13 12:46:53 PM PDT 24
Peak memory 193820 kb
Host smart-bdb805dd-f8d8-491f-b275-c57f29b5e711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525660785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.525660785
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.737673485
Short name T326
Test name
Test status
Simulation time 5565898717 ps
CPU time 22 seconds
Started Jun 13 12:46:51 PM PDT 24
Finished Jun 13 12:47:14 PM PDT 24
Peak memory 197992 kb
Host smart-eb9e8ad5-13d6-4715-b1a2-b72ff9b06c9f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737673485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stres
s.737673485
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.4061044517
Short name T704
Test name
Test status
Simulation time 41779702 ps
CPU time 0.84 seconds
Started Jun 13 12:46:51 PM PDT 24
Finished Jun 13 12:46:53 PM PDT 24
Peak memory 196460 kb
Host smart-35dd472e-7277-4992-99cd-6acf69c45e1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061044517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.4061044517
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.1676508749
Short name T529
Test name
Test status
Simulation time 29697100 ps
CPU time 0.79 seconds
Started Jun 13 12:46:50 PM PDT 24
Finished Jun 13 12:46:51 PM PDT 24
Peak memory 195284 kb
Host smart-a0c64a70-7eab-4a2e-af7e-f175305a9c7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676508749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.1676508749
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.2543894304
Short name T243
Test name
Test status
Simulation time 63509745 ps
CPU time 2.4 seconds
Started Jun 13 12:46:52 PM PDT 24
Finished Jun 13 12:46:55 PM PDT 24
Peak memory 197108 kb
Host smart-2a47d861-1d1a-47f1-b75c-003a1630aa19
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543894304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.2543894304
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.1223497217
Short name T594
Test name
Test status
Simulation time 120565341 ps
CPU time 2.67 seconds
Started Jun 13 12:46:51 PM PDT 24
Finished Jun 13 12:46:55 PM PDT 24
Peak memory 198036 kb
Host smart-f0a2c0a6-c00b-4996-81ca-510e42faa352
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223497217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.1223497217
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.1318809867
Short name T292
Test name
Test status
Simulation time 197107399 ps
CPU time 0.8 seconds
Started Jun 13 12:46:50 PM PDT 24
Finished Jun 13 12:46:52 PM PDT 24
Peak memory 195952 kb
Host smart-a30ce57f-9b99-45ba-9470-162e44eed602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318809867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.1318809867
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.1521716636
Short name T460
Test name
Test status
Simulation time 16662781 ps
CPU time 0.72 seconds
Started Jun 13 12:46:52 PM PDT 24
Finished Jun 13 12:46:54 PM PDT 24
Peak memory 196032 kb
Host smart-f3f91d5f-28ca-43ff-8a0f-d98cc6daf57d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521716636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.1521716636
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.930305560
Short name T637
Test name
Test status
Simulation time 318247546 ps
CPU time 4.09 seconds
Started Jun 13 12:46:51 PM PDT 24
Finished Jun 13 12:46:56 PM PDT 24
Peak memory 197852 kb
Host smart-b35b9006-6e65-49e8-9d55-f4cfffe4ae34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930305560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ran
dom_long_reg_writes_reg_reads.930305560
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.2069925828
Short name T347
Test name
Test status
Simulation time 686346303 ps
CPU time 1.17 seconds
Started Jun 13 12:46:49 PM PDT 24
Finished Jun 13 12:46:51 PM PDT 24
Peak memory 195696 kb
Host smart-69b27e43-ff10-48dc-bc1b-49f19741577e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069925828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.2069925828
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.815646947
Short name T153
Test name
Test status
Simulation time 205771007 ps
CPU time 0.87 seconds
Started Jun 13 12:46:54 PM PDT 24
Finished Jun 13 12:46:56 PM PDT 24
Peak memory 195104 kb
Host smart-4fe9c3fa-65dd-4aeb-a570-b9ecb6a029f4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815646947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.815646947
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.722881801
Short name T682
Test name
Test status
Simulation time 128067121972 ps
CPU time 165.07 seconds
Started Jun 13 12:46:57 PM PDT 24
Finished Jun 13 12:49:43 PM PDT 24
Peak memory 198072 kb
Host smart-317182e4-b9b2-4add-ab8a-cb1c7a8adebd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722881801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.g
pio_stress_all.722881801
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.1639960569
Short name T589
Test name
Test status
Simulation time 234574070379 ps
CPU time 631.47 seconds
Started Jun 13 12:46:55 PM PDT 24
Finished Jun 13 12:57:27 PM PDT 24
Peak memory 206372 kb
Host smart-8eedc024-3b31-4320-a4a5-d983a351ddd9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1639960569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.1639960569
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.832657353
Short name T458
Test name
Test status
Simulation time 16507703 ps
CPU time 0.6 seconds
Started Jun 13 12:46:57 PM PDT 24
Finished Jun 13 12:46:58 PM PDT 24
Peak memory 193960 kb
Host smart-af3f46d5-5fa6-44bc-b7c9-fac56703db46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832657353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.832657353
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.2365093029
Short name T407
Test name
Test status
Simulation time 50474764 ps
CPU time 0.97 seconds
Started Jun 13 12:46:57 PM PDT 24
Finished Jun 13 12:46:58 PM PDT 24
Peak memory 195652 kb
Host smart-d259e02d-2f6e-4d1b-a989-b8071a56841e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365093029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.2365093029
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.1868254762
Short name T673
Test name
Test status
Simulation time 1517955641 ps
CPU time 15.51 seconds
Started Jun 13 12:46:57 PM PDT 24
Finished Jun 13 12:47:13 PM PDT 24
Peak memory 195464 kb
Host smart-6264b525-a618-456d-888b-0048f6efb4f3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868254762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.1868254762
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.798566918
Short name T540
Test name
Test status
Simulation time 210836585 ps
CPU time 0.9 seconds
Started Jun 13 12:46:57 PM PDT 24
Finished Jun 13 12:46:59 PM PDT 24
Peak memory 195800 kb
Host smart-56bd9ffd-3022-485b-a862-d89836011fea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798566918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.798566918
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.2780258841
Short name T275
Test name
Test status
Simulation time 78477155 ps
CPU time 1.11 seconds
Started Jun 13 12:46:59 PM PDT 24
Finished Jun 13 12:47:00 PM PDT 24
Peak memory 195768 kb
Host smart-e663b2a5-268c-49fd-a1d8-5d347121a701
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780258841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.2780258841
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.1387019953
Short name T367
Test name
Test status
Simulation time 250730517 ps
CPU time 2.19 seconds
Started Jun 13 12:46:58 PM PDT 24
Finished Jun 13 12:47:00 PM PDT 24
Peak memory 198080 kb
Host smart-47677f5f-76a6-48bd-b003-d2efa691245e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387019953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.1387019953
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.923656037
Short name T317
Test name
Test status
Simulation time 576974843 ps
CPU time 3.61 seconds
Started Jun 13 12:46:59 PM PDT 24
Finished Jun 13 12:47:03 PM PDT 24
Peak memory 198004 kb
Host smart-78c2adf1-3ab9-447b-b682-02f03706baa7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923656037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.
923656037
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.2679061961
Short name T15
Test name
Test status
Simulation time 154095910 ps
CPU time 0.85 seconds
Started Jun 13 12:46:58 PM PDT 24
Finished Jun 13 12:46:59 PM PDT 24
Peak memory 197076 kb
Host smart-7fc7e797-098f-4775-b055-7e7d2a646f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679061961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.2679061961
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.2712536961
Short name T195
Test name
Test status
Simulation time 116345693 ps
CPU time 1.12 seconds
Started Jun 13 12:46:56 PM PDT 24
Finished Jun 13 12:46:57 PM PDT 24
Peak memory 196760 kb
Host smart-00c03885-05f1-46b8-9f7a-2c20bee39ccf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712536961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.2712536961
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.2303470221
Short name T668
Test name
Test status
Simulation time 207060100 ps
CPU time 3.34 seconds
Started Jun 13 12:46:58 PM PDT 24
Finished Jun 13 12:47:02 PM PDT 24
Peak memory 197888 kb
Host smart-7d7d2f5e-393f-42c4-b2fa-b80b2d6f7cac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303470221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.2303470221
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.258304002
Short name T381
Test name
Test status
Simulation time 268576302 ps
CPU time 1.32 seconds
Started Jun 13 12:46:50 PM PDT 24
Finished Jun 13 12:46:52 PM PDT 24
Peak memory 196416 kb
Host smart-b6d49278-2544-4caf-850d-7b66a98d8425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258304002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.258304002
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.2825204521
Short name T111
Test name
Test status
Simulation time 353555613 ps
CPU time 1.53 seconds
Started Jun 13 12:47:00 PM PDT 24
Finished Jun 13 12:47:02 PM PDT 24
Peak memory 196716 kb
Host smart-77adac65-b38a-4ea5-84aa-d04d3ede59d6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825204521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.2825204521
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.2469263095
Short name T500
Test name
Test status
Simulation time 17648209953 ps
CPU time 239.74 seconds
Started Jun 13 12:46:59 PM PDT 24
Finished Jun 13 12:51:00 PM PDT 24
Peak memory 198044 kb
Host smart-3f9a56e4-e057-4aa8-b02d-28e679a932b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469263095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.2469263095
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.1376255164
Short name T472
Test name
Test status
Simulation time 77690960497 ps
CPU time 262.87 seconds
Started Jun 13 12:46:58 PM PDT 24
Finished Jun 13 12:51:22 PM PDT 24
Peak memory 198040 kb
Host smart-50298d96-8fc4-4171-8817-b9b8fe7b24f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1376255164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.1376255164
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.3901249986
Short name T334
Test name
Test status
Simulation time 12124289 ps
CPU time 0.58 seconds
Started Jun 13 12:47:09 PM PDT 24
Finished Jun 13 12:47:10 PM PDT 24
Peak memory 194320 kb
Host smart-32f81ef4-8894-4189-a53a-3409a4f6345d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901249986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.3901249986
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.1024055585
Short name T192
Test name
Test status
Simulation time 145552631 ps
CPU time 0.95 seconds
Started Jun 13 12:47:04 PM PDT 24
Finished Jun 13 12:47:05 PM PDT 24
Peak memory 197064 kb
Host smart-5b8b924b-4db8-4ac5-aea1-adfbb49bdc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024055585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.1024055585
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.4135029111
Short name T172
Test name
Test status
Simulation time 259459008 ps
CPU time 7.76 seconds
Started Jun 13 12:47:03 PM PDT 24
Finished Jun 13 12:47:12 PM PDT 24
Peak memory 198180 kb
Host smart-7143685b-10bf-4c22-85f7-c6a351a7a2a9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135029111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.4135029111
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.405407901
Short name T659
Test name
Test status
Simulation time 215105922 ps
CPU time 0.88 seconds
Started Jun 13 12:47:01 PM PDT 24
Finished Jun 13 12:47:03 PM PDT 24
Peak memory 196620 kb
Host smart-925c26ad-7a28-4d2b-a770-2e3a40f2f3c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405407901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.405407901
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.1678439644
Short name T173
Test name
Test status
Simulation time 74723025 ps
CPU time 1.14 seconds
Started Jun 13 12:47:03 PM PDT 24
Finished Jun 13 12:47:05 PM PDT 24
Peak memory 195904 kb
Host smart-425b8ea2-30ed-45b2-b9d4-8f756d793529
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678439644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.1678439644
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.3586100631
Short name T447
Test name
Test status
Simulation time 350491899 ps
CPU time 3.77 seconds
Started Jun 13 12:47:04 PM PDT 24
Finished Jun 13 12:47:08 PM PDT 24
Peak memory 198108 kb
Host smart-0105c77e-fff7-47b5-832a-a3e44143c242
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586100631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.3586100631
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3163095710
Short name T711
Test name
Test status
Simulation time 136634729 ps
CPU time 2.97 seconds
Started Jun 13 12:47:07 PM PDT 24
Finished Jun 13 12:47:10 PM PDT 24
Peak memory 198008 kb
Host smart-cb2f7a6f-04c6-4ff7-9bb1-8809f02eddc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163095710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3163095710
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.2935908485
Short name T311
Test name
Test status
Simulation time 353962772 ps
CPU time 1.19 seconds
Started Jun 13 12:47:03 PM PDT 24
Finished Jun 13 12:47:04 PM PDT 24
Peak memory 196028 kb
Host smart-7c6d3c9f-ac8f-4d72-bead-0d37bc6f5062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935908485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.2935908485
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.1483751463
Short name T640
Test name
Test status
Simulation time 138442308 ps
CPU time 1.4 seconds
Started Jun 13 12:47:01 PM PDT 24
Finished Jun 13 12:47:03 PM PDT 24
Peak memory 196856 kb
Host smart-31abdbe1-9002-4ec1-a41b-96502ebbd9f5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483751463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.1483751463
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1775860784
Short name T439
Test name
Test status
Simulation time 87110330 ps
CPU time 3.73 seconds
Started Jun 13 12:47:08 PM PDT 24
Finished Jun 13 12:47:12 PM PDT 24
Peak memory 197924 kb
Host smart-a6149674-8586-45b1-b475-f795bedf9970
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775860784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1775860784
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.379439054
Short name T171
Test name
Test status
Simulation time 165894107 ps
CPU time 1 seconds
Started Jun 13 12:46:58 PM PDT 24
Finished Jun 13 12:46:59 PM PDT 24
Peak memory 196384 kb
Host smart-0af1a6f5-ccfc-49a6-aab3-2d587b5df0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379439054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.379439054
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.801905687
Short name T345
Test name
Test status
Simulation time 235849751 ps
CPU time 1.22 seconds
Started Jun 13 12:46:58 PM PDT 24
Finished Jun 13 12:47:00 PM PDT 24
Peak memory 196536 kb
Host smart-3cf2484e-b72b-482b-b2c9-40e944d5556a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801905687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.801905687
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.2112604269
Short name T337
Test name
Test status
Simulation time 8788927261 ps
CPU time 234.28 seconds
Started Jun 13 12:47:03 PM PDT 24
Finished Jun 13 12:50:58 PM PDT 24
Peak memory 198048 kb
Host smart-cfaebdb2-209e-45f4-bc6e-7b8e6d7bdc11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112604269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.2112604269
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.296685823
Short name T304
Test name
Test status
Simulation time 75568884 ps
CPU time 0.84 seconds
Started Jun 13 12:47:03 PM PDT 24
Finished Jun 13 12:47:04 PM PDT 24
Peak memory 195144 kb
Host smart-b46c996c-e586-4696-aa5e-9ced3dca8308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296685823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.296685823
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.1223763930
Short name T573
Test name
Test status
Simulation time 3724403810 ps
CPU time 26.51 seconds
Started Jun 13 12:47:06 PM PDT 24
Finished Jun 13 12:47:33 PM PDT 24
Peak memory 197008 kb
Host smart-3baf4bb6-d1b9-482a-8b0c-0f8ef499cfac
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223763930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.1223763930
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.3146885012
Short name T169
Test name
Test status
Simulation time 307255273 ps
CPU time 0.89 seconds
Started Jun 13 12:47:03 PM PDT 24
Finished Jun 13 12:47:05 PM PDT 24
Peak memory 196792 kb
Host smart-14bc93c8-36b3-4a56-8aa2-7d582b5c49df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146885012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.3146885012
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.1392152475
Short name T392
Test name
Test status
Simulation time 296193236 ps
CPU time 1.33 seconds
Started Jun 13 12:47:03 PM PDT 24
Finished Jun 13 12:47:05 PM PDT 24
Peak memory 195776 kb
Host smart-701db3a5-bc9f-4efb-9ecb-1f7d9f9de2a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392152475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.1392152475
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.3944600932
Short name T225
Test name
Test status
Simulation time 51881765 ps
CPU time 2.2 seconds
Started Jun 13 12:47:03 PM PDT 24
Finished Jun 13 12:47:05 PM PDT 24
Peak memory 198004 kb
Host smart-b5d4c4b6-ee2e-4900-b3ce-963b2bda3918
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944600932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.3944600932
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.3202286249
Short name T440
Test name
Test status
Simulation time 100824125 ps
CPU time 2.89 seconds
Started Jun 13 12:47:06 PM PDT 24
Finished Jun 13 12:47:09 PM PDT 24
Peak memory 195780 kb
Host smart-08e8d1c8-e166-49ba-937c-7c6c2d338434
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202286249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.3202286249
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.1355808155
Short name T48
Test name
Test status
Simulation time 308392599 ps
CPU time 1.22 seconds
Started Jun 13 12:47:09 PM PDT 24
Finished Jun 13 12:47:11 PM PDT 24
Peak memory 195796 kb
Host smart-c2e41196-9619-4a19-8b19-24828f61052d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355808155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.1355808155
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.3024090791
Short name T154
Test name
Test status
Simulation time 35053930 ps
CPU time 1.19 seconds
Started Jun 13 12:47:03 PM PDT 24
Finished Jun 13 12:47:05 PM PDT 24
Peak memory 196876 kb
Host smart-87b1e275-164a-4201-bfc1-94fc0e3016e6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024090791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.3024090791
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.3462210944
Short name T677
Test name
Test status
Simulation time 67430640 ps
CPU time 2.74 seconds
Started Jun 13 12:47:07 PM PDT 24
Finished Jun 13 12:47:10 PM PDT 24
Peak memory 197916 kb
Host smart-ce9e04de-7879-40ce-b975-9d09dba3963e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462210944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.3462210944
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.31785992
Short name T183
Test name
Test status
Simulation time 358537640 ps
CPU time 1.44 seconds
Started Jun 13 12:47:06 PM PDT 24
Finished Jun 13 12:47:08 PM PDT 24
Peak memory 196916 kb
Host smart-11d6cdab-a874-47bb-829a-cf1653758504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31785992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.31785992
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.3254338959
Short name T248
Test name
Test status
Simulation time 192545670 ps
CPU time 0.88 seconds
Started Jun 13 12:47:06 PM PDT 24
Finished Jun 13 12:47:07 PM PDT 24
Peak memory 196364 kb
Host smart-7cc0844a-7ead-469f-9024-53d4710108c2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254338959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.3254338959
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.1370567451
Short name T214
Test name
Test status
Simulation time 3641940842 ps
CPU time 25.77 seconds
Started Jun 13 12:47:06 PM PDT 24
Finished Jun 13 12:47:32 PM PDT 24
Peak memory 198080 kb
Host smart-2f137cc6-2883-409c-a81a-7397329809a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370567451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.1370567451
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.1080181637
Short name T357
Test name
Test status
Simulation time 14659261 ps
CPU time 0.56 seconds
Started Jun 13 12:45:48 PM PDT 24
Finished Jun 13 12:45:49 PM PDT 24
Peak memory 193724 kb
Host smart-245bd855-21a3-41b1-95d0-428e964c6a1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080181637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.1080181637
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.1714426862
Short name T358
Test name
Test status
Simulation time 121331724 ps
CPU time 0.8 seconds
Started Jun 13 12:45:42 PM PDT 24
Finished Jun 13 12:45:44 PM PDT 24
Peak memory 195820 kb
Host smart-f49e7273-43be-4fcd-9d28-d56707c510d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714426862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.1714426862
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.1808569058
Short name T444
Test name
Test status
Simulation time 1277011187 ps
CPU time 9.72 seconds
Started Jun 13 12:45:46 PM PDT 24
Finished Jun 13 12:45:56 PM PDT 24
Peak memory 196228 kb
Host smart-ace90867-497e-432d-a7b6-b4e5498ea4c6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808569058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.1808569058
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.1758302779
Short name T107
Test name
Test status
Simulation time 196994973 ps
CPU time 0.75 seconds
Started Jun 13 12:45:50 PM PDT 24
Finished Jun 13 12:45:51 PM PDT 24
Peak memory 195736 kb
Host smart-30d54ce2-ec6b-4355-bdf0-867cf0432102
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758302779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.1758302779
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.475897415
Short name T661
Test name
Test status
Simulation time 42297736 ps
CPU time 1.05 seconds
Started Jun 13 12:45:39 PM PDT 24
Finished Jun 13 12:45:40 PM PDT 24
Peak memory 195988 kb
Host smart-1cb9e5b0-b08b-4404-a82a-900b623d4d01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475897415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.475897415
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.3942535686
Short name T254
Test name
Test status
Simulation time 71384885 ps
CPU time 2.81 seconds
Started Jun 13 12:45:40 PM PDT 24
Finished Jun 13 12:45:43 PM PDT 24
Peak memory 197968 kb
Host smart-fddac139-1f2a-4fd1-986d-fb80dae0d27c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942535686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.3942535686
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.3834558700
Short name T300
Test name
Test status
Simulation time 81821456 ps
CPU time 2.47 seconds
Started Jun 13 12:45:42 PM PDT 24
Finished Jun 13 12:45:45 PM PDT 24
Peak memory 195692 kb
Host smart-2024c1e2-f5d7-4f55-9706-4c841602f2ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834558700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
3834558700
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.2615808311
Short name T299
Test name
Test status
Simulation time 291069725 ps
CPU time 0.94 seconds
Started Jun 13 12:45:48 PM PDT 24
Finished Jun 13 12:45:49 PM PDT 24
Peak memory 195836 kb
Host smart-88e2af16-4356-4362-bdf0-4a003120a5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615808311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.2615808311
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.184590279
Short name T448
Test name
Test status
Simulation time 59091110 ps
CPU time 1.36 seconds
Started Jun 13 12:45:40 PM PDT 24
Finished Jun 13 12:45:42 PM PDT 24
Peak memory 197256 kb
Host smart-233f9bf7-0797-4932-8cb1-59d546bada7e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184590279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup_
pulldown.184590279
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.3989553733
Short name T574
Test name
Test status
Simulation time 1297935673 ps
CPU time 5.54 seconds
Started Jun 13 12:45:49 PM PDT 24
Finished Jun 13 12:45:55 PM PDT 24
Peak memory 197932 kb
Host smart-f022a2aa-6afd-4a78-b9a4-28281575df7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989553733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.3989553733
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.2422815950
Short name T36
Test name
Test status
Simulation time 366991891 ps
CPU time 0.93 seconds
Started Jun 13 12:45:53 PM PDT 24
Finished Jun 13 12:45:54 PM PDT 24
Peak memory 214740 kb
Host smart-bc16b994-e414-4e9b-b73e-ac952356e738
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422815950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.2422815950
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.3391514436
Short name T204
Test name
Test status
Simulation time 113618834 ps
CPU time 1.35 seconds
Started Jun 13 12:45:46 PM PDT 24
Finished Jun 13 12:45:48 PM PDT 24
Peak memory 196724 kb
Host smart-6a6e3e9a-9ab3-4d2b-a18e-263e666ebf11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391514436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.3391514436
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.407907263
Short name T150
Test name
Test status
Simulation time 65424613 ps
CPU time 1.27 seconds
Started Jun 13 12:45:40 PM PDT 24
Finished Jun 13 12:45:43 PM PDT 24
Peak memory 195676 kb
Host smart-a79a83cd-1a91-4906-9514-0e1230b681cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407907263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.407907263
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.1585567348
Short name T152
Test name
Test status
Simulation time 9785426491 ps
CPU time 184.73 seconds
Started Jun 13 12:45:48 PM PDT 24
Finished Jun 13 12:48:53 PM PDT 24
Peak memory 197992 kb
Host smart-45700ac6-bc1a-4806-b3ba-de07e7e681ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585567348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.1585567348
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.1917335397
Short name T369
Test name
Test status
Simulation time 13806434 ps
CPU time 0.58 seconds
Started Jun 13 12:47:12 PM PDT 24
Finished Jun 13 12:47:13 PM PDT 24
Peak memory 193744 kb
Host smart-78011ac9-87f3-49d0-bf97-adcfbb12ab76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917335397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.1917335397
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.1706152907
Short name T211
Test name
Test status
Simulation time 116787166 ps
CPU time 0.64 seconds
Started Jun 13 12:47:03 PM PDT 24
Finished Jun 13 12:47:05 PM PDT 24
Peak memory 193892 kb
Host smart-2267b45f-0c08-4455-9e9f-cbecb3329aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706152907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.1706152907
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.2358841219
Short name T175
Test name
Test status
Simulation time 831932971 ps
CPU time 5.91 seconds
Started Jun 13 12:47:11 PM PDT 24
Finished Jun 13 12:47:17 PM PDT 24
Peak memory 196760 kb
Host smart-227bfd89-f0cb-4b4d-a870-5fba379106a1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358841219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.2358841219
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.2937001016
Short name T131
Test name
Test status
Simulation time 26658305 ps
CPU time 0.7 seconds
Started Jun 13 12:47:13 PM PDT 24
Finished Jun 13 12:47:14 PM PDT 24
Peak memory 194532 kb
Host smart-8984a3ce-ba4f-4f86-a9a3-d2e3cc3bd663
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937001016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.2937001016
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.3885187955
Short name T14
Test name
Test status
Simulation time 151527348 ps
CPU time 1.07 seconds
Started Jun 13 12:47:09 PM PDT 24
Finished Jun 13 12:47:10 PM PDT 24
Peak memory 195540 kb
Host smart-68dc9264-c7f6-4d6e-94d1-4c0d33737d60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885187955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.3885187955
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.3679550565
Short name T136
Test name
Test status
Simulation time 69655953 ps
CPU time 3.18 seconds
Started Jun 13 12:47:11 PM PDT 24
Finished Jun 13 12:47:15 PM PDT 24
Peak memory 198028 kb
Host smart-2c80ea7e-ed35-4781-9bbd-d8031702fd60
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679550565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.3679550565
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.304653580
Short name T343
Test name
Test status
Simulation time 2649088863 ps
CPU time 2.65 seconds
Started Jun 13 12:47:13 PM PDT 24
Finished Jun 13 12:47:16 PM PDT 24
Peak memory 197436 kb
Host smart-d2801247-c690-4d57-9de5-1c9d7b56e60a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304653580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger.
304653580
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.100546584
Short name T278
Test name
Test status
Simulation time 46658916 ps
CPU time 1.13 seconds
Started Jun 13 12:47:09 PM PDT 24
Finished Jun 13 12:47:10 PM PDT 24
Peak memory 195936 kb
Host smart-391f709f-ea91-4f1d-a4d8-0a57a553fd23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100546584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.100546584
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.3941508404
Short name T554
Test name
Test status
Simulation time 115034476 ps
CPU time 1.22 seconds
Started Jun 13 12:47:01 PM PDT 24
Finished Jun 13 12:47:03 PM PDT 24
Peak memory 195980 kb
Host smart-44941c06-8628-48b8-b3a3-098cf8e5d295
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941508404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.3941508404
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.3684849299
Short name T410
Test name
Test status
Simulation time 98318921 ps
CPU time 4.48 seconds
Started Jun 13 12:47:14 PM PDT 24
Finished Jun 13 12:47:18 PM PDT 24
Peak memory 197932 kb
Host smart-fad48091-69eb-49e6-9738-2d0227fbf8dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684849299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.3684849299
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.2955796087
Short name T385
Test name
Test status
Simulation time 69005710 ps
CPU time 1.01 seconds
Started Jun 13 12:47:04 PM PDT 24
Finished Jun 13 12:47:05 PM PDT 24
Peak memory 195740 kb
Host smart-dd943c96-d968-457b-88b5-a3aab7a07bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955796087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.2955796087
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.3057801100
Short name T551
Test name
Test status
Simulation time 91539704 ps
CPU time 1.01 seconds
Started Jun 13 12:47:03 PM PDT 24
Finished Jun 13 12:47:05 PM PDT 24
Peak memory 196396 kb
Host smart-6921b765-76d0-45b1-a13d-6d837a5bbfa7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057801100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.3057801100
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.2828086653
Short name T413
Test name
Test status
Simulation time 11898385588 ps
CPU time 167.28 seconds
Started Jun 13 12:47:10 PM PDT 24
Finished Jun 13 12:49:58 PM PDT 24
Peak memory 198076 kb
Host smart-309ffc60-18af-4372-b109-4f0cd64d97e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828086653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.2828086653
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.2846866
Short name T521
Test name
Test status
Simulation time 20966677 ps
CPU time 0.55 seconds
Started Jun 13 12:47:19 PM PDT 24
Finished Jun 13 12:47:20 PM PDT 24
Peak memory 194456 kb
Host smart-029c7705-2e6f-4226-9506-89b0422b381e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.2846866
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.1323367009
Short name T340
Test name
Test status
Simulation time 88518100 ps
CPU time 0.71 seconds
Started Jun 13 12:47:12 PM PDT 24
Finished Jun 13 12:47:13 PM PDT 24
Peak memory 194088 kb
Host smart-8e5922da-1e2f-4ebc-a740-d3b3d65d1817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323367009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.1323367009
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.3185513322
Short name T572
Test name
Test status
Simulation time 1097873201 ps
CPU time 17.72 seconds
Started Jun 13 12:47:21 PM PDT 24
Finished Jun 13 12:47:39 PM PDT 24
Peak memory 197968 kb
Host smart-56646d7e-cd30-402b-894e-aeda68d9f9cb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185513322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.3185513322
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.4060296506
Short name T273
Test name
Test status
Simulation time 129412542 ps
CPU time 0.96 seconds
Started Jun 13 12:47:17 PM PDT 24
Finished Jun 13 12:47:19 PM PDT 24
Peak memory 197568 kb
Host smart-39feb663-2f10-4280-9d88-9a9f85d5e461
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060296506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.4060296506
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.3982608447
Short name T403
Test name
Test status
Simulation time 40460862 ps
CPU time 1.16 seconds
Started Jun 13 12:47:14 PM PDT 24
Finished Jun 13 12:47:15 PM PDT 24
Peak memory 196436 kb
Host smart-77d6882b-ec0d-4937-b6f0-791dfd9a0762
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982608447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.3982608447
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.455547105
Short name T672
Test name
Test status
Simulation time 87364597 ps
CPU time 3.42 seconds
Started Jun 13 12:47:21 PM PDT 24
Finished Jun 13 12:47:25 PM PDT 24
Peak memory 198000 kb
Host smart-d877d7fc-f206-436a-b3f2-924c355259d4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455547105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.gpio_intr_with_filter_rand_intr_event.455547105
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.4139726321
Short name T282
Test name
Test status
Simulation time 52846058 ps
CPU time 1.26 seconds
Started Jun 13 12:47:13 PM PDT 24
Finished Jun 13 12:47:14 PM PDT 24
Peak memory 196264 kb
Host smart-3f01321f-e53c-4de5-854f-db1d0bc63172
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139726321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.4139726321
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.234767151
Short name T363
Test name
Test status
Simulation time 148657310 ps
CPU time 1.37 seconds
Started Jun 13 12:47:14 PM PDT 24
Finished Jun 13 12:47:16 PM PDT 24
Peak memory 197008 kb
Host smart-0d47a40c-2cfa-4a02-b4fd-80d7af97831e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234767151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.234767151
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.1241277689
Short name T505
Test name
Test status
Simulation time 71725867 ps
CPU time 0.8 seconds
Started Jun 13 12:47:17 PM PDT 24
Finished Jun 13 12:47:18 PM PDT 24
Peak memory 195184 kb
Host smart-7facab0d-3e72-4a77-a7bb-bafb85b0b200
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241277689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.1241277689
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.1846065971
Short name T141
Test name
Test status
Simulation time 287095285 ps
CPU time 3.79 seconds
Started Jun 13 12:47:19 PM PDT 24
Finished Jun 13 12:47:23 PM PDT 24
Peak memory 197780 kb
Host smart-75db079c-c059-41c1-a2e8-d065c4981631
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846065971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.1846065971
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.376636258
Short name T390
Test name
Test status
Simulation time 32669556 ps
CPU time 0.83 seconds
Started Jun 13 12:47:11 PM PDT 24
Finished Jun 13 12:47:12 PM PDT 24
Peak memory 195068 kb
Host smart-83a500cc-2995-44d0-814f-9ddfb07231f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376636258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.376636258
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.1901539853
Short name T366
Test name
Test status
Simulation time 286174283 ps
CPU time 1.53 seconds
Started Jun 13 12:47:13 PM PDT 24
Finished Jun 13 12:47:14 PM PDT 24
Peak memory 198052 kb
Host smart-4a8a4125-b784-47e6-920d-304e65d18c80
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901539853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.1901539853
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.2977566297
Short name T116
Test name
Test status
Simulation time 2711160028 ps
CPU time 73.73 seconds
Started Jun 13 12:47:18 PM PDT 24
Finished Jun 13 12:48:32 PM PDT 24
Peak memory 198016 kb
Host smart-f375f765-4887-4d15-b757-68ef8f8c7570
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977566297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.2977566297
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.4255493598
Short name T62
Test name
Test status
Simulation time 685310007135 ps
CPU time 1128.43 seconds
Started Jun 13 12:47:20 PM PDT 24
Finished Jun 13 01:06:09 PM PDT 24
Peak memory 198164 kb
Host smart-db7a2825-ae8f-4751-b916-3955d20e92d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4255493598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.4255493598
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.2408163518
Short name T436
Test name
Test status
Simulation time 11728841 ps
CPU time 0.6 seconds
Started Jun 13 12:47:19 PM PDT 24
Finished Jun 13 12:47:20 PM PDT 24
Peak memory 193712 kb
Host smart-d8d74e11-3ed7-4247-8c76-769476f0f3df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408163518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.2408163518
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.827847912
Short name T139
Test name
Test status
Simulation time 43757570 ps
CPU time 0.85 seconds
Started Jun 13 12:47:19 PM PDT 24
Finished Jun 13 12:47:21 PM PDT 24
Peak memory 195144 kb
Host smart-0973e098-ae16-4a1a-a5de-b2e534dfcca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827847912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.827847912
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.2283800380
Short name T660
Test name
Test status
Simulation time 455105999 ps
CPU time 18.61 seconds
Started Jun 13 12:47:18 PM PDT 24
Finished Jun 13 12:47:37 PM PDT 24
Peak memory 195412 kb
Host smart-5a6bd453-e7b3-4962-96de-932aa42237fa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283800380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.2283800380
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.3046772886
Short name T22
Test name
Test status
Simulation time 65537886 ps
CPU time 0.92 seconds
Started Jun 13 12:47:18 PM PDT 24
Finished Jun 13 12:47:19 PM PDT 24
Peak memory 195940 kb
Host smart-3e2bcdd1-bbbb-4035-b4d9-d79736557697
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046772886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.3046772886
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.3608685704
Short name T149
Test name
Test status
Simulation time 180316752 ps
CPU time 1.42 seconds
Started Jun 13 12:47:18 PM PDT 24
Finished Jun 13 12:47:20 PM PDT 24
Peak memory 196964 kb
Host smart-3bb9c1da-16b8-4027-b7a1-bbeddc998654
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608685704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.3608685704
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.1850456327
Short name T266
Test name
Test status
Simulation time 329329407 ps
CPU time 3.07 seconds
Started Jun 13 12:47:18 PM PDT 24
Finished Jun 13 12:47:22 PM PDT 24
Peak memory 198004 kb
Host smart-af7e8cb1-a501-4906-b621-d9c4fd1c82fd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850456327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.1850456327
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.3793879296
Short name T553
Test name
Test status
Simulation time 1360719839 ps
CPU time 2.06 seconds
Started Jun 13 12:47:19 PM PDT 24
Finished Jun 13 12:47:22 PM PDT 24
Peak memory 196908 kb
Host smart-07144442-cc43-43ff-a51f-2d4872325574
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793879296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.3793879296
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.3274554349
Short name T412
Test name
Test status
Simulation time 97747530 ps
CPU time 1.28 seconds
Started Jun 13 12:47:20 PM PDT 24
Finished Jun 13 12:47:22 PM PDT 24
Peak memory 195764 kb
Host smart-679b4258-a79f-4eea-8a64-8fc7d4aff9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274554349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.3274554349
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.368682330
Short name T356
Test name
Test status
Simulation time 152870621 ps
CPU time 1.05 seconds
Started Jun 13 12:47:17 PM PDT 24
Finished Jun 13 12:47:18 PM PDT 24
Peak memory 195780 kb
Host smart-6f854b4a-4846-4db2-9ae0-6f8b576ff88c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368682330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullup
_pulldown.368682330
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.2155791199
Short name T468
Test name
Test status
Simulation time 229046077 ps
CPU time 2.96 seconds
Started Jun 13 12:47:21 PM PDT 24
Finished Jun 13 12:47:24 PM PDT 24
Peak memory 197908 kb
Host smart-10cd6c77-c8a7-4ff1-a44e-17d19b36f6a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155791199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.2155791199
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.2117994860
Short name T414
Test name
Test status
Simulation time 176880876 ps
CPU time 1.3 seconds
Started Jun 13 12:47:18 PM PDT 24
Finished Jun 13 12:47:20 PM PDT 24
Peak memory 196668 kb
Host smart-67dc180d-5799-4a52-9f1a-dd2ec6e49b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117994860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.2117994860
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.1442564423
Short name T415
Test name
Test status
Simulation time 128692098 ps
CPU time 1.03 seconds
Started Jun 13 12:47:18 PM PDT 24
Finished Jun 13 12:47:20 PM PDT 24
Peak memory 195780 kb
Host smart-4e759002-53c0-45ff-8053-b7496d3e73d3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442564423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.1442564423
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.3478679307
Short name T534
Test name
Test status
Simulation time 10262677486 ps
CPU time 111.47 seconds
Started Jun 13 12:47:17 PM PDT 24
Finished Jun 13 12:49:09 PM PDT 24
Peak memory 197960 kb
Host smart-cf236d78-133b-42cb-a301-402858396046
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478679307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.3478679307
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.455306462
Short name T528
Test name
Test status
Simulation time 46272015 ps
CPU time 0.62 seconds
Started Jun 13 12:47:24 PM PDT 24
Finished Jun 13 12:47:25 PM PDT 24
Peak memory 193696 kb
Host smart-4b6990db-4a90-480e-8374-38f9ed1c1687
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455306462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.455306462
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.2182780766
Short name T147
Test name
Test status
Simulation time 47522739 ps
CPU time 0.67 seconds
Started Jun 13 12:47:21 PM PDT 24
Finished Jun 13 12:47:22 PM PDT 24
Peak memory 194724 kb
Host smart-242e06b5-e4a8-42ad-89d5-52f1ae2d7c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182780766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.2182780766
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.2513004712
Short name T443
Test name
Test status
Simulation time 1227673411 ps
CPU time 15.9 seconds
Started Jun 13 12:47:25 PM PDT 24
Finished Jun 13 12:47:41 PM PDT 24
Peak memory 196688 kb
Host smart-c662995d-cf47-4d6c-b9cc-8e9ba5cee6b7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513004712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.2513004712
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.131450248
Short name T459
Test name
Test status
Simulation time 128423526 ps
CPU time 0.78 seconds
Started Jun 13 12:47:24 PM PDT 24
Finished Jun 13 12:47:25 PM PDT 24
Peak memory 196528 kb
Host smart-5ea0c017-a752-4e03-845f-0bfe4d610102
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131450248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.131450248
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.2549091414
Short name T622
Test name
Test status
Simulation time 77545481 ps
CPU time 1.27 seconds
Started Jun 13 12:47:24 PM PDT 24
Finished Jun 13 12:47:25 PM PDT 24
Peak memory 197004 kb
Host smart-9022bae7-2918-4a51-bed6-83654d761895
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549091414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.2549091414
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.2241054687
Short name T518
Test name
Test status
Simulation time 79355211 ps
CPU time 3.42 seconds
Started Jun 13 12:47:25 PM PDT 24
Finished Jun 13 12:47:29 PM PDT 24
Peak memory 198000 kb
Host smart-2fe00619-11e3-4477-8087-c74d57050358
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241054687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.2241054687
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.152434153
Short name T125
Test name
Test status
Simulation time 138774817 ps
CPU time 2.45 seconds
Started Jun 13 12:47:26 PM PDT 24
Finished Jun 13 12:47:29 PM PDT 24
Peak memory 196988 kb
Host smart-d7d0d154-3144-47b8-9cee-2fa41dee65a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152434153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger.
152434153
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.3098908236
Short name T327
Test name
Test status
Simulation time 221566715 ps
CPU time 1.13 seconds
Started Jun 13 12:47:20 PM PDT 24
Finished Jun 13 12:47:22 PM PDT 24
Peak memory 196024 kb
Host smart-4bddf223-f0cb-4892-9818-64d73c680ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098908236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.3098908236
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.3769757468
Short name T216
Test name
Test status
Simulation time 55595646 ps
CPU time 1.29 seconds
Started Jun 13 12:47:18 PM PDT 24
Finished Jun 13 12:47:20 PM PDT 24
Peak memory 196932 kb
Host smart-6bf2f5ae-b062-4214-bcaa-2a4503dc8df4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769757468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.3769757468
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.4250888844
Short name T310
Test name
Test status
Simulation time 1291668530 ps
CPU time 3.72 seconds
Started Jun 13 12:47:27 PM PDT 24
Finished Jun 13 12:47:31 PM PDT 24
Peak memory 197740 kb
Host smart-f98c7dae-9983-4daa-b3a7-fb811de4ec0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250888844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.4250888844
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.2051957516
Short name T365
Test name
Test status
Simulation time 36815219 ps
CPU time 0.99 seconds
Started Jun 13 12:47:19 PM PDT 24
Finished Jun 13 12:47:21 PM PDT 24
Peak memory 196856 kb
Host smart-56da42c1-8d70-4745-aef3-fb28ed3f9b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051957516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.2051957516
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.1465160953
Short name T281
Test name
Test status
Simulation time 71602634 ps
CPU time 1.05 seconds
Started Jun 13 12:47:18 PM PDT 24
Finished Jun 13 12:47:19 PM PDT 24
Peak memory 196376 kb
Host smart-4af25b41-73f0-43e8-ba87-7bf6f25ccb31
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465160953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.1465160953
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.2791574267
Short name T199
Test name
Test status
Simulation time 141293891663 ps
CPU time 207.65 seconds
Started Jun 13 12:47:25 PM PDT 24
Finished Jun 13 12:50:53 PM PDT 24
Peak memory 198072 kb
Host smart-a98e108a-848f-4337-8d28-716dc18264ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791574267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.2791574267
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.3903282809
Short name T523
Test name
Test status
Simulation time 80593434 ps
CPU time 0.59 seconds
Started Jun 13 12:47:32 PM PDT 24
Finished Jun 13 12:47:33 PM PDT 24
Peak memory 193916 kb
Host smart-f1e8f708-c5df-4c2a-83e3-9ea8e3e35c4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903282809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.3903282809
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.414168410
Short name T313
Test name
Test status
Simulation time 148225374 ps
CPU time 0.94 seconds
Started Jun 13 12:47:25 PM PDT 24
Finished Jun 13 12:47:26 PM PDT 24
Peak memory 196384 kb
Host smart-174bfee0-cbe0-49b7-ba08-35e40b44fcda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414168410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.414168410
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.3768000042
Short name T289
Test name
Test status
Simulation time 4073123382 ps
CPU time 22.29 seconds
Started Jun 13 12:47:25 PM PDT 24
Finished Jun 13 12:47:48 PM PDT 24
Peak memory 196932 kb
Host smart-28f02aa6-677c-4024-8c3a-8193d817407e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768000042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.3768000042
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.1306535478
Short name T382
Test name
Test status
Simulation time 138162279 ps
CPU time 0.76 seconds
Started Jun 13 12:47:28 PM PDT 24
Finished Jun 13 12:47:29 PM PDT 24
Peak memory 195692 kb
Host smart-7733d75e-93f1-4754-8560-7a87abaf59ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306535478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.1306535478
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.1424207242
Short name T401
Test name
Test status
Simulation time 73809925 ps
CPU time 0.9 seconds
Started Jun 13 12:47:25 PM PDT 24
Finished Jun 13 12:47:27 PM PDT 24
Peak memory 196024 kb
Host smart-34126691-eca5-4841-bfb4-e405ffc4c354
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424207242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.1424207242
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.1986836938
Short name T122
Test name
Test status
Simulation time 55151442 ps
CPU time 1.26 seconds
Started Jun 13 12:47:28 PM PDT 24
Finished Jun 13 12:47:29 PM PDT 24
Peak memory 196448 kb
Host smart-c28ff64e-457a-4207-8a93-d7d93dc67747
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986836938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.1986836938
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.1899057056
Short name T579
Test name
Test status
Simulation time 308167306 ps
CPU time 2.48 seconds
Started Jun 13 12:47:25 PM PDT 24
Finished Jun 13 12:47:28 PM PDT 24
Peak memory 195808 kb
Host smart-1edd57a8-0454-4c23-9e22-b8330526113d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899057056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.1899057056
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.729208745
Short name T445
Test name
Test status
Simulation time 139328075 ps
CPU time 1.28 seconds
Started Jun 13 12:47:25 PM PDT 24
Finished Jun 13 12:47:27 PM PDT 24
Peak memory 198028 kb
Host smart-2f511124-592c-495c-a179-6263c1f40e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729208745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.729208745
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.1228345623
Short name T570
Test name
Test status
Simulation time 116077273 ps
CPU time 1.27 seconds
Started Jun 13 12:47:25 PM PDT 24
Finished Jun 13 12:47:27 PM PDT 24
Peak memory 197060 kb
Host smart-e992cbc8-fa76-474d-b527-65369b22d64b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228345623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.1228345623
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.1561326248
Short name T9
Test name
Test status
Simulation time 1203695840 ps
CPU time 2.69 seconds
Started Jun 13 12:47:26 PM PDT 24
Finished Jun 13 12:47:29 PM PDT 24
Peak memory 197928 kb
Host smart-2ebee2c3-f4f3-4eff-a45d-91061c376523
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561326248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.1561326248
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.2320168076
Short name T667
Test name
Test status
Simulation time 198201386 ps
CPU time 1.16 seconds
Started Jun 13 12:47:25 PM PDT 24
Finished Jun 13 12:47:27 PM PDT 24
Peak memory 195540 kb
Host smart-ec10f132-a9e7-4c28-a205-ad5dc72c0034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320168076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.2320168076
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.2870322460
Short name T322
Test name
Test status
Simulation time 24306924 ps
CPU time 0.77 seconds
Started Jun 13 12:47:25 PM PDT 24
Finished Jun 13 12:47:26 PM PDT 24
Peak memory 195024 kb
Host smart-b0a0fa88-175d-40cc-935f-a60a7b9ce2ca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870322460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.2870322460
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.3559345185
Short name T674
Test name
Test status
Simulation time 29377300968 ps
CPU time 194.94 seconds
Started Jun 13 12:47:33 PM PDT 24
Finished Jun 13 12:50:49 PM PDT 24
Peak memory 198020 kb
Host smart-8e4d2ebf-e830-43eb-8eb1-bd14833a749f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559345185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.3559345185
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.1453178718
Short name T293
Test name
Test status
Simulation time 13028856 ps
CPU time 0.58 seconds
Started Jun 13 12:47:36 PM PDT 24
Finished Jun 13 12:47:37 PM PDT 24
Peak memory 193756 kb
Host smart-7786e7fb-0522-498f-b0c7-416384bd4b86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453178718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.1453178718
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.30757587
Short name T269
Test name
Test status
Simulation time 71133417 ps
CPU time 0.86 seconds
Started Jun 13 12:47:33 PM PDT 24
Finished Jun 13 12:47:35 PM PDT 24
Peak memory 196440 kb
Host smart-d0fd9b6e-9d1f-4f3b-967d-c85e680ab327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30757587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.30757587
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.16075208
Short name T265
Test name
Test status
Simulation time 807834932 ps
CPU time 7.36 seconds
Started Jun 13 12:47:34 PM PDT 24
Finished Jun 13 12:47:42 PM PDT 24
Peak memory 196796 kb
Host smart-ec20e985-c8e4-4da5-93b8-218def53e8df
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16075208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stress
.16075208
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.1580760073
Short name T181
Test name
Test status
Simulation time 670470255 ps
CPU time 0.91 seconds
Started Jun 13 12:47:34 PM PDT 24
Finished Jun 13 12:47:35 PM PDT 24
Peak memory 197692 kb
Host smart-f61537fe-8c9b-4fb4-abaf-844209ddb881
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580760073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.1580760073
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.3812412827
Short name T132
Test name
Test status
Simulation time 53974477 ps
CPU time 0.8 seconds
Started Jun 13 12:47:34 PM PDT 24
Finished Jun 13 12:47:35 PM PDT 24
Peak memory 196176 kb
Host smart-3e9708d0-219d-464e-8599-ae988025dac6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812412827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.3812412827
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.2563671609
Short name T129
Test name
Test status
Simulation time 170738404 ps
CPU time 3.61 seconds
Started Jun 13 12:47:32 PM PDT 24
Finished Jun 13 12:47:36 PM PDT 24
Peak memory 198016 kb
Host smart-852e5b10-a3c9-4ad4-ab11-112478c012ff
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563671609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.2563671609
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.1043179106
Short name T200
Test name
Test status
Simulation time 271795401 ps
CPU time 1.79 seconds
Started Jun 13 12:47:33 PM PDT 24
Finished Jun 13 12:47:35 PM PDT 24
Peak memory 196712 kb
Host smart-2f5f0945-784d-47a7-874b-c94129f8c338
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043179106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.1043179106
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.1076457197
Short name T142
Test name
Test status
Simulation time 296959930 ps
CPU time 1.44 seconds
Started Jun 13 12:47:32 PM PDT 24
Finished Jun 13 12:47:34 PM PDT 24
Peak memory 195844 kb
Host smart-1a898d45-42bb-4184-bd5d-7f2ee70c485d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076457197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.1076457197
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.1197474145
Short name T545
Test name
Test status
Simulation time 52814441 ps
CPU time 0.74 seconds
Started Jun 13 12:47:36 PM PDT 24
Finished Jun 13 12:47:37 PM PDT 24
Peak memory 195344 kb
Host smart-ac0d4899-d083-4dc5-a823-9c5997aa578b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197474145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.1197474145
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.626687742
Short name T24
Test name
Test status
Simulation time 52691955 ps
CPU time 2.41 seconds
Started Jun 13 12:47:33 PM PDT 24
Finished Jun 13 12:47:36 PM PDT 24
Peak memory 197908 kb
Host smart-e34b4af7-a7ec-4366-b515-7426f97c0b74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626687742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ran
dom_long_reg_writes_reg_reads.626687742
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.2519279550
Short name T106
Test name
Test status
Simulation time 257167015 ps
CPU time 1.09 seconds
Started Jun 13 12:47:31 PM PDT 24
Finished Jun 13 12:47:33 PM PDT 24
Peak memory 195824 kb
Host smart-4f5b5116-b7f6-4b73-9a2f-e7f2d38240d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519279550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.2519279550
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.3089179684
Short name T464
Test name
Test status
Simulation time 294081976 ps
CPU time 1.25 seconds
Started Jun 13 12:47:33 PM PDT 24
Finished Jun 13 12:47:35 PM PDT 24
Peak memory 195712 kb
Host smart-99538ce2-fa5f-42b6-aa6a-9b1af36f5c21
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089179684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.3089179684
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.2358880764
Short name T482
Test name
Test status
Simulation time 7068632137 ps
CPU time 205.02 seconds
Started Jun 13 12:47:36 PM PDT 24
Finished Jun 13 12:51:01 PM PDT 24
Peak memory 198140 kb
Host smart-c3294353-d249-40b7-8513-60825528e4a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358880764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.2358880764
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.3515102492
Short name T563
Test name
Test status
Simulation time 34314864320 ps
CPU time 376.08 seconds
Started Jun 13 12:47:33 PM PDT 24
Finished Jun 13 12:53:50 PM PDT 24
Peak memory 198136 kb
Host smart-7422e451-368d-471e-93c7-04d79673a840
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3515102492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.3515102492
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.2568986456
Short name T690
Test name
Test status
Simulation time 34829649 ps
CPU time 0.57 seconds
Started Jun 13 12:47:38 PM PDT 24
Finished Jun 13 12:47:39 PM PDT 24
Peak memory 193680 kb
Host smart-e018bb5d-74c5-4b81-a97e-c3ebdbec2602
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568986456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.2568986456
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.4239608453
Short name T601
Test name
Test status
Simulation time 14924389 ps
CPU time 0.65 seconds
Started Jun 13 12:47:38 PM PDT 24
Finished Jun 13 12:47:39 PM PDT 24
Peak memory 193688 kb
Host smart-246010da-d167-44a7-b8f4-4d866a1a1a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239608453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.4239608453
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.2923802150
Short name T295
Test name
Test status
Simulation time 7700986339 ps
CPU time 22.36 seconds
Started Jun 13 12:47:35 PM PDT 24
Finished Jun 13 12:47:58 PM PDT 24
Peak memory 197912 kb
Host smart-624d8ec3-6881-4d7e-88e5-3840c1703e9a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923802150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.2923802150
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.3060633517
Short name T319
Test name
Test status
Simulation time 204443582 ps
CPU time 0.93 seconds
Started Jun 13 12:47:34 PM PDT 24
Finished Jun 13 12:47:35 PM PDT 24
Peak memory 197600 kb
Host smart-8f88785c-3b85-40da-a207-58648eaf80a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060633517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.3060633517
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.3842941530
Short name T657
Test name
Test status
Simulation time 354780126 ps
CPU time 1.32 seconds
Started Jun 13 12:47:34 PM PDT 24
Finished Jun 13 12:47:36 PM PDT 24
Peak memory 196964 kb
Host smart-59568d83-819e-48d8-8174-89982cac2c5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842941530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.3842941530
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.2001817996
Short name T256
Test name
Test status
Simulation time 87686161 ps
CPU time 3.71 seconds
Started Jun 13 12:47:37 PM PDT 24
Finished Jun 13 12:47:41 PM PDT 24
Peak memory 198072 kb
Host smart-75e188e1-4b40-47cf-9061-1653df9f5b69
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001817996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.2001817996
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.1173276505
Short name T488
Test name
Test status
Simulation time 481584895 ps
CPU time 2.55 seconds
Started Jun 13 12:47:37 PM PDT 24
Finished Jun 13 12:47:40 PM PDT 24
Peak memory 197040 kb
Host smart-365f5141-7845-445e-a291-8cf7a0ffcb84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173276505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.1173276505
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.1342115433
Short name T406
Test name
Test status
Simulation time 53835850 ps
CPU time 0.83 seconds
Started Jun 13 12:47:36 PM PDT 24
Finished Jun 13 12:47:37 PM PDT 24
Peak memory 195204 kb
Host smart-9ef0f4c7-ccab-4cde-b114-3624ec47f6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342115433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.1342115433
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.1861779469
Short name T450
Test name
Test status
Simulation time 355495967 ps
CPU time 1.09 seconds
Started Jun 13 12:47:35 PM PDT 24
Finished Jun 13 12:47:36 PM PDT 24
Peak memory 196600 kb
Host smart-90704db1-2715-47ff-8bbb-cd1970071ebd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861779469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.1861779469
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.3950140723
Short name T7
Test name
Test status
Simulation time 1029191124 ps
CPU time 6.34 seconds
Started Jun 13 12:47:38 PM PDT 24
Finished Jun 13 12:47:44 PM PDT 24
Peak memory 196848 kb
Host smart-f71fb91a-8dc5-4142-a0e7-e4c46fb23581
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950140723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.3950140723
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.2147161951
Short name T126
Test name
Test status
Simulation time 43248876 ps
CPU time 0.89 seconds
Started Jun 13 12:47:33 PM PDT 24
Finished Jun 13 12:47:35 PM PDT 24
Peak memory 195796 kb
Host smart-e187b9e1-cd6f-4a6c-a195-03f2a5b4495d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147161951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.2147161951
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.3967817811
Short name T329
Test name
Test status
Simulation time 52488776 ps
CPU time 1.5 seconds
Started Jun 13 12:47:35 PM PDT 24
Finished Jun 13 12:47:37 PM PDT 24
Peak memory 197900 kb
Host smart-94bd3cba-b73e-4b26-9f78-3ce082dbb8bc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967817811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.3967817811
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.3486888015
Short name T8
Test name
Test status
Simulation time 14581523502 ps
CPU time 40.35 seconds
Started Jun 13 12:47:40 PM PDT 24
Finished Jun 13 12:48:21 PM PDT 24
Peak memory 198068 kb
Host smart-9c353e5e-d9a3-4d2e-9a72-4d137ea66314
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486888015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.3486888015
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.3898054504
Short name T38
Test name
Test status
Simulation time 32016067 ps
CPU time 0.55 seconds
Started Jun 13 12:47:41 PM PDT 24
Finished Jun 13 12:47:42 PM PDT 24
Peak memory 192584 kb
Host smart-0c4ff976-d527-4347-8594-904d9f40a120
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898054504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.3898054504
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.1623946429
Short name T350
Test name
Test status
Simulation time 38044946 ps
CPU time 0.8 seconds
Started Jun 13 12:47:38 PM PDT 24
Finished Jun 13 12:47:39 PM PDT 24
Peak memory 195908 kb
Host smart-0c056011-14d7-4334-b844-95be410a7674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623946429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.1623946429
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.2730692359
Short name T454
Test name
Test status
Simulation time 289398318 ps
CPU time 16.31 seconds
Started Jun 13 12:47:39 PM PDT 24
Finished Jun 13 12:47:56 PM PDT 24
Peak memory 197028 kb
Host smart-1a8cdd71-02f9-48ce-a650-4e91679a3c38
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730692359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.2730692359
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.4180081402
Short name T607
Test name
Test status
Simulation time 31115900 ps
CPU time 0.77 seconds
Started Jun 13 12:47:39 PM PDT 24
Finished Jun 13 12:47:40 PM PDT 24
Peak memory 195720 kb
Host smart-3a6660b1-33a5-4da0-af95-bf7ff21b1a85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180081402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.4180081402
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.638322012
Short name T625
Test name
Test status
Simulation time 279730093 ps
CPU time 0.89 seconds
Started Jun 13 12:47:41 PM PDT 24
Finished Jun 13 12:47:42 PM PDT 24
Peak memory 195480 kb
Host smart-ecc646f2-08b6-493e-827c-1dd40c0ef58c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638322012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.638322012
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.3859250820
Short name T479
Test name
Test status
Simulation time 85790412 ps
CPU time 3.27 seconds
Started Jun 13 12:47:40 PM PDT 24
Finished Jun 13 12:47:44 PM PDT 24
Peak memory 198080 kb
Host smart-b2bedfbb-c3a1-4c66-9900-4ea79bb06573
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859250820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.3859250820
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.592633248
Short name T429
Test name
Test status
Simulation time 370434240 ps
CPU time 2.03 seconds
Started Jun 13 12:47:38 PM PDT 24
Finished Jun 13 12:47:41 PM PDT 24
Peak memory 195940 kb
Host smart-f0dbefe6-e1eb-48b6-8aef-9f1e5d6eae0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592633248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger.
592633248
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.1598854932
Short name T321
Test name
Test status
Simulation time 145152248 ps
CPU time 0.98 seconds
Started Jun 13 12:47:38 PM PDT 24
Finished Jun 13 12:47:39 PM PDT 24
Peak memory 195916 kb
Host smart-717b2472-52d3-42a7-abd6-05dc7768f57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598854932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.1598854932
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.1136598005
Short name T286
Test name
Test status
Simulation time 51373843 ps
CPU time 0.99 seconds
Started Jun 13 12:47:38 PM PDT 24
Finished Jun 13 12:47:40 PM PDT 24
Peak memory 195844 kb
Host smart-d375e79b-6a0b-4c3c-8ee2-ffad46c9d2a3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136598005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.1136598005
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.2011167222
Short name T185
Test name
Test status
Simulation time 1245210614 ps
CPU time 3.63 seconds
Started Jun 13 12:47:39 PM PDT 24
Finished Jun 13 12:47:43 PM PDT 24
Peak memory 197892 kb
Host smart-ad31891c-2b7e-44e4-973b-4acb90bb45b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011167222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.2011167222
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.3270380532
Short name T456
Test name
Test status
Simulation time 36406908 ps
CPU time 0.85 seconds
Started Jun 13 12:47:41 PM PDT 24
Finished Jun 13 12:47:42 PM PDT 24
Peak memory 195816 kb
Host smart-a04ec6ee-49a9-41cf-9703-49381af89a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270380532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.3270380532
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.524513410
Short name T702
Test name
Test status
Simulation time 157078822 ps
CPU time 1.48 seconds
Started Jun 13 12:47:40 PM PDT 24
Finished Jun 13 12:47:42 PM PDT 24
Peak memory 196820 kb
Host smart-6a4c7007-a39e-4bb7-ab12-9b3e730188f9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524513410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.524513410
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.3010723638
Short name T501
Test name
Test status
Simulation time 2180897042 ps
CPU time 61.5 seconds
Started Jun 13 12:47:39 PM PDT 24
Finished Jun 13 12:48:41 PM PDT 24
Peak memory 198020 kb
Host smart-2f1354ae-5630-44ff-b0e8-5726c7d3390a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010723638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.3010723638
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.3146362759
Short name T335
Test name
Test status
Simulation time 13932104 ps
CPU time 0.59 seconds
Started Jun 13 12:47:47 PM PDT 24
Finished Jun 13 12:47:49 PM PDT 24
Peak memory 194432 kb
Host smart-ec11e399-2a3b-4e9b-b0fd-ba32b3b87efc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146362759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.3146362759
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.3190797695
Short name T398
Test name
Test status
Simulation time 20105294 ps
CPU time 0.74 seconds
Started Jun 13 12:47:45 PM PDT 24
Finished Jun 13 12:47:46 PM PDT 24
Peak memory 195148 kb
Host smart-54fd6603-d536-4111-b58b-86757125b64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190797695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.3190797695
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.241312580
Short name T206
Test name
Test status
Simulation time 1796112885 ps
CPU time 28.54 seconds
Started Jun 13 12:47:48 PM PDT 24
Finished Jun 13 12:48:17 PM PDT 24
Peak memory 196644 kb
Host smart-67932977-f7c8-4dda-92c7-6361c0e40a25
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241312580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stres
s.241312580
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.2751856491
Short name T699
Test name
Test status
Simulation time 158794722 ps
CPU time 0.8 seconds
Started Jun 13 12:47:51 PM PDT 24
Finished Jun 13 12:47:52 PM PDT 24
Peak memory 195880 kb
Host smart-b4a435df-b87e-436b-8d63-5bc36aad7458
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751856491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.2751856491
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.2382542726
Short name T420
Test name
Test status
Simulation time 17563512 ps
CPU time 0.69 seconds
Started Jun 13 12:47:47 PM PDT 24
Finished Jun 13 12:47:49 PM PDT 24
Peak memory 194884 kb
Host smart-94b6a769-dd94-401f-a3f1-0c2e46158733
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382542726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.2382542726
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.1921146931
Short name T646
Test name
Test status
Simulation time 93007503 ps
CPU time 3.94 seconds
Started Jun 13 12:47:46 PM PDT 24
Finished Jun 13 12:47:51 PM PDT 24
Peak memory 198000 kb
Host smart-fe69ca5a-924a-4b87-a879-532d0ef0cdb8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921146931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.1921146931
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.3309809442
Short name T144
Test name
Test status
Simulation time 54200534 ps
CPU time 1.4 seconds
Started Jun 13 12:47:46 PM PDT 24
Finished Jun 13 12:47:48 PM PDT 24
Peak memory 197348 kb
Host smart-e5aab9f5-754c-4e42-bb9a-1395e1842431
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309809442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.3309809442
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.3225440989
Short name T395
Test name
Test status
Simulation time 78454567 ps
CPU time 1.34 seconds
Started Jun 13 12:47:45 PM PDT 24
Finished Jun 13 12:47:47 PM PDT 24
Peak memory 196908 kb
Host smart-ced13618-8a56-4ca3-9b43-59854ada85c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225440989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.3225440989
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.3875286930
Short name T63
Test name
Test status
Simulation time 111818852 ps
CPU time 1.09 seconds
Started Jun 13 12:47:46 PM PDT 24
Finished Jun 13 12:47:48 PM PDT 24
Peak memory 196648 kb
Host smart-68011cf6-f63a-4f03-a1b9-03e9fe5eaeba
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875286930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.3875286930
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.1107721982
Short name T520
Test name
Test status
Simulation time 70005489 ps
CPU time 3.38 seconds
Started Jun 13 12:47:48 PM PDT 24
Finished Jun 13 12:47:52 PM PDT 24
Peak memory 197896 kb
Host smart-2564c117-cc63-4a5e-b110-30a72bfc0e6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107721982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.1107721982
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.1169698532
Short name T465
Test name
Test status
Simulation time 301092678 ps
CPU time 1.38 seconds
Started Jun 13 12:47:40 PM PDT 24
Finished Jun 13 12:47:42 PM PDT 24
Peak memory 197884 kb
Host smart-70276b4d-e3d7-45aa-9f4a-e6e746f98dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169698532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.1169698532
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.4144640910
Short name T593
Test name
Test status
Simulation time 168616001 ps
CPU time 1.04 seconds
Started Jun 13 12:47:46 PM PDT 24
Finished Jun 13 12:47:48 PM PDT 24
Peak memory 196200 kb
Host smart-23636e8c-5aee-416f-95d3-988e44d1958b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144640910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.4144640910
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.251544343
Short name T6
Test name
Test status
Simulation time 14863367395 ps
CPU time 179.67 seconds
Started Jun 13 12:47:46 PM PDT 24
Finished Jun 13 12:50:47 PM PDT 24
Peak memory 197936 kb
Host smart-26ab3d3b-5cf8-406a-a995-303a2645b33f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251544343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.g
pio_stress_all.251544343
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.3391217739
Short name T583
Test name
Test status
Simulation time 55579670466 ps
CPU time 1778.85 seconds
Started Jun 13 12:47:46 PM PDT 24
Finished Jun 13 01:17:25 PM PDT 24
Peak memory 198172 kb
Host smart-a64783bb-a759-4db1-a05f-b76a21b07f44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3391217739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.3391217739
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.280567865
Short name T587
Test name
Test status
Simulation time 25319781 ps
CPU time 0.57 seconds
Started Jun 13 12:47:58 PM PDT 24
Finished Jun 13 12:47:59 PM PDT 24
Peak memory 194440 kb
Host smart-aeb6d76b-2056-4b79-b051-5aca26a1e892
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280567865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.280567865
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.1464760570
Short name T263
Test name
Test status
Simulation time 65104724 ps
CPU time 0.72 seconds
Started Jun 13 12:47:48 PM PDT 24
Finished Jun 13 12:47:50 PM PDT 24
Peak memory 194076 kb
Host smart-bee37da8-8831-46ff-85a8-1ce99bf9daf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464760570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.1464760570
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.1459600922
Short name T160
Test name
Test status
Simulation time 2779998641 ps
CPU time 16.78 seconds
Started Jun 13 12:47:47 PM PDT 24
Finished Jun 13 12:48:05 PM PDT 24
Peak memory 196716 kb
Host smart-2fdca69c-9bc4-47d5-8717-6ce9f9da9f56
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459600922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.1459600922
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.1977690880
Short name T320
Test name
Test status
Simulation time 76631113 ps
CPU time 0.67 seconds
Started Jun 13 12:47:52 PM PDT 24
Finished Jun 13 12:47:53 PM PDT 24
Peak memory 194584 kb
Host smart-55e51a7f-851e-4f89-93b8-c12ebe07abf3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977690880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.1977690880
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.3922215627
Short name T506
Test name
Test status
Simulation time 110171050 ps
CPU time 1.41 seconds
Started Jun 13 12:47:49 PM PDT 24
Finished Jun 13 12:47:51 PM PDT 24
Peak memory 197040 kb
Host smart-2fdd2e4f-8285-45b1-8643-a7a09fd21790
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922215627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.3922215627
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.127327975
Short name T517
Test name
Test status
Simulation time 73565574 ps
CPU time 2.93 seconds
Started Jun 13 12:47:46 PM PDT 24
Finished Jun 13 12:47:50 PM PDT 24
Peak memory 198080 kb
Host smart-fb98ffcd-7fda-400b-b5b0-3cacf872c231
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127327975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.gpio_intr_with_filter_rand_intr_event.127327975
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.3520114966
Short name T686
Test name
Test status
Simulation time 103203156 ps
CPU time 2.45 seconds
Started Jun 13 12:47:47 PM PDT 24
Finished Jun 13 12:47:51 PM PDT 24
Peak memory 198012 kb
Host smart-109af6f3-dc07-48a0-aeb1-9bcbedb3ad03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520114966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.3520114966
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.3490437125
Short name T163
Test name
Test status
Simulation time 50836265 ps
CPU time 0.68 seconds
Started Jun 13 12:47:48 PM PDT 24
Finished Jun 13 12:47:49 PM PDT 24
Peak memory 194184 kb
Host smart-748a7217-8b5d-4977-b007-b3b8f082f68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490437125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.3490437125
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.54730970
Short name T274
Test name
Test status
Simulation time 338901046 ps
CPU time 1.37 seconds
Started Jun 13 12:47:46 PM PDT 24
Finished Jun 13 12:47:48 PM PDT 24
Peak memory 195752 kb
Host smart-ee9cd163-c610-46d6-8c08-efeb50001611
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54730970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullup_
pulldown.54730970
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.1370677554
Short name T159
Test name
Test status
Simulation time 781312967 ps
CPU time 5.64 seconds
Started Jun 13 12:47:46 PM PDT 24
Finished Jun 13 12:47:52 PM PDT 24
Peak memory 197932 kb
Host smart-76e0bc1d-aa6b-4163-8281-9cd238a201fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370677554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.1370677554
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.928329525
Short name T54
Test name
Test status
Simulation time 143945039 ps
CPU time 1.25 seconds
Started Jun 13 12:47:47 PM PDT 24
Finished Jun 13 12:47:50 PM PDT 24
Peak memory 196204 kb
Host smart-8ea7dff4-2f0b-4952-b219-864ce96e0ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928329525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.928329525
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.829423291
Short name T246
Test name
Test status
Simulation time 95003946 ps
CPU time 0.94 seconds
Started Jun 13 12:47:47 PM PDT 24
Finished Jun 13 12:47:49 PM PDT 24
Peak memory 195988 kb
Host smart-c4ad7e79-0935-4e7a-a430-b3e0c1283416
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829423291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.829423291
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.2805277052
Short name T138
Test name
Test status
Simulation time 14348052385 ps
CPU time 163 seconds
Started Jun 13 12:47:51 PM PDT 24
Finished Jun 13 12:50:35 PM PDT 24
Peak memory 198092 kb
Host smart-b680641d-3a7b-4800-ace3-6d0a14191670
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805277052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.2805277052
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.3407158809
Short name T514
Test name
Test status
Simulation time 34374842 ps
CPU time 0.58 seconds
Started Jun 13 12:46:01 PM PDT 24
Finished Jun 13 12:46:02 PM PDT 24
Peak memory 194328 kb
Host smart-0161cddc-7b5a-4b0d-8b95-19be4c38fcaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407158809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.3407158809
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.3354209873
Short name T167
Test name
Test status
Simulation time 129335043 ps
CPU time 0.88 seconds
Started Jun 13 12:45:48 PM PDT 24
Finished Jun 13 12:45:49 PM PDT 24
Peak memory 195948 kb
Host smart-7bb48c0e-c6d3-46db-bda4-01edf1d322d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354209873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.3354209873
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.302397449
Short name T231
Test name
Test status
Simulation time 515184397 ps
CPU time 13.21 seconds
Started Jun 13 12:45:52 PM PDT 24
Finished Jun 13 12:46:06 PM PDT 24
Peak memory 197972 kb
Host smart-a2fd673f-5212-416e-9ad6-dfe6f6c222ab
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302397449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stress
.302397449
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.3705832523
Short name T490
Test name
Test status
Simulation time 93794231 ps
CPU time 0.78 seconds
Started Jun 13 12:45:52 PM PDT 24
Finished Jun 13 12:45:53 PM PDT 24
Peak memory 195788 kb
Host smart-1cf26ab4-ac49-482e-8a61-07157484464c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705832523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.3705832523
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.2986874107
Short name T180
Test name
Test status
Simulation time 84021841 ps
CPU time 1.42 seconds
Started Jun 13 12:45:48 PM PDT 24
Finished Jun 13 12:45:50 PM PDT 24
Peak memory 197844 kb
Host smart-9c2d5766-f158-4598-85cc-edb4a5680d29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986874107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.2986874107
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.762978104
Short name T591
Test name
Test status
Simulation time 75981918 ps
CPU time 3.09 seconds
Started Jun 13 12:45:52 PM PDT 24
Finished Jun 13 12:45:56 PM PDT 24
Peak memory 198096 kb
Host smart-38980270-5f5a-4385-bae9-995c04d02347
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762978104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.gpio_intr_with_filter_rand_intr_event.762978104
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.2542622391
Short name T564
Test name
Test status
Simulation time 172599298 ps
CPU time 1.15 seconds
Started Jun 13 12:45:49 PM PDT 24
Finished Jun 13 12:45:51 PM PDT 24
Peak memory 196084 kb
Host smart-e4b7e2f9-d5f2-42fa-b4d1-2c8962614770
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542622391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
2542622391
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.2888256297
Short name T628
Test name
Test status
Simulation time 49501136 ps
CPU time 1.15 seconds
Started Jun 13 12:45:49 PM PDT 24
Finished Jun 13 12:45:50 PM PDT 24
Peak memory 196052 kb
Host smart-bd36ff27-36a2-4cf4-a072-8fcc810f9172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888256297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.2888256297
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.3768521058
Short name T52
Test name
Test status
Simulation time 36046026 ps
CPU time 0.9 seconds
Started Jun 13 12:45:49 PM PDT 24
Finished Jun 13 12:45:51 PM PDT 24
Peak memory 197284 kb
Host smart-0b68da54-7e1f-415d-8b06-e829dc4cbdb5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768521058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.3768521058
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.2582133760
Short name T118
Test name
Test status
Simulation time 93175369 ps
CPU time 1.2 seconds
Started Jun 13 12:45:50 PM PDT 24
Finished Jun 13 12:45:52 PM PDT 24
Peak memory 197056 kb
Host smart-5c924955-4d35-49d9-99c7-d20a2e413be3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582133760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.2582133760
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.4216982653
Short name T35
Test name
Test status
Simulation time 95582508 ps
CPU time 0.96 seconds
Started Jun 13 12:45:53 PM PDT 24
Finished Jun 13 12:45:54 PM PDT 24
Peak memory 214832 kb
Host smart-7871c123-4e4e-48f2-a71b-15b722482633
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216982653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.4216982653
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.369322124
Short name T290
Test name
Test status
Simulation time 143536552 ps
CPU time 1.26 seconds
Started Jun 13 12:45:47 PM PDT 24
Finished Jun 13 12:45:49 PM PDT 24
Peak memory 195504 kb
Host smart-aa8efcd4-8a98-4afe-a85b-2cf039fb460b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369322124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.369322124
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.2151534736
Short name T296
Test name
Test status
Simulation time 65248233 ps
CPU time 1.03 seconds
Started Jun 13 12:45:47 PM PDT 24
Finished Jun 13 12:45:48 PM PDT 24
Peak memory 195704 kb
Host smart-32e351b2-142a-435f-a280-397770d4e637
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151534736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.2151534736
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.2896058897
Short name T627
Test name
Test status
Simulation time 32772893737 ps
CPU time 121.42 seconds
Started Jun 13 12:45:53 PM PDT 24
Finished Jun 13 12:47:54 PM PDT 24
Peak memory 198088 kb
Host smart-5a6af78e-52b3-465d-9841-3bc20712f37c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896058897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.2896058897
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.1299285609
Short name T455
Test name
Test status
Simulation time 15630608 ps
CPU time 0.57 seconds
Started Jun 13 12:47:57 PM PDT 24
Finished Jun 13 12:47:58 PM PDT 24
Peak memory 193968 kb
Host smart-928a7b4c-13d1-4dd8-b459-a08246ee9166
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299285609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.1299285609
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.840502132
Short name T621
Test name
Test status
Simulation time 42181805 ps
CPU time 0.95 seconds
Started Jun 13 12:47:52 PM PDT 24
Finished Jun 13 12:47:54 PM PDT 24
Peak memory 195920 kb
Host smart-8a674847-8b18-454d-a084-ca5af5e04a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840502132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.840502132
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.2277130983
Short name T533
Test name
Test status
Simulation time 350721164 ps
CPU time 5.82 seconds
Started Jun 13 12:47:54 PM PDT 24
Finished Jun 13 12:48:00 PM PDT 24
Peak memory 196180 kb
Host smart-0e3aa4c3-58bd-4ca9-9736-171f05a660bf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277130983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.2277130983
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.750523736
Short name T675
Test name
Test status
Simulation time 57096244 ps
CPU time 0.88 seconds
Started Jun 13 12:47:51 PM PDT 24
Finished Jun 13 12:47:53 PM PDT 24
Peak memory 195796 kb
Host smart-6376b269-2ff8-4907-a54f-9a78513d751e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750523736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.750523736
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.1287562293
Short name T130
Test name
Test status
Simulation time 382147591 ps
CPU time 1.36 seconds
Started Jun 13 12:47:52 PM PDT 24
Finished Jun 13 12:47:54 PM PDT 24
Peak memory 197176 kb
Host smart-4e0729f8-db22-4457-ac03-f1ff062f346a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287562293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.1287562293
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.4266597229
Short name T194
Test name
Test status
Simulation time 83187439 ps
CPU time 3.21 seconds
Started Jun 13 12:47:51 PM PDT 24
Finished Jun 13 12:47:55 PM PDT 24
Peak memory 198336 kb
Host smart-9f6bb36f-ca25-4cf6-8625-7680d0c7c206
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266597229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.4266597229
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.2789799663
Short name T110
Test name
Test status
Simulation time 190092895 ps
CPU time 3 seconds
Started Jun 13 12:47:52 PM PDT 24
Finished Jun 13 12:47:56 PM PDT 24
Peak memory 195776 kb
Host smart-54559b5d-7e05-4634-87b6-e2ec23524091
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789799663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.2789799663
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.3703601571
Short name T433
Test name
Test status
Simulation time 22063281 ps
CPU time 0.95 seconds
Started Jun 13 12:47:53 PM PDT 24
Finished Jun 13 12:47:54 PM PDT 24
Peak memory 195696 kb
Host smart-7e2ce478-44dc-46f5-a53e-7e1413461a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703601571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.3703601571
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.3461062834
Short name T555
Test name
Test status
Simulation time 49186262 ps
CPU time 0.64 seconds
Started Jun 13 12:47:58 PM PDT 24
Finished Jun 13 12:48:00 PM PDT 24
Peak memory 194200 kb
Host smart-68e52664-3dd1-4c80-b5f0-f40a1e840176
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461062834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.3461062834
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.2924122108
Short name T648
Test name
Test status
Simulation time 459391581 ps
CPU time 5.29 seconds
Started Jun 13 12:47:54 PM PDT 24
Finished Jun 13 12:48:00 PM PDT 24
Peak memory 197900 kb
Host smart-b196a5f4-7834-4510-adf9-ee0d00afd89c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924122108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.2924122108
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.902886244
Short name T451
Test name
Test status
Simulation time 73110142 ps
CPU time 1.25 seconds
Started Jun 13 12:47:51 PM PDT 24
Finished Jun 13 12:47:53 PM PDT 24
Peak memory 195492 kb
Host smart-6bfb878d-f47b-4265-8dff-5279ac0c62e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902886244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.902886244
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.4121041041
Short name T375
Test name
Test status
Simulation time 62584705 ps
CPU time 1.31 seconds
Started Jun 13 12:47:53 PM PDT 24
Finished Jun 13 12:47:55 PM PDT 24
Peak memory 195648 kb
Host smart-a52fdf9c-7b05-4c0b-9dd2-0289def615c8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121041041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.4121041041
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.2908739110
Short name T634
Test name
Test status
Simulation time 30478456859 ps
CPU time 98.41 seconds
Started Jun 13 12:47:51 PM PDT 24
Finished Jun 13 12:49:30 PM PDT 24
Peak memory 191648 kb
Host smart-94b3e278-d6ec-438f-972d-8710f216793e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908739110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.2908739110
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.319746158
Short name T264
Test name
Test status
Simulation time 59340512 ps
CPU time 0.58 seconds
Started Jun 13 12:48:00 PM PDT 24
Finished Jun 13 12:48:01 PM PDT 24
Peak memory 193748 kb
Host smart-2cdb3e2d-126c-461f-82a0-c1901ccbed78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319746158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.319746158
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.4239834378
Short name T642
Test name
Test status
Simulation time 110488632 ps
CPU time 0.93 seconds
Started Jun 13 12:47:51 PM PDT 24
Finished Jun 13 12:47:53 PM PDT 24
Peak memory 195836 kb
Host smart-381767bf-e7f0-4518-bd58-9e4ff3e8b032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239834378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.4239834378
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.4180314022
Short name T411
Test name
Test status
Simulation time 504280435 ps
CPU time 18.23 seconds
Started Jun 13 12:48:00 PM PDT 24
Finished Jun 13 12:48:19 PM PDT 24
Peak memory 196876 kb
Host smart-c8a8c79a-29df-4dc2-8d28-e00e4129a0af
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180314022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.4180314022
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.555807276
Short name T49
Test name
Test status
Simulation time 31712073 ps
CPU time 0.76 seconds
Started Jun 13 12:47:59 PM PDT 24
Finished Jun 13 12:48:01 PM PDT 24
Peak memory 194480 kb
Host smart-29614f0b-e176-4499-bc08-da210d3f04b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555807276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.555807276
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.4019451627
Short name T23
Test name
Test status
Simulation time 74842466 ps
CPU time 0.97 seconds
Started Jun 13 12:48:00 PM PDT 24
Finished Jun 13 12:48:02 PM PDT 24
Peak memory 196300 kb
Host smart-6e211299-7e17-4a61-b4c8-50beccc70821
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019451627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.4019451627
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.3895307531
Short name T666
Test name
Test status
Simulation time 64022289 ps
CPU time 2.91 seconds
Started Jun 13 12:47:59 PM PDT 24
Finished Jun 13 12:48:02 PM PDT 24
Peak memory 198108 kb
Host smart-d2d35d4b-b66f-4717-8a19-1e852902554e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895307531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.3895307531
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.2343818733
Short name T676
Test name
Test status
Simulation time 89661622 ps
CPU time 2.47 seconds
Started Jun 13 12:47:59 PM PDT 24
Finished Jun 13 12:48:02 PM PDT 24
Peak memory 196676 kb
Host smart-f37d94d4-f2b6-49cc-be77-c3a4e578d292
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343818733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.2343818733
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.2077711557
Short name T655
Test name
Test status
Simulation time 34650232 ps
CPU time 1.23 seconds
Started Jun 13 12:47:59 PM PDT 24
Finished Jun 13 12:48:01 PM PDT 24
Peak memory 197980 kb
Host smart-cca06e2f-8672-45d4-8297-3a54a1594e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077711557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.2077711557
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.3637776334
Short name T708
Test name
Test status
Simulation time 161475753 ps
CPU time 0.7 seconds
Started Jun 13 12:47:54 PM PDT 24
Finished Jun 13 12:47:55 PM PDT 24
Peak memory 196020 kb
Host smart-b67a5334-762e-44ac-ade8-fbbc25556c74
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637776334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.3637776334
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.3794334399
Short name T360
Test name
Test status
Simulation time 482662541 ps
CPU time 3.24 seconds
Started Jun 13 12:48:00 PM PDT 24
Finished Jun 13 12:48:04 PM PDT 24
Peak memory 197964 kb
Host smart-3de316b5-205f-462f-a4b3-a50a546ff203
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794334399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.3794334399
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.1258257795
Short name T210
Test name
Test status
Simulation time 188204410 ps
CPU time 1.29 seconds
Started Jun 13 12:47:57 PM PDT 24
Finished Jun 13 12:47:59 PM PDT 24
Peak memory 195496 kb
Host smart-0895d59f-d74d-4acb-9328-04d6ab0b5e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258257795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.1258257795
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2900257943
Short name T229
Test name
Test status
Simulation time 95784300 ps
CPU time 1.04 seconds
Started Jun 13 12:47:54 PM PDT 24
Finished Jun 13 12:47:56 PM PDT 24
Peak memory 196528 kb
Host smart-63166ff9-70b6-4194-9858-7d7b07e6a7d6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900257943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.2900257943
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.2398019241
Short name T577
Test name
Test status
Simulation time 30026763910 ps
CPU time 215.34 seconds
Started Jun 13 12:48:00 PM PDT 24
Finished Jun 13 12:51:36 PM PDT 24
Peak memory 198068 kb
Host smart-ebd6970d-8a5f-4b7f-8ff3-8446a62649b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398019241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.2398019241
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.469005567
Short name T535
Test name
Test status
Simulation time 18383862 ps
CPU time 0.61 seconds
Started Jun 13 12:48:12 PM PDT 24
Finished Jun 13 12:48:13 PM PDT 24
Peak memory 194684 kb
Host smart-d0766bbd-cf67-47a0-b04e-458deb5cd44d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469005567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.469005567
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.4190368778
Short name T624
Test name
Test status
Simulation time 31131535 ps
CPU time 0.83 seconds
Started Jun 13 12:48:00 PM PDT 24
Finished Jun 13 12:48:01 PM PDT 24
Peak memory 195244 kb
Host smart-0453cb11-b74d-4f16-b8e5-8d8aaef0bef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190368778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.4190368778
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.4119066374
Short name T128
Test name
Test status
Simulation time 545781463 ps
CPU time 15.37 seconds
Started Jun 13 12:48:01 PM PDT 24
Finished Jun 13 12:48:17 PM PDT 24
Peak memory 195492 kb
Host smart-bb31b56a-ee8b-43a5-912f-c79a5a3a56ac
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119066374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.4119066374
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.1814098919
Short name T494
Test name
Test status
Simulation time 170712542 ps
CPU time 0.76 seconds
Started Jun 13 12:48:02 PM PDT 24
Finished Jun 13 12:48:03 PM PDT 24
Peak memory 195380 kb
Host smart-0690c4bd-a294-4408-a7f9-844acd60a8dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814098919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.1814098919
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.2731893525
Short name T614
Test name
Test status
Simulation time 57466615 ps
CPU time 0.65 seconds
Started Jun 13 12:48:01 PM PDT 24
Finished Jun 13 12:48:02 PM PDT 24
Peak memory 194100 kb
Host smart-71bba674-de17-4abc-8f51-77115864ac71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731893525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.2731893525
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.3117129196
Short name T68
Test name
Test status
Simulation time 145613393 ps
CPU time 3.03 seconds
Started Jun 13 12:48:02 PM PDT 24
Finished Jun 13 12:48:06 PM PDT 24
Peak memory 196296 kb
Host smart-9a967d4e-be6f-43f6-b2e6-070f5f66061a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117129196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.3117129196
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.2001215738
Short name T541
Test name
Test status
Simulation time 188981069 ps
CPU time 3.13 seconds
Started Jun 13 12:47:59 PM PDT 24
Finished Jun 13 12:48:02 PM PDT 24
Peak memory 197080 kb
Host smart-63c2a59a-18f2-4414-a32c-b806b724f53a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001215738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.2001215738
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.2218603322
Short name T324
Test name
Test status
Simulation time 53612591 ps
CPU time 0.85 seconds
Started Jun 13 12:47:59 PM PDT 24
Finished Jun 13 12:48:01 PM PDT 24
Peak memory 196428 kb
Host smart-4f2a6d14-16d3-49f7-bdbe-bbf237a0f57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218603322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.2218603322
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.1492105807
Short name T165
Test name
Test status
Simulation time 98766015 ps
CPU time 1.15 seconds
Started Jun 13 12:48:02 PM PDT 24
Finished Jun 13 12:48:03 PM PDT 24
Peak memory 195756 kb
Host smart-7453207a-d7d5-4774-8bba-a8bc33ba2c28
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492105807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.1492105807
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.4196515528
Short name T709
Test name
Test status
Simulation time 361887878 ps
CPU time 2.43 seconds
Started Jun 13 12:48:01 PM PDT 24
Finished Jun 13 12:48:04 PM PDT 24
Peak memory 197888 kb
Host smart-8d45651e-c2a9-4bcb-80da-564069756b59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196515528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.4196515528
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.3693200370
Short name T645
Test name
Test status
Simulation time 148551028 ps
CPU time 1.27 seconds
Started Jun 13 12:48:01 PM PDT 24
Finished Jun 13 12:48:03 PM PDT 24
Peak memory 196696 kb
Host smart-cc39e73a-6cae-4d92-9cac-aeca5321f7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693200370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.3693200370
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.1379499452
Short name T615
Test name
Test status
Simulation time 27947352 ps
CPU time 0.78 seconds
Started Jun 13 12:47:59 PM PDT 24
Finished Jun 13 12:48:01 PM PDT 24
Peak memory 195144 kb
Host smart-1513d5f2-775a-41f9-acca-3baf279fcf18
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379499452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.1379499452
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.3143887918
Short name T5
Test name
Test status
Simulation time 88522640029 ps
CPU time 179.44 seconds
Started Jun 13 12:47:59 PM PDT 24
Finished Jun 13 12:50:58 PM PDT 24
Peak memory 198064 kb
Host smart-42b3777d-2f6b-4fc7-a56a-e8936e2e31f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143887918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.3143887918
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.2171554802
Short name T166
Test name
Test status
Simulation time 18283999 ps
CPU time 0.57 seconds
Started Jun 13 12:48:06 PM PDT 24
Finished Jun 13 12:48:07 PM PDT 24
Peak memory 193680 kb
Host smart-bfbce017-d25e-4a36-b396-eeb42f922c7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171554802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.2171554802
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.329227160
Short name T205
Test name
Test status
Simulation time 18643196 ps
CPU time 0.7 seconds
Started Jun 13 12:48:04 PM PDT 24
Finished Jun 13 12:48:05 PM PDT 24
Peak memory 194020 kb
Host smart-402e631d-28ac-4bf0-acf4-3afdb2a83b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329227160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.329227160
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.2872875840
Short name T698
Test name
Test status
Simulation time 2105860425 ps
CPU time 27.83 seconds
Started Jun 13 12:48:08 PM PDT 24
Finished Jun 13 12:48:36 PM PDT 24
Peak memory 197916 kb
Host smart-f3813786-7beb-44ca-8d7f-3fb3550ba388
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872875840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.2872875840
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.1078708891
Short name T307
Test name
Test status
Simulation time 35137197 ps
CPU time 0.76 seconds
Started Jun 13 12:48:11 PM PDT 24
Finished Jun 13 12:48:13 PM PDT 24
Peak memory 196328 kb
Host smart-c068324b-583d-4c9c-97e1-43581e2a1648
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078708891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.1078708891
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.4127568276
Short name T582
Test name
Test status
Simulation time 400001821 ps
CPU time 1.51 seconds
Started Jun 13 12:48:05 PM PDT 24
Finished Jun 13 12:48:07 PM PDT 24
Peak memory 197028 kb
Host smart-2b5f7a40-b952-4526-ba83-49c07fe28c9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127568276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.4127568276
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.2782423357
Short name T651
Test name
Test status
Simulation time 98803845 ps
CPU time 0.99 seconds
Started Jun 13 12:48:12 PM PDT 24
Finished Jun 13 12:48:13 PM PDT 24
Peak memory 196012 kb
Host smart-67edb9ec-2152-4f57-939f-b71ead97f162
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782423357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.2782423357
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.178350338
Short name T219
Test name
Test status
Simulation time 395419103 ps
CPU time 2.42 seconds
Started Jun 13 12:48:05 PM PDT 24
Finished Jun 13 12:48:08 PM PDT 24
Peak memory 197044 kb
Host smart-c35b2fa1-c01a-4fce-8b6c-8ff5c6a04186
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178350338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger.
178350338
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.3516764977
Short name T187
Test name
Test status
Simulation time 60760371 ps
CPU time 0.76 seconds
Started Jun 13 12:48:11 PM PDT 24
Finished Jun 13 12:48:12 PM PDT 24
Peak memory 196032 kb
Host smart-85936da1-99ec-419f-9b2c-abf5fdae7549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516764977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.3516764977
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.2258547523
Short name T712
Test name
Test status
Simulation time 29161189 ps
CPU time 0.66 seconds
Started Jun 13 12:48:06 PM PDT 24
Finished Jun 13 12:48:07 PM PDT 24
Peak memory 194164 kb
Host smart-e0b7c992-680a-496f-938d-74aa4018b07e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258547523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.2258547523
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.3121296246
Short name T461
Test name
Test status
Simulation time 84821540 ps
CPU time 1.19 seconds
Started Jun 13 12:48:07 PM PDT 24
Finished Jun 13 12:48:08 PM PDT 24
Peak memory 197856 kb
Host smart-7e5019bf-1c3d-420a-a1e4-a892b82ffb89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121296246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.3121296246
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.2357043882
Short name T515
Test name
Test status
Simulation time 48311266 ps
CPU time 1.05 seconds
Started Jun 13 12:48:05 PM PDT 24
Finished Jun 13 12:48:07 PM PDT 24
Peak memory 195660 kb
Host smart-7d77d1b4-bc30-4b47-8bec-465d5901f859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357043882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.2357043882
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.808192930
Short name T547
Test name
Test status
Simulation time 44302227 ps
CPU time 1.29 seconds
Started Jun 13 12:48:06 PM PDT 24
Finished Jun 13 12:48:08 PM PDT 24
Peak memory 196644 kb
Host smart-63cc51e1-99e5-4972-b258-19ba233c502e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808192930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.808192930
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.1922995152
Short name T325
Test name
Test status
Simulation time 3408341656 ps
CPU time 20.76 seconds
Started Jun 13 12:48:05 PM PDT 24
Finished Jun 13 12:48:26 PM PDT 24
Peak memory 198084 kb
Host smart-4a100c1b-24e7-410f-b28d-9a45bd2f21b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922995152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.1922995152
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.3828196025
Short name T190
Test name
Test status
Simulation time 16584801 ps
CPU time 0.54 seconds
Started Jun 13 12:48:14 PM PDT 24
Finished Jun 13 12:48:15 PM PDT 24
Peak memory 193316 kb
Host smart-875b17c7-e628-49b1-b829-9521e41689f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828196025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.3828196025
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.474932728
Short name T217
Test name
Test status
Simulation time 49150342 ps
CPU time 0.63 seconds
Started Jun 13 12:48:13 PM PDT 24
Finished Jun 13 12:48:15 PM PDT 24
Peak memory 193916 kb
Host smart-7cb6997d-963e-4715-b288-8df56b6fa263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474932728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.474932728
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.3599328972
Short name T331
Test name
Test status
Simulation time 591917526 ps
CPU time 4.72 seconds
Started Jun 13 12:48:22 PM PDT 24
Finished Jun 13 12:48:28 PM PDT 24
Peak memory 196204 kb
Host smart-1cd02808-aab8-434f-884f-03c216830e4a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599328972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.3599328972
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.2998172634
Short name T525
Test name
Test status
Simulation time 1083958607 ps
CPU time 0.95 seconds
Started Jun 13 12:48:18 PM PDT 24
Finished Jun 13 12:48:20 PM PDT 24
Peak memory 197012 kb
Host smart-379c2cb3-324e-40a2-9898-68ecaea4dec2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998172634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.2998172634
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.701792862
Short name T308
Test name
Test status
Simulation time 58122239 ps
CPU time 1.07 seconds
Started Jun 13 12:48:13 PM PDT 24
Finished Jun 13 12:48:15 PM PDT 24
Peak memory 195692 kb
Host smart-adce22ab-fe35-4f54-90b0-39e4ae2e54cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701792862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.701792862
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.1051256902
Short name T603
Test name
Test status
Simulation time 323474918 ps
CPU time 2.77 seconds
Started Jun 13 12:48:13 PM PDT 24
Finished Jun 13 12:48:16 PM PDT 24
Peak memory 196460 kb
Host smart-319d8be7-3a92-4228-bee8-0981a70c7932
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051256902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.1051256902
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.3169554894
Short name T285
Test name
Test status
Simulation time 88819524 ps
CPU time 2.02 seconds
Started Jun 13 12:48:22 PM PDT 24
Finished Jun 13 12:48:25 PM PDT 24
Peak memory 197128 kb
Host smart-8ef9a176-a37e-439d-9802-63898131d141
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169554894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.3169554894
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.1802401767
Short name T484
Test name
Test status
Simulation time 48980024 ps
CPU time 0.77 seconds
Started Jun 13 12:48:14 PM PDT 24
Finished Jun 13 12:48:15 PM PDT 24
Peak memory 196020 kb
Host smart-888d0a66-5bf4-4ed8-850f-aaa19855d133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802401767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.1802401767
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.3431252020
Short name T578
Test name
Test status
Simulation time 62694309 ps
CPU time 1.29 seconds
Started Jun 13 12:48:13 PM PDT 24
Finished Jun 13 12:48:14 PM PDT 24
Peak memory 195768 kb
Host smart-0cafe417-3c89-43c7-808f-84fb413a0b24
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431252020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.3431252020
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.2522036189
Short name T656
Test name
Test status
Simulation time 365129053 ps
CPU time 2.48 seconds
Started Jun 13 12:48:19 PM PDT 24
Finished Jun 13 12:48:22 PM PDT 24
Peak memory 197744 kb
Host smart-f93290d2-067d-4cd5-9550-d3c8648e4bc1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522036189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.2522036189
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.1494421480
Short name T419
Test name
Test status
Simulation time 37721942 ps
CPU time 1.21 seconds
Started Jun 13 12:48:04 PM PDT 24
Finished Jun 13 12:48:06 PM PDT 24
Peak memory 197052 kb
Host smart-c6bc1d89-0c72-4856-9ff7-46da0b865631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494421480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.1494421480
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.556163860
Short name T480
Test name
Test status
Simulation time 73029693 ps
CPU time 1.46 seconds
Started Jun 13 12:48:12 PM PDT 24
Finished Jun 13 12:48:13 PM PDT 24
Peak memory 195484 kb
Host smart-35680fcd-3276-4090-a8d1-160945923c49
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556163860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.556163860
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.1809304565
Short name T336
Test name
Test status
Simulation time 4478438122 ps
CPU time 48.13 seconds
Started Jun 13 12:48:18 PM PDT 24
Finished Jun 13 12:49:07 PM PDT 24
Peak memory 197992 kb
Host smart-5b142430-4306-4327-b662-5843d150fa10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809304565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.1809304565
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.683726065
Short name T232
Test name
Test status
Simulation time 80754847 ps
CPU time 0.56 seconds
Started Jun 13 12:48:24 PM PDT 24
Finished Jun 13 12:48:25 PM PDT 24
Peak memory 193964 kb
Host smart-88f70325-0954-4b44-9579-75c43f830957
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683726065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.683726065
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.1190494491
Short name T188
Test name
Test status
Simulation time 123625840 ps
CPU time 0.74 seconds
Started Jun 13 12:48:14 PM PDT 24
Finished Jun 13 12:48:15 PM PDT 24
Peak memory 195212 kb
Host smart-8b811bb9-7199-4d67-832b-bb3bc51b3ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190494491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.1190494491
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.2230083392
Short name T600
Test name
Test status
Simulation time 1741978268 ps
CPU time 24.38 seconds
Started Jun 13 12:48:21 PM PDT 24
Finished Jun 13 12:48:46 PM PDT 24
Peak memory 195468 kb
Host smart-706d0f56-90bf-4cfc-8ca6-a1d83d7ebb2d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230083392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.2230083392
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.3463182696
Short name T391
Test name
Test status
Simulation time 325523584 ps
CPU time 0.9 seconds
Started Jun 13 12:48:20 PM PDT 24
Finished Jun 13 12:48:23 PM PDT 24
Peak memory 196584 kb
Host smart-5c000c37-a23b-4d7a-87f8-35952b33a099
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463182696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3463182696
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.2210990355
Short name T399
Test name
Test status
Simulation time 103181052 ps
CPU time 1.45 seconds
Started Jun 13 12:48:19 PM PDT 24
Finished Jun 13 12:48:21 PM PDT 24
Peak memory 198020 kb
Host smart-b276b47f-f6f1-46c7-857f-028f6035d434
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210990355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.2210990355
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.2155021385
Short name T519
Test name
Test status
Simulation time 230964864 ps
CPU time 2.02 seconds
Started Jun 13 12:48:23 PM PDT 24
Finished Jun 13 12:48:25 PM PDT 24
Peak memory 198056 kb
Host smart-c45da405-d864-4343-9028-5443cdc7b6fe
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155021385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.2155021385
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.2610513930
Short name T236
Test name
Test status
Simulation time 440571227 ps
CPU time 2.58 seconds
Started Jun 13 12:48:20 PM PDT 24
Finished Jun 13 12:48:24 PM PDT 24
Peak memory 197172 kb
Host smart-1292bf1c-9b62-44da-9437-e23818970610
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610513930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.2610513930
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.3889603697
Short name T692
Test name
Test status
Simulation time 35933900 ps
CPU time 0.94 seconds
Started Jun 13 12:48:14 PM PDT 24
Finished Jun 13 12:48:16 PM PDT 24
Peak memory 195844 kb
Host smart-0072c530-47e0-4855-84ef-ac2f0b37fc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889603697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.3889603697
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.2629570031
Short name T612
Test name
Test status
Simulation time 52104948 ps
CPU time 1.02 seconds
Started Jun 13 12:48:14 PM PDT 24
Finished Jun 13 12:48:15 PM PDT 24
Peak memory 196020 kb
Host smart-ae95d0d5-dfdb-49cb-b134-ef0d2c024122
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629570031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.2629570031
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.2414576979
Short name T586
Test name
Test status
Simulation time 421789990 ps
CPU time 5.1 seconds
Started Jun 13 12:48:20 PM PDT 24
Finished Jun 13 12:48:27 PM PDT 24
Peak memory 197916 kb
Host smart-8df8d1eb-d3e5-42fc-8073-e749c1105adb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414576979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.2414576979
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.1157583472
Short name T249
Test name
Test status
Simulation time 55643394 ps
CPU time 0.88 seconds
Started Jun 13 12:48:20 PM PDT 24
Finished Jun 13 12:48:21 PM PDT 24
Peak memory 196856 kb
Host smart-474edb6b-9781-4a17-b283-40502eadb6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157583472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.1157583472
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.3943056284
Short name T504
Test name
Test status
Simulation time 190758205 ps
CPU time 1.43 seconds
Started Jun 13 12:48:21 PM PDT 24
Finished Jun 13 12:48:24 PM PDT 24
Peak memory 196672 kb
Host smart-e1d27720-cf31-4c4f-8781-9a00d89afba4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943056284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.3943056284
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.2575186718
Short name T221
Test name
Test status
Simulation time 19533084383 ps
CPU time 68.83 seconds
Started Jun 13 12:48:28 PM PDT 24
Finished Jun 13 12:49:38 PM PDT 24
Peak memory 198048 kb
Host smart-c5a6ce12-3c58-490b-a0cd-d9367304a5f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575186718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.2575186718
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.2714512441
Short name T60
Test name
Test status
Simulation time 87810757091 ps
CPU time 1903.15 seconds
Started Jun 13 12:48:20 PM PDT 24
Finished Jun 13 01:20:04 PM PDT 24
Peak memory 198112 kb
Host smart-0d0e6986-d640-4c09-849a-b826d7037040
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2714512441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.2714512441
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.1146870444
Short name T581
Test name
Test status
Simulation time 12202620 ps
CPU time 0.56 seconds
Started Jun 13 12:48:23 PM PDT 24
Finished Jun 13 12:48:25 PM PDT 24
Peak memory 192520 kb
Host smart-836f5a72-f8f1-4da4-85a6-e7a86c14e711
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146870444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.1146870444
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.3182974950
Short name T416
Test name
Test status
Simulation time 93640536 ps
CPU time 0.7 seconds
Started Jun 13 12:48:21 PM PDT 24
Finished Jun 13 12:48:23 PM PDT 24
Peak memory 194040 kb
Host smart-ec988478-f567-47fe-956e-bdd24f96ef85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182974950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.3182974950
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.3770832379
Short name T669
Test name
Test status
Simulation time 927792299 ps
CPU time 9.25 seconds
Started Jun 13 12:48:20 PM PDT 24
Finished Jun 13 12:48:31 PM PDT 24
Peak memory 196848 kb
Host smart-c7dcde88-4ee9-4c14-80a5-9b88fe97994b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770832379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.3770832379
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.1367234028
Short name T425
Test name
Test status
Simulation time 107622446 ps
CPU time 0.89 seconds
Started Jun 13 12:48:20 PM PDT 24
Finished Jun 13 12:48:23 PM PDT 24
Peak memory 196552 kb
Host smart-1ee78736-44b1-4c3a-b46f-09b2556c5fdf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367234028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.1367234028
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.1140000553
Short name T377
Test name
Test status
Simulation time 159065042 ps
CPU time 1.21 seconds
Started Jun 13 12:48:18 PM PDT 24
Finished Jun 13 12:48:20 PM PDT 24
Peak memory 196636 kb
Host smart-8f189a6c-ddb1-40df-b776-2ffb60c7ca33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140000553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.1140000553
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.2124761928
Short name T162
Test name
Test status
Simulation time 44011788 ps
CPU time 1.69 seconds
Started Jun 13 12:48:28 PM PDT 24
Finished Jun 13 12:48:30 PM PDT 24
Peak memory 196252 kb
Host smart-5337353c-e630-4e6c-910d-d5888ec9a4a5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124761928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.2124761928
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.214803217
Short name T613
Test name
Test status
Simulation time 589009337 ps
CPU time 2.13 seconds
Started Jun 13 12:48:19 PM PDT 24
Finished Jun 13 12:48:22 PM PDT 24
Peak memory 198008 kb
Host smart-3024898f-91b7-4d1e-bc13-253f0d574f5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214803217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger.
214803217
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.4122352825
Short name T184
Test name
Test status
Simulation time 21140861 ps
CPU time 0.85 seconds
Started Jun 13 12:48:21 PM PDT 24
Finished Jun 13 12:48:23 PM PDT 24
Peak memory 196320 kb
Host smart-cd8a16df-b59b-4d02-b240-26eee41dd269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122352825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.4122352825
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.794578355
Short name T208
Test name
Test status
Simulation time 160245045 ps
CPU time 0.76 seconds
Started Jun 13 12:48:19 PM PDT 24
Finished Jun 13 12:48:20 PM PDT 24
Peak memory 195264 kb
Host smart-492dca2e-5423-4538-a345-a006920cd9c3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794578355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullup
_pulldown.794578355
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.752325557
Short name T348
Test name
Test status
Simulation time 456677315 ps
CPU time 1.42 seconds
Started Jun 13 12:48:20 PM PDT 24
Finished Jun 13 12:48:22 PM PDT 24
Peak memory 197876 kb
Host smart-4fa9458d-665d-480b-b579-9123a8ececd1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752325557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ran
dom_long_reg_writes_reg_reads.752325557
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.32346062
Short name T18
Test name
Test status
Simulation time 98393798 ps
CPU time 1.45 seconds
Started Jun 13 12:48:20 PM PDT 24
Finished Jun 13 12:48:23 PM PDT 24
Peak memory 195416 kb
Host smart-c4db84df-73a1-4f03-a9a9-caf27639313a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32346062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.32346062
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.1327742210
Short name T338
Test name
Test status
Simulation time 67319964 ps
CPU time 1.17 seconds
Started Jun 13 12:48:26 PM PDT 24
Finished Jun 13 12:48:28 PM PDT 24
Peak memory 196172 kb
Host smart-bcacd480-532e-489f-a171-c97448146e45
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327742210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.1327742210
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.1372404844
Short name T616
Test name
Test status
Simulation time 10620024920 ps
CPU time 62.65 seconds
Started Jun 13 12:48:28 PM PDT 24
Finished Jun 13 12:49:31 PM PDT 24
Peak memory 198024 kb
Host smart-20c735a3-6c11-49b7-bcf8-397e91562ee8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372404844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.1372404844
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.4054886726
Short name T220
Test name
Test status
Simulation time 22733659 ps
CPU time 0.6 seconds
Started Jun 13 12:48:26 PM PDT 24
Finished Jun 13 12:48:28 PM PDT 24
Peak memory 194368 kb
Host smart-20b5bf56-cb9f-4ac9-aa6b-c276cec1f514
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054886726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.4054886726
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.406733872
Short name T207
Test name
Test status
Simulation time 52019675 ps
CPU time 0.71 seconds
Started Jun 13 12:48:26 PM PDT 24
Finished Jun 13 12:48:27 PM PDT 24
Peak memory 194024 kb
Host smart-6ccca628-204b-47b1-9eee-81ca299a706b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406733872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.406733872
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.296369761
Short name T302
Test name
Test status
Simulation time 483693274 ps
CPU time 22.4 seconds
Started Jun 13 12:48:27 PM PDT 24
Finished Jun 13 12:48:50 PM PDT 24
Peak memory 195484 kb
Host smart-18bbc252-b25d-4c52-b21e-e4b9bb4a03be
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296369761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stres
s.296369761
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.422892997
Short name T604
Test name
Test status
Simulation time 76047446 ps
CPU time 1.06 seconds
Started Jun 13 12:48:26 PM PDT 24
Finished Jun 13 12:48:28 PM PDT 24
Peak memory 197724 kb
Host smart-be3780e5-c781-4a55-9441-8855c4c8b8a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422892997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.422892997
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.1568737180
Short name T546
Test name
Test status
Simulation time 51541598 ps
CPU time 1.29 seconds
Started Jun 13 12:48:28 PM PDT 24
Finished Jun 13 12:48:30 PM PDT 24
Peak memory 196620 kb
Host smart-564a879b-dac4-435a-b882-0cd42cfdc135
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568737180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.1568737180
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.3863700448
Short name T241
Test name
Test status
Simulation time 182762073 ps
CPU time 3.54 seconds
Started Jun 13 12:48:24 PM PDT 24
Finished Jun 13 12:48:29 PM PDT 24
Peak memory 198056 kb
Host smart-a4c8c615-6126-491c-9716-0ce090ea0c9c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863700448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.3863700448
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.2487643922
Short name T531
Test name
Test status
Simulation time 543752991 ps
CPU time 3.6 seconds
Started Jun 13 12:48:26 PM PDT 24
Finished Jun 13 12:48:30 PM PDT 24
Peak memory 197052 kb
Host smart-c3719427-70f0-4f37-be7c-add221df9df2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487643922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.2487643922
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.3978074644
Short name T252
Test name
Test status
Simulation time 40555006 ps
CPU time 0.63 seconds
Started Jun 13 12:48:20 PM PDT 24
Finished Jun 13 12:48:23 PM PDT 24
Peak memory 194116 kb
Host smart-677c277d-d263-4bac-8e0a-b90c9e356a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978074644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.3978074644
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.1935299580
Short name T218
Test name
Test status
Simulation time 128138316 ps
CPU time 1.06 seconds
Started Jun 13 12:48:28 PM PDT 24
Finished Jun 13 12:48:30 PM PDT 24
Peak memory 196020 kb
Host smart-522ef166-19ad-4b05-ac48-0b5ef8cdb659
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935299580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.1935299580
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.3939310309
Short name T280
Test name
Test status
Simulation time 954934603 ps
CPU time 3.7 seconds
Started Jun 13 12:48:26 PM PDT 24
Finished Jun 13 12:48:30 PM PDT 24
Peak memory 197888 kb
Host smart-18b8e179-f80f-4789-9950-5c5d08fcadd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939310309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.3939310309
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.2440292806
Short name T333
Test name
Test status
Simulation time 32251884 ps
CPU time 0.91 seconds
Started Jun 13 12:48:19 PM PDT 24
Finished Jun 13 12:48:21 PM PDT 24
Peak memory 195120 kb
Host smart-c7780f26-d401-40b0-a4c1-02d7eb98cf63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440292806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.2440292806
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.378716586
Short name T112
Test name
Test status
Simulation time 87071595 ps
CPU time 1.13 seconds
Started Jun 13 12:48:22 PM PDT 24
Finished Jun 13 12:48:24 PM PDT 24
Peak memory 195640 kb
Host smart-22f33a3e-7481-4e12-a17f-dd8c25d515a2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378716586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.378716586
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.214540453
Short name T277
Test name
Test status
Simulation time 9803231634 ps
CPU time 148.54 seconds
Started Jun 13 12:48:26 PM PDT 24
Finished Jun 13 12:50:56 PM PDT 24
Peak memory 198140 kb
Host smart-22ae3627-0d5f-45ff-81e3-b925ae3d7905
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214540453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.g
pio_stress_all.214540453
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.14410825
Short name T30
Test name
Test status
Simulation time 1881377986796 ps
CPU time 2510.39 seconds
Started Jun 13 12:48:26 PM PDT 24
Finished Jun 13 01:30:18 PM PDT 24
Peak memory 206340 kb
Host smart-8d1070c3-8684-4676-b451-60d77a990e5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=14410825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.14410825
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.375483353
Short name T602
Test name
Test status
Simulation time 14045256 ps
CPU time 0.59 seconds
Started Jun 13 12:48:34 PM PDT 24
Finished Jun 13 12:48:35 PM PDT 24
Peak memory 193928 kb
Host smart-8d00253b-24a8-46be-8bbd-f5e2dcff203f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375483353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.375483353
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.1957302163
Short name T105
Test name
Test status
Simulation time 13460570 ps
CPU time 0.63 seconds
Started Jun 13 12:48:32 PM PDT 24
Finished Jun 13 12:48:33 PM PDT 24
Peak memory 194468 kb
Host smart-ddf5178c-87de-429f-94ad-2fac35ec1eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957302163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.1957302163
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.2955323544
Short name T538
Test name
Test status
Simulation time 729072016 ps
CPU time 16.49 seconds
Started Jun 13 12:48:35 PM PDT 24
Finished Jun 13 12:48:52 PM PDT 24
Peak memory 195464 kb
Host smart-9cebc9a6-368c-4cbb-8941-6091f169c59a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955323544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.2955323544
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.921645956
Short name T650
Test name
Test status
Simulation time 61573772 ps
CPU time 0.89 seconds
Started Jun 13 12:48:35 PM PDT 24
Finished Jun 13 12:48:36 PM PDT 24
Peak memory 196996 kb
Host smart-645dfda2-2e2c-4a73-a278-f3800c6da9d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921645956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.921645956
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.651928336
Short name T631
Test name
Test status
Simulation time 203507164 ps
CPU time 0.93 seconds
Started Jun 13 12:48:33 PM PDT 24
Finished Jun 13 12:48:35 PM PDT 24
Peak memory 196592 kb
Host smart-7ad5fd7d-82a3-4774-845c-58fb8a280449
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651928336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.651928336
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.337120907
Short name T253
Test name
Test status
Simulation time 139606565 ps
CPU time 2.92 seconds
Started Jun 13 12:48:32 PM PDT 24
Finished Jun 13 12:48:35 PM PDT 24
Peak memory 198108 kb
Host smart-5de8e453-139b-4139-ace5-c81a92bd6083
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337120907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.gpio_intr_with_filter_rand_intr_event.337120907
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.127451690
Short name T193
Test name
Test status
Simulation time 38258278 ps
CPU time 1.08 seconds
Started Jun 13 12:48:35 PM PDT 24
Finished Jun 13 12:48:36 PM PDT 24
Peak memory 195488 kb
Host smart-75645f1a-d150-4b24-aa14-7b60b2ecef80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127451690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger.
127451690
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.3752024262
Short name T137
Test name
Test status
Simulation time 42052402 ps
CPU time 1.07 seconds
Started Jun 13 12:48:28 PM PDT 24
Finished Jun 13 12:48:29 PM PDT 24
Peak memory 196000 kb
Host smart-d703b473-a971-4708-9698-1045142915f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752024262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.3752024262
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.2563234715
Short name T151
Test name
Test status
Simulation time 186611831 ps
CPU time 1 seconds
Started Jun 13 12:48:27 PM PDT 24
Finished Jun 13 12:48:28 PM PDT 24
Peak memory 196000 kb
Host smart-bb52fed7-3451-4334-a3c5-11eb4f751dd6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563234715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.2563234715
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.391805812
Short name T418
Test name
Test status
Simulation time 70303375 ps
CPU time 1.32 seconds
Started Jun 13 12:48:31 PM PDT 24
Finished Jun 13 12:48:33 PM PDT 24
Peak memory 198000 kb
Host smart-54d7e25a-99eb-4933-bbf6-ab54a83b17a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391805812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ran
dom_long_reg_writes_reg_reads.391805812
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.4101191714
Short name T598
Test name
Test status
Simulation time 44567157 ps
CPU time 1.32 seconds
Started Jun 13 12:48:26 PM PDT 24
Finished Jun 13 12:48:28 PM PDT 24
Peak memory 196528 kb
Host smart-ccba3412-913f-4477-8fb7-8c29be3d528e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101191714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.4101191714
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.3519887703
Short name T466
Test name
Test status
Simulation time 70012923 ps
CPU time 1.41 seconds
Started Jun 13 12:48:26 PM PDT 24
Finished Jun 13 12:48:28 PM PDT 24
Peak memory 196736 kb
Host smart-ef259e3f-ff6e-4d60-94d8-29285f5d624a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519887703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.3519887703
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.3095599860
Short name T556
Test name
Test status
Simulation time 28308052004 ps
CPU time 175.13 seconds
Started Jun 13 12:48:31 PM PDT 24
Finished Jun 13 12:51:27 PM PDT 24
Peak memory 198016 kb
Host smart-bb4d0dd1-5008-4fbf-b5e5-a7e2391c56ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095599860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.3095599860
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.1386208073
Short name T629
Test name
Test status
Simulation time 23691088 ps
CPU time 0.6 seconds
Started Jun 13 12:48:32 PM PDT 24
Finished Jun 13 12:48:33 PM PDT 24
Peak memory 194000 kb
Host smart-f61f475d-2bde-4ad2-b405-fc67a545b18e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386208073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.1386208073
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.580282946
Short name T380
Test name
Test status
Simulation time 94471646 ps
CPU time 0.89 seconds
Started Jun 13 12:48:33 PM PDT 24
Finished Jun 13 12:48:35 PM PDT 24
Peak memory 197124 kb
Host smart-dfabdb40-478f-452f-9697-892d791ff501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580282946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.580282946
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.2744075050
Short name T687
Test name
Test status
Simulation time 3376642666 ps
CPU time 14.88 seconds
Started Jun 13 12:48:36 PM PDT 24
Finished Jun 13 12:48:51 PM PDT 24
Peak memory 198072 kb
Host smart-f392afd3-bd09-4ed2-91fa-266371537eed
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744075050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.2744075050
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.3018911831
Short name T435
Test name
Test status
Simulation time 875235056 ps
CPU time 1.03 seconds
Started Jun 13 12:48:33 PM PDT 24
Finished Jun 13 12:48:35 PM PDT 24
Peak memory 197104 kb
Host smart-f0fdd5c0-7da7-40ad-97a5-5b588dc4ddd7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018911831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.3018911831
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.561850477
Short name T510
Test name
Test status
Simulation time 291025428 ps
CPU time 1.17 seconds
Started Jun 13 12:48:33 PM PDT 24
Finished Jun 13 12:48:35 PM PDT 24
Peak memory 195948 kb
Host smart-f4b46c6e-2961-4b26-afdb-efe2f4e03577
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561850477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.561850477
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.2600114855
Short name T191
Test name
Test status
Simulation time 95928097 ps
CPU time 2.05 seconds
Started Jun 13 12:48:33 PM PDT 24
Finished Jun 13 12:48:36 PM PDT 24
Peak memory 196456 kb
Host smart-c684d6d3-942e-48f5-acf6-2d702ae55822
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600114855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.2600114855
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.458772445
Short name T542
Test name
Test status
Simulation time 152859110 ps
CPU time 1.07 seconds
Started Jun 13 12:48:32 PM PDT 24
Finished Jun 13 12:48:34 PM PDT 24
Peak memory 195524 kb
Host smart-9c8db827-9c1b-4fea-afe9-465565dbc3d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458772445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger.
458772445
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.2385486528
Short name T291
Test name
Test status
Simulation time 36475646 ps
CPU time 0.86 seconds
Started Jun 13 12:48:36 PM PDT 24
Finished Jun 13 12:48:37 PM PDT 24
Peak memory 196424 kb
Host smart-714cc728-8351-480f-9b47-a196b4b01828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385486528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.2385486528
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.2133969972
Short name T202
Test name
Test status
Simulation time 15546460 ps
CPU time 0.66 seconds
Started Jun 13 12:48:31 PM PDT 24
Finished Jun 13 12:48:33 PM PDT 24
Peak memory 194912 kb
Host smart-c88bb220-c5a2-4751-aae2-a2b9351722e1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133969972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.2133969972
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.1900891828
Short name T639
Test name
Test status
Simulation time 901775508 ps
CPU time 5.07 seconds
Started Jun 13 12:48:33 PM PDT 24
Finished Jun 13 12:48:39 PM PDT 24
Peak memory 197888 kb
Host smart-a08fc63b-bee8-4628-ae35-19c2b2b342a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900891828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.1900891828
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.3439228596
Short name T422
Test name
Test status
Simulation time 175950832 ps
CPU time 1.13 seconds
Started Jun 13 12:48:34 PM PDT 24
Finished Jun 13 12:48:36 PM PDT 24
Peak memory 196368 kb
Host smart-feb4ec94-02ad-4133-8c07-b52c31462ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439228596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.3439228596
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.2867222216
Short name T133
Test name
Test status
Simulation time 271454003 ps
CPU time 1.27 seconds
Started Jun 13 12:48:32 PM PDT 24
Finished Jun 13 12:48:34 PM PDT 24
Peak memory 195548 kb
Host smart-41e8f36f-3793-497d-b981-feb0892818d8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867222216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.2867222216
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.4176423682
Short name T507
Test name
Test status
Simulation time 10228946365 ps
CPU time 313.34 seconds
Started Jun 13 12:48:33 PM PDT 24
Finished Jun 13 12:53:47 PM PDT 24
Peak memory 206348 kb
Host smart-492b043e-0cf0-457a-a66b-3ed4c02d2c9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4176423682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.4176423682
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.3720717278
Short name T156
Test name
Test status
Simulation time 11130097 ps
CPU time 0.56 seconds
Started Jun 13 12:45:53 PM PDT 24
Finished Jun 13 12:45:55 PM PDT 24
Peak memory 193736 kb
Host smart-6f0a6e1c-747c-42c9-ab6f-e9a0554eddb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720717278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.3720717278
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.593003499
Short name T557
Test name
Test status
Simulation time 70839487 ps
CPU time 0.84 seconds
Started Jun 13 12:45:58 PM PDT 24
Finished Jun 13 12:45:59 PM PDT 24
Peak memory 196204 kb
Host smart-fd11c786-a81a-4d34-aa51-f1f8f9d687fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593003499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.593003499
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.511517111
Short name T70
Test name
Test status
Simulation time 815125154 ps
CPU time 23.29 seconds
Started Jun 13 12:45:53 PM PDT 24
Finished Jun 13 12:46:17 PM PDT 24
Peak memory 197916 kb
Host smart-2fa0583b-b645-4c2f-b67c-83d314b5a29a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511517111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stress
.511517111
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.1856236499
Short name T638
Test name
Test status
Simulation time 221392918 ps
CPU time 0.75 seconds
Started Jun 13 12:45:56 PM PDT 24
Finished Jun 13 12:45:57 PM PDT 24
Peak memory 195720 kb
Host smart-74fd9cf3-d419-4821-b7b6-53de59f79c9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856236499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.1856236499
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.1840642088
Short name T693
Test name
Test status
Simulation time 249196133 ps
CPU time 1.24 seconds
Started Jun 13 12:45:53 PM PDT 24
Finished Jun 13 12:45:55 PM PDT 24
Peak memory 196908 kb
Host smart-2d075d36-50e3-49df-8cbb-7511bdbfe52e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840642088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.1840642088
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.3628294968
Short name T196
Test name
Test status
Simulation time 195238424 ps
CPU time 2.25 seconds
Started Jun 13 12:45:53 PM PDT 24
Finished Jun 13 12:45:56 PM PDT 24
Peak memory 198072 kb
Host smart-d7317262-84e5-4ec5-b893-cd7df510d0f3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628294968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.3628294968
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.3115943737
Short name T512
Test name
Test status
Simulation time 477674371 ps
CPU time 1.3 seconds
Started Jun 13 12:45:53 PM PDT 24
Finished Jun 13 12:45:55 PM PDT 24
Peak memory 196116 kb
Host smart-d6cf725f-86a9-46b4-af57-dc6bef7cfca2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115943737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
3115943737
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.3818650916
Short name T400
Test name
Test status
Simulation time 244228185 ps
CPU time 1.34 seconds
Started Jun 13 12:45:53 PM PDT 24
Finished Jun 13 12:45:55 PM PDT 24
Peak memory 196976 kb
Host smart-229cca69-5a67-42a9-90ba-81c636226b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818650916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.3818650916
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.133908478
Short name T434
Test name
Test status
Simulation time 30737955 ps
CPU time 1.19 seconds
Started Jun 13 12:45:56 PM PDT 24
Finished Jun 13 12:45:58 PM PDT 24
Peak memory 197064 kb
Host smart-a2cdba4b-dd7e-4723-b649-08fe280301fc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133908478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup_
pulldown.133908478
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.869785277
Short name T69
Test name
Test status
Simulation time 357509528 ps
CPU time 3.95 seconds
Started Jun 13 12:45:56 PM PDT 24
Finished Jun 13 12:46:00 PM PDT 24
Peak memory 197864 kb
Host smart-89ab2512-c051-48fc-9ea1-bb6689bfd9d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869785277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand
om_long_reg_writes_reg_reads.869785277
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.2400143829
Short name T47
Test name
Test status
Simulation time 64565053 ps
CPU time 0.78 seconds
Started Jun 13 12:45:55 PM PDT 24
Finished Jun 13 12:45:56 PM PDT 24
Peak memory 213572 kb
Host smart-f312e148-0dc7-4bcb-b575-ecd456cd8f05
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400143829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.2400143829
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.423533247
Short name T569
Test name
Test status
Simulation time 318404729 ps
CPU time 1.34 seconds
Started Jun 13 12:45:54 PM PDT 24
Finished Jun 13 12:45:56 PM PDT 24
Peak memory 197920 kb
Host smart-6f81011f-d1cf-409c-9759-cd2bf3b3bf68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423533247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.423533247
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.3827852395
Short name T303
Test name
Test status
Simulation time 36277165 ps
CPU time 0.86 seconds
Started Jun 13 12:45:52 PM PDT 24
Finished Jun 13 12:45:53 PM PDT 24
Peak memory 195948 kb
Host smart-5605f102-87b7-43de-9380-d05eef7b1a07
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827852395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.3827852395
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.1239476005
Short name T114
Test name
Test status
Simulation time 8165344050 ps
CPU time 50.9 seconds
Started Jun 13 12:45:53 PM PDT 24
Finished Jun 13 12:46:44 PM PDT 24
Peak memory 198000 kb
Host smart-19263c8e-25c3-477b-854e-ae9857b7697c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239476005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.1239476005
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.2046332768
Short name T678
Test name
Test status
Simulation time 33052266 ps
CPU time 0.59 seconds
Started Jun 13 12:48:41 PM PDT 24
Finished Jun 13 12:48:42 PM PDT 24
Peak memory 194432 kb
Host smart-cd967d95-9a6f-44c8-a89e-5d99f46d658f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046332768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.2046332768
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.465355523
Short name T576
Test name
Test status
Simulation time 100484973 ps
CPU time 0.89 seconds
Started Jun 13 12:48:41 PM PDT 24
Finished Jun 13 12:48:43 PM PDT 24
Peak memory 196028 kb
Host smart-63928c75-6e82-4182-9b72-22a629c2eabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465355523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.465355523
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.3297415558
Short name T233
Test name
Test status
Simulation time 3807803258 ps
CPU time 27.2 seconds
Started Jun 13 12:48:42 PM PDT 24
Finished Jun 13 12:49:10 PM PDT 24
Peak memory 196412 kb
Host smart-6559b815-1bff-4a82-a8aa-f393f52ae46d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297415558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.3297415558
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.1814763102
Short name T680
Test name
Test status
Simulation time 171083939 ps
CPU time 1.01 seconds
Started Jun 13 12:48:40 PM PDT 24
Finished Jun 13 12:48:42 PM PDT 24
Peak memory 197132 kb
Host smart-c6f68b70-67a6-477f-8969-39334e230067
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814763102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.1814763102
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.2756122293
Short name T649
Test name
Test status
Simulation time 81663777 ps
CPU time 0.75 seconds
Started Jun 13 12:48:39 PM PDT 24
Finished Jun 13 12:48:41 PM PDT 24
Peak memory 195260 kb
Host smart-aa129ec6-4d94-4cac-a1b3-3ef5ca067b9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756122293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.2756122293
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.4242979089
Short name T227
Test name
Test status
Simulation time 277729426 ps
CPU time 2.45 seconds
Started Jun 13 12:48:41 PM PDT 24
Finished Jun 13 12:48:44 PM PDT 24
Peak memory 198004 kb
Host smart-8b386ecc-3e08-4568-a241-6a7be3a599e1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242979089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.4242979089
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.37483200
Short name T700
Test name
Test status
Simulation time 410541931 ps
CPU time 2.76 seconds
Started Jun 13 12:48:42 PM PDT 24
Finished Jun 13 12:48:46 PM PDT 24
Peak memory 195776 kb
Host smart-f5415a1a-fdf3-45f0-8ec5-9dc2946c59e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37483200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger.37483200
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.3681557437
Short name T312
Test name
Test status
Simulation time 219599135 ps
CPU time 0.89 seconds
Started Jun 13 12:48:42 PM PDT 24
Finished Jun 13 12:48:43 PM PDT 24
Peak memory 195392 kb
Host smart-4f632074-3d32-4879-9120-53feebd46ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681557437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.3681557437
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.2461476240
Short name T487
Test name
Test status
Simulation time 73739285 ps
CPU time 1.08 seconds
Started Jun 13 12:48:41 PM PDT 24
Finished Jun 13 12:48:43 PM PDT 24
Peak memory 195968 kb
Host smart-82af00e2-434a-4660-998c-acb8d7a07301
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461476240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.2461476240
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.3871998659
Short name T559
Test name
Test status
Simulation time 6606914766 ps
CPU time 4.88 seconds
Started Jun 13 12:48:43 PM PDT 24
Finished Jun 13 12:48:49 PM PDT 24
Peak memory 198040 kb
Host smart-3b008610-4333-4b3f-b446-73e61d90ae31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871998659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.3871998659
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.29992806
Short name T257
Test name
Test status
Simulation time 53614349 ps
CPU time 0.97 seconds
Started Jun 13 12:48:39 PM PDT 24
Finished Jun 13 12:48:40 PM PDT 24
Peak memory 196436 kb
Host smart-9bc339e9-e7c1-4eb6-af43-ad4e93bf6f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29992806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.29992806
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.2284408898
Short name T662
Test name
Test status
Simulation time 42733772 ps
CPU time 1.09 seconds
Started Jun 13 12:48:40 PM PDT 24
Finished Jun 13 12:48:41 PM PDT 24
Peak memory 195580 kb
Host smart-855b8ebb-3064-4ba5-b98e-c80d683537ce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284408898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.2284408898
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.375492010
Short name T491
Test name
Test status
Simulation time 61292965021 ps
CPU time 210.2 seconds
Started Jun 13 12:48:44 PM PDT 24
Finished Jun 13 12:52:15 PM PDT 24
Peak memory 198076 kb
Host smart-e2ca26a2-8569-4d8f-b6d5-7ea96965fab3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375492010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.g
pio_stress_all.375492010
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.981554
Short name T567
Test name
Test status
Simulation time 32037757 ps
CPU time 0.57 seconds
Started Jun 13 12:48:46 PM PDT 24
Finished Jun 13 12:48:47 PM PDT 24
Peak memory 194648 kb
Host smart-17b1024c-9fe8-4f9c-aada-8a9f6da8dddd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.981554
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.107742708
Short name T683
Test name
Test status
Simulation time 170714542 ps
CPU time 0.64 seconds
Started Jun 13 12:48:42 PM PDT 24
Finished Jun 13 12:48:43 PM PDT 24
Peak memory 194536 kb
Host smart-1332a82a-76a8-4ccb-8499-1bb5ddf41d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107742708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.107742708
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.2628074141
Short name T332
Test name
Test status
Simulation time 606305652 ps
CPU time 8.37 seconds
Started Jun 13 12:48:44 PM PDT 24
Finished Jun 13 12:48:53 PM PDT 24
Peak memory 195492 kb
Host smart-2a8b3f2c-bca8-463e-af22-2f845c2a966e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628074141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.2628074141
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.2671305460
Short name T109
Test name
Test status
Simulation time 70932020 ps
CPU time 1.05 seconds
Started Jun 13 12:48:44 PM PDT 24
Finished Jun 13 12:48:46 PM PDT 24
Peak memory 196496 kb
Host smart-e3bc75b1-c0dc-4855-b23f-1ef9e8cc860b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671305460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.2671305460
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.657751953
Short name T297
Test name
Test status
Simulation time 93884323 ps
CPU time 1.38 seconds
Started Jun 13 12:48:43 PM PDT 24
Finished Jun 13 12:48:45 PM PDT 24
Peak memory 197988 kb
Host smart-357da085-fbc5-40d7-841c-b1e2d6c288cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657751953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.657751953
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.909941125
Short name T101
Test name
Test status
Simulation time 85713862 ps
CPU time 3.5 seconds
Started Jun 13 12:48:41 PM PDT 24
Finished Jun 13 12:48:45 PM PDT 24
Peak memory 198084 kb
Host smart-7bc0c693-bc57-43b2-9dba-33c0a13be875
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909941125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.gpio_intr_with_filter_rand_intr_event.909941125
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.1929628593
Short name T652
Test name
Test status
Simulation time 90565754 ps
CPU time 2.69 seconds
Started Jun 13 12:48:43 PM PDT 24
Finished Jun 13 12:48:46 PM PDT 24
Peak memory 195720 kb
Host smart-b191a5c0-b1dc-4ea3-9ca1-a528bfed5ac7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929628593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.1929628593
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.1715134767
Short name T561
Test name
Test status
Simulation time 49909908 ps
CPU time 0.76 seconds
Started Jun 13 12:48:41 PM PDT 24
Finished Jun 13 12:48:42 PM PDT 24
Peak memory 195244 kb
Host smart-7be18c51-e4db-4e6f-9657-bd484071ac97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715134767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.1715134767
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.2624773451
Short name T626
Test name
Test status
Simulation time 29736742 ps
CPU time 1.12 seconds
Started Jun 13 12:48:41 PM PDT 24
Finished Jun 13 12:48:43 PM PDT 24
Peak memory 195968 kb
Host smart-be8e9248-b2f3-4976-8a12-60237c04362a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624773451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.2624773451
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.3917687270
Short name T354
Test name
Test status
Simulation time 1496673268 ps
CPU time 5.2 seconds
Started Jun 13 12:48:42 PM PDT 24
Finished Jun 13 12:48:48 PM PDT 24
Peak memory 197984 kb
Host smart-48e8acc9-1890-4f3b-817c-0236a16456f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917687270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.3917687270
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.2988338743
Short name T238
Test name
Test status
Simulation time 124196240 ps
CPU time 1.44 seconds
Started Jun 13 12:48:40 PM PDT 24
Finished Jun 13 12:48:42 PM PDT 24
Peak memory 197964 kb
Host smart-8dfc87e2-e9fc-463e-b56e-daa3f1ef2bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988338743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.2988338743
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.2699850806
Short name T695
Test name
Test status
Simulation time 243257646 ps
CPU time 1.28 seconds
Started Jun 13 12:48:41 PM PDT 24
Finished Jun 13 12:48:43 PM PDT 24
Peak memory 195748 kb
Host smart-eade891e-8d66-4e44-87f5-2d6559f990ae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699850806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.2699850806
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.3419120401
Short name T513
Test name
Test status
Simulation time 31895100839 ps
CPU time 202.7 seconds
Started Jun 13 12:48:45 PM PDT 24
Finished Jun 13 12:52:09 PM PDT 24
Peak memory 198036 kb
Host smart-23b826d6-ccc4-46e1-bba8-807e4c938769
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419120401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.3419120401
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.2295620029
Short name T566
Test name
Test status
Simulation time 172091514349 ps
CPU time 1163.23 seconds
Started Jun 13 12:48:45 PM PDT 24
Finished Jun 13 01:08:09 PM PDT 24
Peak memory 198132 kb
Host smart-612fac2b-9f77-4e52-9b83-0f24e15ed044
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2295620029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.2295620029
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.830166804
Short name T314
Test name
Test status
Simulation time 52663278 ps
CPU time 0.6 seconds
Started Jun 13 01:18:44 PM PDT 24
Finished Jun 13 01:18:45 PM PDT 24
Peak memory 194016 kb
Host smart-190ba31d-f5b9-46b4-a6ef-0ad8d62ab277
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830166804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.830166804
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.1536586650
Short name T492
Test name
Test status
Simulation time 79732576 ps
CPU time 0.84 seconds
Started Jun 13 12:48:45 PM PDT 24
Finished Jun 13 12:48:47 PM PDT 24
Peak memory 195332 kb
Host smart-58bed347-b51f-4412-9f33-7192928b12ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536586650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.1536586650
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.3636199241
Short name T26
Test name
Test status
Simulation time 288656472 ps
CPU time 14.74 seconds
Started Jun 13 12:48:47 PM PDT 24
Finished Jun 13 12:49:02 PM PDT 24
Peak memory 196836 kb
Host smart-e7feab5c-59fc-4bec-8253-e7ec939ff818
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636199241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.3636199241
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.2446331522
Short name T341
Test name
Test status
Simulation time 23938452 ps
CPU time 0.64 seconds
Started Jun 13 01:42:12 PM PDT 24
Finished Jun 13 01:42:14 PM PDT 24
Peak memory 195044 kb
Host smart-43665331-d2bd-4f14-9bc6-02779b54e0ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446331522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.2446331522
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.246039692
Short name T632
Test name
Test status
Simulation time 41411603 ps
CPU time 1.2 seconds
Started Jun 13 12:48:46 PM PDT 24
Finished Jun 13 12:48:48 PM PDT 24
Peak memory 196828 kb
Host smart-f4fa3330-66d7-4555-a260-9fc50973d652
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246039692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.246039692
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.337489810
Short name T316
Test name
Test status
Simulation time 416457374 ps
CPU time 4.01 seconds
Started Jun 13 12:48:45 PM PDT 24
Finished Jun 13 12:48:49 PM PDT 24
Peak memory 197992 kb
Host smart-02aa28af-aec2-4d63-a114-512fd5464bee
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337489810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.gpio_intr_with_filter_rand_intr_event.337489810
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.1954781611
Short name T685
Test name
Test status
Simulation time 124854326 ps
CPU time 3.55 seconds
Started Jun 13 12:48:45 PM PDT 24
Finished Jun 13 12:48:50 PM PDT 24
Peak memory 196916 kb
Host smart-5c7d33ae-0226-42ec-a4b6-2b7f42e5d625
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954781611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.1954781611
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.4147040125
Short name T630
Test name
Test status
Simulation time 22629426 ps
CPU time 0.8 seconds
Started Jun 13 12:48:46 PM PDT 24
Finished Jun 13 12:48:47 PM PDT 24
Peak memory 197088 kb
Host smart-309a9a4a-02d7-4618-912d-5cc3b54bece5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147040125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.4147040125
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.4144654877
Short name T376
Test name
Test status
Simulation time 34373810 ps
CPU time 1.32 seconds
Started Jun 13 12:48:46 PM PDT 24
Finished Jun 13 12:48:48 PM PDT 24
Peak memory 197048 kb
Host smart-735ebd0b-0df0-4911-85eb-cb3d65dc42ec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144654877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.4144654877
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.221651888
Short name T635
Test name
Test status
Simulation time 210477112 ps
CPU time 2.1 seconds
Started Jun 13 12:48:45 PM PDT 24
Finished Jun 13 12:48:47 PM PDT 24
Peak memory 197804 kb
Host smart-a8f72a42-4e20-4e50-84db-a5200189fefb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221651888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ran
dom_long_reg_writes_reg_reads.221651888
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.3750769555
Short name T251
Test name
Test status
Simulation time 174282729 ps
CPU time 1.29 seconds
Started Jun 13 12:48:45 PM PDT 24
Finished Jun 13 12:48:47 PM PDT 24
Peak memory 196608 kb
Host smart-3eabe3fb-f069-429e-8f52-81d518ff43d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750769555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.3750769555
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.456688522
Short name T605
Test name
Test status
Simulation time 607689859 ps
CPU time 1.34 seconds
Started Jun 13 12:48:46 PM PDT 24
Finished Jun 13 12:48:48 PM PDT 24
Peak memory 196404 kb
Host smart-96970a92-50e3-438f-b1d9-0ed93a495cba
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456688522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.456688522
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.1831308447
Short name T368
Test name
Test status
Simulation time 41313431241 ps
CPU time 151.41 seconds
Started Jun 13 02:02:33 PM PDT 24
Finished Jun 13 02:05:06 PM PDT 24
Peak memory 191976 kb
Host smart-9d7caada-c750-4884-ac33-0e27565b2633
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831308447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.1831308447
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.4147193438
Short name T503
Test name
Test status
Simulation time 453429363518 ps
CPU time 2076.3 seconds
Started Jun 13 01:24:11 PM PDT 24
Finished Jun 13 01:58:48 PM PDT 24
Peak memory 198200 kb
Host smart-9123db8a-e795-4e01-8e05-3129af14ecf7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4147193438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.4147193438
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.2931216164
Short name T471
Test name
Test status
Simulation time 10778691 ps
CPU time 0.59 seconds
Started Jun 13 01:54:33 PM PDT 24
Finished Jun 13 01:54:40 PM PDT 24
Peak memory 193828 kb
Host smart-fda5edcd-816f-4c48-bd77-deeb49b3a694
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931216164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.2931216164
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.4169334149
Short name T701
Test name
Test status
Simulation time 25974729 ps
CPU time 0.8 seconds
Started Jun 13 01:38:56 PM PDT 24
Finished Jun 13 01:38:58 PM PDT 24
Peak memory 195172 kb
Host smart-c55dc81b-fe69-49c9-ac21-77248554ad9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169334149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.4169334149
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.3919796365
Short name T408
Test name
Test status
Simulation time 416680735 ps
CPU time 14.68 seconds
Started Jun 13 12:54:59 PM PDT 24
Finished Jun 13 12:55:15 PM PDT 24
Peak memory 196728 kb
Host smart-c19eaa48-8155-4f7e-ae3f-ace0b3aae889
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919796365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.3919796365
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.3217444668
Short name T449
Test name
Test status
Simulation time 306657425 ps
CPU time 1.08 seconds
Started Jun 13 12:48:45 PM PDT 24
Finished Jun 13 12:48:46 PM PDT 24
Peak memory 196548 kb
Host smart-7a6d3380-ca8c-4fe2-9cb2-3df55e459056
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217444668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.3217444668
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.3542093310
Short name T12
Test name
Test status
Simulation time 40624266 ps
CPU time 1.15 seconds
Started Jun 13 01:18:37 PM PDT 24
Finished Jun 13 01:18:38 PM PDT 24
Peak memory 196148 kb
Host smart-c7efc162-675a-4df7-9c05-015851cffbbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542093310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.3542093310
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.571003564
Short name T427
Test name
Test status
Simulation time 262300729 ps
CPU time 2.76 seconds
Started Jun 13 12:55:27 PM PDT 24
Finished Jun 13 12:55:30 PM PDT 24
Peak memory 197912 kb
Host smart-7ad17fd5-a728-4256-ba19-b43b343f6390
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571003564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.gpio_intr_with_filter_rand_intr_event.571003564
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.4249571565
Short name T565
Test name
Test status
Simulation time 640451650 ps
CPU time 3.41 seconds
Started Jun 13 01:41:34 PM PDT 24
Finished Jun 13 01:41:39 PM PDT 24
Peak memory 195828 kb
Host smart-c94f9188-8ffb-4473-a02c-e87dc6aadf92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249571565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.4249571565
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.2402026327
Short name T361
Test name
Test status
Simulation time 22070467 ps
CPU time 0.68 seconds
Started Jun 13 01:30:38 PM PDT 24
Finished Jun 13 01:30:39 PM PDT 24
Peak memory 194264 kb
Host smart-1fa28c30-648b-4020-a4f9-8eec71fcacb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402026327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.2402026327
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.3093135364
Short name T355
Test name
Test status
Simulation time 141626910 ps
CPU time 0.94 seconds
Started Jun 13 02:15:47 PM PDT 24
Finished Jun 13 02:15:49 PM PDT 24
Peak memory 196600 kb
Host smart-fd0d7bd1-0964-4667-affe-a50bb5037903
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093135364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.3093135364
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.2945951403
Short name T643
Test name
Test status
Simulation time 176723033 ps
CPU time 4.11 seconds
Started Jun 13 01:26:21 PM PDT 24
Finished Jun 13 01:26:26 PM PDT 24
Peak memory 197988 kb
Host smart-b95692fa-c980-42a2-9d6c-0064d4e023b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945951403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.2945951403
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.1296089040
Short name T123
Test name
Test status
Simulation time 79715606 ps
CPU time 1.14 seconds
Started Jun 13 02:35:29 PM PDT 24
Finished Jun 13 02:35:32 PM PDT 24
Peak memory 196248 kb
Host smart-f21e30f0-cca5-49ff-bf9f-d324642cb016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296089040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.1296089040
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.630882036
Short name T222
Test name
Test status
Simulation time 392139410 ps
CPU time 1.05 seconds
Started Jun 13 01:07:50 PM PDT 24
Finished Jun 13 01:07:51 PM PDT 24
Peak memory 195828 kb
Host smart-3025a431-4a5d-4359-82ff-75a25d21cbc0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630882036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.630882036
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.3352234409
Short name T452
Test name
Test status
Simulation time 13304371679 ps
CPU time 100.2 seconds
Started Jun 13 02:14:48 PM PDT 24
Finished Jun 13 02:16:29 PM PDT 24
Peak memory 198160 kb
Host smart-bd1ee986-d628-4106-9e51-9eab7d813a4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352234409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.3352234409
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.4294473794
Short name T45
Test name
Test status
Simulation time 48800411 ps
CPU time 0.59 seconds
Started Jun 13 01:31:36 PM PDT 24
Finished Jun 13 01:31:38 PM PDT 24
Peak memory 194004 kb
Host smart-9eb941a0-a26a-4389-8c34-952874db2154
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294473794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.4294473794
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.1786701620
Short name T362
Test name
Test status
Simulation time 174005779 ps
CPU time 1.02 seconds
Started Jun 13 01:50:09 PM PDT 24
Finished Jun 13 01:50:13 PM PDT 24
Peak memory 196568 kb
Host smart-80fa6d68-63c4-48d8-9cc0-fc57045e9d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786701620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.1786701620
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.3851111505
Short name T259
Test name
Test status
Simulation time 621393208 ps
CPU time 21.7 seconds
Started Jun 13 01:57:18 PM PDT 24
Finished Jun 13 01:57:42 PM PDT 24
Peak memory 196760 kb
Host smart-1f80a6de-574e-40e7-a46e-454d4640b0cd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851111505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.3851111505
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.3937371615
Short name T235
Test name
Test status
Simulation time 49682600 ps
CPU time 0.81 seconds
Started Jun 13 01:44:02 PM PDT 24
Finished Jun 13 01:44:04 PM PDT 24
Peak memory 195680 kb
Host smart-c37ae8cb-b070-4b5b-a660-b39419222b2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937371615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.3937371615
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.2700505313
Short name T301
Test name
Test status
Simulation time 355402626 ps
CPU time 1.23 seconds
Started Jun 13 01:39:07 PM PDT 24
Finished Jun 13 01:39:09 PM PDT 24
Peak memory 197264 kb
Host smart-03671d8a-55bb-413b-8c01-163bd89210d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700505313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.2700505313
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.3364916483
Short name T344
Test name
Test status
Simulation time 321926331 ps
CPU time 3.68 seconds
Started Jun 13 02:03:06 PM PDT 24
Finished Jun 13 02:03:11 PM PDT 24
Peak memory 198032 kb
Host smart-e8501797-d034-4fdb-9fe6-2542a1ff98be
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364916483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.3364916483
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.2787312705
Short name T383
Test name
Test status
Simulation time 199937578 ps
CPU time 2.73 seconds
Started Jun 13 12:48:45 PM PDT 24
Finished Jun 13 12:48:48 PM PDT 24
Peak memory 197084 kb
Host smart-f03d7af0-e50b-49a3-b138-d03a579b65b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787312705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.2787312705
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.2678396964
Short name T562
Test name
Test status
Simulation time 29044086 ps
CPU time 1.03 seconds
Started Jun 13 01:44:53 PM PDT 24
Finished Jun 13 01:44:54 PM PDT 24
Peak memory 196064 kb
Host smart-498c8ffc-7711-4634-aaa4-93a11eab13fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678396964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.2678396964
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.3052626820
Short name T108
Test name
Test status
Simulation time 32372753 ps
CPU time 0.85 seconds
Started Jun 13 02:16:21 PM PDT 24
Finished Jun 13 02:16:25 PM PDT 24
Peak memory 195492 kb
Host smart-9fb5c6ee-7cde-46f7-bac6-b39e5bd977c7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052626820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.3052626820
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.2614673582
Short name T245
Test name
Test status
Simulation time 35606514 ps
CPU time 1.83 seconds
Started Jun 13 12:48:51 PM PDT 24
Finished Jun 13 12:48:53 PM PDT 24
Peak memory 197928 kb
Host smart-c3785528-94d8-493a-890d-06179f84fd26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614673582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.2614673582
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.1125374508
Short name T372
Test name
Test status
Simulation time 366675303 ps
CPU time 1.17 seconds
Started Jun 13 02:06:32 PM PDT 24
Finished Jun 13 02:06:34 PM PDT 24
Peak memory 195592 kb
Host smart-61ba02a9-0c3b-4923-bb09-770c697973e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125374508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.1125374508
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.3274431168
Short name T119
Test name
Test status
Simulation time 80882313 ps
CPU time 1.24 seconds
Started Jun 13 01:49:12 PM PDT 24
Finished Jun 13 01:49:14 PM PDT 24
Peak memory 195516 kb
Host smart-4492634c-9a14-4cd4-8640-12aadf3f20c0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274431168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.3274431168
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.1105350122
Short name T590
Test name
Test status
Simulation time 7507903333 ps
CPU time 81.77 seconds
Started Jun 13 01:32:05 PM PDT 24
Finished Jun 13 01:33:28 PM PDT 24
Peak memory 198180 kb
Host smart-f7038848-f83d-414d-881d-ae540fd29fd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105350122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.1105350122
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.2775031208
Short name T59
Test name
Test status
Simulation time 102395555966 ps
CPU time 365.65 seconds
Started Jun 13 12:48:52 PM PDT 24
Finished Jun 13 12:54:58 PM PDT 24
Peak memory 206304 kb
Host smart-0ba84c5d-115e-42be-a18d-8ccb349f2476
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2775031208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.2775031208
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.2090879609
Short name T315
Test name
Test status
Simulation time 15327457 ps
CPU time 0.59 seconds
Started Jun 13 12:48:53 PM PDT 24
Finished Jun 13 12:48:54 PM PDT 24
Peak memory 193744 kb
Host smart-46031d26-d68e-436e-b2dc-4b3167415aa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090879609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.2090879609
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.752418468
Short name T287
Test name
Test status
Simulation time 48005428 ps
CPU time 0.64 seconds
Started Jun 13 01:16:44 PM PDT 24
Finished Jun 13 01:16:46 PM PDT 24
Peak memory 193988 kb
Host smart-c6b698f3-e850-4207-8851-fde7eb563c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752418468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.752418468
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.536609341
Short name T323
Test name
Test status
Simulation time 4826870749 ps
CPU time 22.46 seconds
Started Jun 13 02:33:11 PM PDT 24
Finished Jun 13 02:33:35 PM PDT 24
Peak memory 196928 kb
Host smart-08614546-7c1f-4d39-a411-1bad02cc320c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536609341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stres
s.536609341
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.3624135104
Short name T117
Test name
Test status
Simulation time 107897955 ps
CPU time 0.73 seconds
Started Jun 13 01:25:43 PM PDT 24
Finished Jun 13 01:25:45 PM PDT 24
Peak memory 194640 kb
Host smart-67c378f2-8178-4762-bdd7-aed7727876c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624135104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.3624135104
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.514512120
Short name T17
Test name
Test status
Simulation time 77807853 ps
CPU time 1.14 seconds
Started Jun 13 02:00:39 PM PDT 24
Finished Jun 13 02:00:42 PM PDT 24
Peak memory 196184 kb
Host smart-1c0ceef3-4d68-4405-8203-a7c4bca390d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514512120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.514512120
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.533624248
Short name T203
Test name
Test status
Simulation time 137886238 ps
CPU time 1.79 seconds
Started Jun 13 01:24:05 PM PDT 24
Finished Jun 13 01:24:07 PM PDT 24
Peak memory 197276 kb
Host smart-ca07c383-f3a3-4089-be6f-ebe8a837a12e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533624248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.gpio_intr_with_filter_rand_intr_event.533624248
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.1754196897
Short name T483
Test name
Test status
Simulation time 72656446 ps
CPU time 1.86 seconds
Started Jun 13 01:31:14 PM PDT 24
Finished Jun 13 01:31:17 PM PDT 24
Peak memory 196192 kb
Host smart-6e27cc11-5fbb-49b0-aa83-5dbabc852a7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754196897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.1754196897
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.158827220
Short name T182
Test name
Test status
Simulation time 90841768 ps
CPU time 1.14 seconds
Started Jun 13 01:28:50 PM PDT 24
Finished Jun 13 01:28:51 PM PDT 24
Peak memory 196724 kb
Host smart-fd46b4b6-aa25-42a9-8a2a-6e9085231a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158827220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.158827220
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.4162251357
Short name T353
Test name
Test status
Simulation time 40678629 ps
CPU time 0.95 seconds
Started Jun 13 12:48:52 PM PDT 24
Finished Jun 13 12:48:53 PM PDT 24
Peak memory 196496 kb
Host smart-daa1faf5-120c-46fa-9abe-ebe729014cd5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162251357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.4162251357
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.3076151183
Short name T20
Test name
Test status
Simulation time 387076847 ps
CPU time 5.55 seconds
Started Jun 13 01:03:39 PM PDT 24
Finished Jun 13 01:03:45 PM PDT 24
Peak memory 197896 kb
Host smart-8dd5ca28-6feb-4cc9-956e-11953fad2ee6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076151183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.3076151183
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.92843422
Short name T597
Test name
Test status
Simulation time 131092737 ps
CPU time 1.22 seconds
Started Jun 13 01:06:33 PM PDT 24
Finished Jun 13 01:06:36 PM PDT 24
Peak memory 195620 kb
Host smart-697c0b92-a1b3-410b-b0fe-e4b7d26bfe2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92843422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.92843422
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.899491854
Short name T25
Test name
Test status
Simulation time 100911818 ps
CPU time 0.9 seconds
Started Jun 13 12:54:35 PM PDT 24
Finished Jun 13 12:54:37 PM PDT 24
Peak memory 195236 kb
Host smart-71cb748d-31ec-44dc-9341-74c7e81621c3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899491854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.899491854
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.896518836
Short name T127
Test name
Test status
Simulation time 5091769246 ps
CPU time 151.97 seconds
Started Jun 13 01:37:47 PM PDT 24
Finished Jun 13 01:40:20 PM PDT 24
Peak memory 198160 kb
Host smart-eb447df3-b985-43d5-b481-751ee36488d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896518836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.g
pio_stress_all.896518836
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.2247950065
Short name T499
Test name
Test status
Simulation time 77713718 ps
CPU time 0.59 seconds
Started Jun 13 01:23:27 PM PDT 24
Finished Jun 13 01:23:28 PM PDT 24
Peak memory 194772 kb
Host smart-3e8a2235-3a14-4e4d-8e68-3c346b8a36e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247950065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.2247950065
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.2877006917
Short name T691
Test name
Test status
Simulation time 28777849 ps
CPU time 0.8 seconds
Started Jun 13 02:23:08 PM PDT 24
Finished Jun 13 02:23:10 PM PDT 24
Peak memory 195332 kb
Host smart-93e1fcc5-5475-4a24-8538-3ebedc196899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877006917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.2877006917
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.282686163
Short name T694
Test name
Test status
Simulation time 3504070736 ps
CPU time 24.55 seconds
Started Jun 13 12:48:51 PM PDT 24
Finished Jun 13 12:49:16 PM PDT 24
Peak memory 196948 kb
Host smart-e718e93c-256a-42b9-afb4-9dd48172144a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282686163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stres
s.282686163
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.1442800959
Short name T486
Test name
Test status
Simulation time 90833950 ps
CPU time 1.15 seconds
Started Jun 13 12:55:34 PM PDT 24
Finished Jun 13 12:55:36 PM PDT 24
Peak memory 196580 kb
Host smart-46beee42-f0c9-4988-896f-f0e8f1583da6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442800959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.1442800959
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.158344553
Short name T432
Test name
Test status
Simulation time 35862844 ps
CPU time 0.96 seconds
Started Jun 13 01:20:56 PM PDT 24
Finished Jun 13 01:20:57 PM PDT 24
Peak memory 196012 kb
Host smart-acb9e831-806b-402e-b3f3-26f2e34a275d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158344553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.158344553
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.1685712545
Short name T441
Test name
Test status
Simulation time 119090490 ps
CPU time 3.47 seconds
Started Jun 13 01:55:55 PM PDT 24
Finished Jun 13 01:56:01 PM PDT 24
Peak memory 198080 kb
Host smart-8fc0decf-e98c-4fd6-a64d-5c862a9256f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685712545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.1685712545
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.36851365
Short name T710
Test name
Test status
Simulation time 31755622 ps
CPU time 1.23 seconds
Started Jun 13 02:10:02 PM PDT 24
Finished Jun 13 02:10:04 PM PDT 24
Peak memory 195900 kb
Host smart-ae671a57-5af8-48de-873f-ad86d303b1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36851365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.36851365
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.1206765424
Short name T339
Test name
Test status
Simulation time 69024669 ps
CPU time 0.88 seconds
Started Jun 13 12:48:52 PM PDT 24
Finished Jun 13 12:48:53 PM PDT 24
Peak memory 195788 kb
Host smart-62170422-bc5e-43ec-bb8c-95f89fbb532d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206765424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.1206765424
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.2052343520
Short name T67
Test name
Test status
Simulation time 744967501 ps
CPU time 5.02 seconds
Started Jun 13 01:34:15 PM PDT 24
Finished Jun 13 01:34:21 PM PDT 24
Peak memory 197980 kb
Host smart-722954a0-bbf5-4f81-87d8-88d8eb4cb94b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052343520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.2052343520
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.2819402701
Short name T215
Test name
Test status
Simulation time 84306408 ps
CPU time 1.34 seconds
Started Jun 13 12:48:53 PM PDT 24
Finished Jun 13 12:48:55 PM PDT 24
Peak memory 196824 kb
Host smart-a16f766f-b617-429e-b63c-e8316ccbf7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819402701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.2819402701
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.2323541427
Short name T384
Test name
Test status
Simulation time 238158936 ps
CPU time 1.36 seconds
Started Jun 13 01:45:02 PM PDT 24
Finished Jun 13 01:45:04 PM PDT 24
Peak memory 198240 kb
Host smart-a8dae969-7fc8-4e11-aea0-6bf2805bf75b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323541427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.2323541427
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.3495316592
Short name T489
Test name
Test status
Simulation time 16782238444 ps
CPU time 201 seconds
Started Jun 13 01:41:11 PM PDT 24
Finished Jun 13 01:44:33 PM PDT 24
Peak memory 198144 kb
Host smart-259f6d1d-b8c7-4747-a27b-8141b15ee1bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495316592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.3495316592
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.3511961345
Short name T57
Test name
Test status
Simulation time 527514082985 ps
CPU time 1156.74 seconds
Started Jun 13 01:21:39 PM PDT 24
Finished Jun 13 01:40:57 PM PDT 24
Peak memory 198180 kb
Host smart-5867f160-ca24-4186-8a40-fd31dc9548e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3511961345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.3511961345
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.2215720580
Short name T571
Test name
Test status
Simulation time 11256493 ps
CPU time 0.55 seconds
Started Jun 13 01:26:48 PM PDT 24
Finished Jun 13 01:26:50 PM PDT 24
Peak memory 192700 kb
Host smart-0be9e431-c731-4023-8842-84771f2f15ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215720580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.2215720580
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.996417800
Short name T481
Test name
Test status
Simulation time 44231957 ps
CPU time 0.68 seconds
Started Jun 13 12:56:27 PM PDT 24
Finished Jun 13 12:56:29 PM PDT 24
Peak memory 194092 kb
Host smart-2c172c8e-1e43-493f-85a4-debfe97a72f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996417800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.996417800
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.246366320
Short name T157
Test name
Test status
Simulation time 303688109 ps
CPU time 15.65 seconds
Started Jun 13 01:34:01 PM PDT 24
Finished Jun 13 01:34:17 PM PDT 24
Peak memory 197184 kb
Host smart-c5ed3ad0-277d-42e9-9225-6724f7ccd95c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246366320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stres
s.246366320
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.2065453547
Short name T226
Test name
Test status
Simulation time 179964476 ps
CPU time 0.91 seconds
Started Jun 13 01:57:58 PM PDT 24
Finished Jun 13 01:58:01 PM PDT 24
Peak memory 196044 kb
Host smart-10af1464-548f-4718-b741-f4cb4adcddcf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065453547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.2065453547
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.2277637142
Short name T404
Test name
Test status
Simulation time 115697395 ps
CPU time 1.05 seconds
Started Jun 13 02:05:48 PM PDT 24
Finished Jun 13 02:05:51 PM PDT 24
Peak memory 196716 kb
Host smart-6d1e86d2-6377-49cd-b19c-06671b25d52a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277637142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.2277637142
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.1614810387
Short name T371
Test name
Test status
Simulation time 105535365 ps
CPU time 1.21 seconds
Started Jun 13 01:05:19 PM PDT 24
Finished Jun 13 01:05:24 PM PDT 24
Peak memory 196644 kb
Host smart-c8ed4ed7-cdd5-4bca-b04a-af64d400cc7e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614810387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.1614810387
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.4270702381
Short name T421
Test name
Test status
Simulation time 65428211 ps
CPU time 1.68 seconds
Started Jun 13 02:09:38 PM PDT 24
Finished Jun 13 02:09:41 PM PDT 24
Peak memory 196708 kb
Host smart-bba558da-ca25-42f7-a19b-b16cdd4e7c42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270702381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.4270702381
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.2054159580
Short name T496
Test name
Test status
Simulation time 214243632 ps
CPU time 1.33 seconds
Started Jun 13 01:27:09 PM PDT 24
Finished Jun 13 01:27:12 PM PDT 24
Peak memory 197064 kb
Host smart-75cfef93-1f5b-483d-a977-0b6a4aa5ea37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054159580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.2054159580
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.2632580021
Short name T201
Test name
Test status
Simulation time 46878074 ps
CPU time 0.99 seconds
Started Jun 13 01:41:25 PM PDT 24
Finished Jun 13 01:41:27 PM PDT 24
Peak memory 195828 kb
Host smart-02a6b57d-55af-4c8f-93c5-9c1f2c4783a3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632580021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.2632580021
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.3293898831
Short name T550
Test name
Test status
Simulation time 998528867 ps
CPU time 6.26 seconds
Started Jun 13 01:30:56 PM PDT 24
Finished Jun 13 01:31:03 PM PDT 24
Peak memory 198036 kb
Host smart-752072a3-4b5c-4a8f-aab2-761777a5b451
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293898831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.3293898831
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.964207261
Short name T197
Test name
Test status
Simulation time 55789924 ps
CPU time 1.09 seconds
Started Jun 13 01:11:18 PM PDT 24
Finished Jun 13 01:11:20 PM PDT 24
Peak memory 196440 kb
Host smart-71d7d518-611a-4b7d-bb8b-283473d76e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964207261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.964207261
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.323938829
Short name T272
Test name
Test status
Simulation time 82576047 ps
CPU time 1.34 seconds
Started Jun 13 01:59:01 PM PDT 24
Finished Jun 13 01:59:04 PM PDT 24
Peak memory 197140 kb
Host smart-b24d916c-67e9-401a-a07c-8a98a1f9856c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323938829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.323938829
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.1292246357
Short name T349
Test name
Test status
Simulation time 15253801623 ps
CPU time 99.3 seconds
Started Jun 13 12:50:57 PM PDT 24
Finished Jun 13 12:52:36 PM PDT 24
Peak memory 198056 kb
Host smart-56c8e7fd-ce32-425a-95ae-27d239eb04ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292246357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.1292246357
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.3426964808
Short name T61
Test name
Test status
Simulation time 49748363717 ps
CPU time 1334.93 seconds
Started Jun 13 01:46:25 PM PDT 24
Finished Jun 13 02:08:42 PM PDT 24
Peak memory 198168 kb
Host smart-b55221d2-990f-4589-b8f6-b64d7b6e6963
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3426964808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.3426964808
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.2978006611
Short name T16
Test name
Test status
Simulation time 32236511 ps
CPU time 0.6 seconds
Started Jun 13 01:53:55 PM PDT 24
Finished Jun 13 01:53:57 PM PDT 24
Peak memory 193768 kb
Host smart-79c190cb-2f4d-46a7-8670-9516a720a2ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978006611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.2978006611
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.4049346009
Short name T530
Test name
Test status
Simulation time 154675039 ps
CPU time 0.92 seconds
Started Jun 13 01:56:43 PM PDT 24
Finished Jun 13 01:56:46 PM PDT 24
Peak memory 195244 kb
Host smart-d1dc5282-726d-4820-9643-eb95b4ccead7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049346009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.4049346009
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.589868637
Short name T346
Test name
Test status
Simulation time 526081719 ps
CPU time 6.74 seconds
Started Jun 13 02:04:20 PM PDT 24
Finished Jun 13 02:04:29 PM PDT 24
Peak memory 195516 kb
Host smart-9c832d41-18ce-455b-9e2f-f3611ae981dd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589868637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stres
s.589868637
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.3182116225
Short name T284
Test name
Test status
Simulation time 133129683 ps
CPU time 0.62 seconds
Started Jun 13 12:53:54 PM PDT 24
Finished Jun 13 12:53:55 PM PDT 24
Peak memory 195096 kb
Host smart-5e167589-6651-43e6-b3d5-8284d6a48b7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182116225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.3182116225
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.2793050547
Short name T168
Test name
Test status
Simulation time 51037746 ps
CPU time 1.1 seconds
Started Jun 13 01:54:59 PM PDT 24
Finished Jun 13 01:55:01 PM PDT 24
Peak memory 196892 kb
Host smart-5941ccea-6e47-4ff8-8d82-7c8ce773c7a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793050547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.2793050547
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.31175781
Short name T431
Test name
Test status
Simulation time 58764170 ps
CPU time 1.46 seconds
Started Jun 13 01:16:52 PM PDT 24
Finished Jun 13 01:16:54 PM PDT 24
Peak memory 196756 kb
Host smart-beb0fbf9-25ff-44a3-ad69-dddeed10a0aa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31175781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 48.gpio_intr_with_filter_rand_intr_event.31175781
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.924214643
Short name T618
Test name
Test status
Simulation time 99551216 ps
CPU time 2.74 seconds
Started Jun 13 01:19:50 PM PDT 24
Finished Jun 13 01:19:53 PM PDT 24
Peak memory 197232 kb
Host smart-cd279a08-aac4-4532-b568-9b2003ee4168
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924214643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger.
924214643
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.4268328590
Short name T610
Test name
Test status
Simulation time 77339302 ps
CPU time 1.42 seconds
Started Jun 13 01:26:45 PM PDT 24
Finished Jun 13 01:26:47 PM PDT 24
Peak memory 197028 kb
Host smart-a06791a8-952b-44f2-90d4-9a3629ab98a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268328590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.4268328590
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.2731807142
Short name T405
Test name
Test status
Simulation time 59116864 ps
CPU time 1.22 seconds
Started Jun 13 01:37:07 PM PDT 24
Finished Jun 13 01:37:09 PM PDT 24
Peak memory 198052 kb
Host smart-3d25271b-49c5-4c02-a76f-131a74910e1a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731807142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.2731807142
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.325803330
Short name T696
Test name
Test status
Simulation time 464850528 ps
CPU time 2.27 seconds
Started Jun 13 12:48:52 PM PDT 24
Finished Jun 13 12:48:54 PM PDT 24
Peak memory 197908 kb
Host smart-9ba7dd20-7d5a-408a-84a6-b5e672c1caa7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325803330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ran
dom_long_reg_writes_reg_reads.325803330
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.377609344
Short name T467
Test name
Test status
Simulation time 83046561 ps
CPU time 0.82 seconds
Started Jun 13 12:48:53 PM PDT 24
Finished Jun 13 12:48:54 PM PDT 24
Peak memory 195068 kb
Host smart-b285d37e-a70a-453f-aec1-0bb2b00abbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377609344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.377609344
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.2647835875
Short name T379
Test name
Test status
Simulation time 130895702 ps
CPU time 1.03 seconds
Started Jun 13 01:21:16 PM PDT 24
Finished Jun 13 01:21:18 PM PDT 24
Peak memory 196504 kb
Host smart-83c0ab61-431a-4bc8-88b1-249d74f5ac17
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647835875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.2647835875
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.1452642828
Short name T1
Test name
Test status
Simulation time 34101799066 ps
CPU time 86.81 seconds
Started Jun 13 02:44:23 PM PDT 24
Finished Jun 13 02:45:57 PM PDT 24
Peak memory 198172 kb
Host smart-eda92024-d35f-40fc-8eac-f44cae6b5ec8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452642828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.1452642828
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.91954889
Short name T560
Test name
Test status
Simulation time 253258894446 ps
CPU time 1071.39 seconds
Started Jun 13 12:48:51 PM PDT 24
Finished Jun 13 01:06:42 PM PDT 24
Peak memory 198096 kb
Host smart-1247f680-2c2f-47ae-86c0-5a4618b711d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=91954889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.91954889
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.988378255
Short name T595
Test name
Test status
Simulation time 12797753 ps
CPU time 0.57 seconds
Started Jun 13 12:58:47 PM PDT 24
Finished Jun 13 12:58:49 PM PDT 24
Peak memory 194432 kb
Host smart-538f5f5c-fbb1-4a99-bf5c-4bbc8d66ffec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988378255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.988378255
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.2291144750
Short name T485
Test name
Test status
Simulation time 92020226 ps
CPU time 0.92 seconds
Started Jun 13 02:40:43 PM PDT 24
Finished Jun 13 02:40:49 PM PDT 24
Peak memory 196496 kb
Host smart-80f6abb0-4d17-40a0-b895-7202531b5281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291144750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.2291144750
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.851385119
Short name T620
Test name
Test status
Simulation time 125279224 ps
CPU time 3.15 seconds
Started Jun 13 01:23:16 PM PDT 24
Finished Jun 13 01:23:20 PM PDT 24
Peak memory 195532 kb
Host smart-edcc1def-0193-4ae2-a093-6be8f1298b75
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851385119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stres
s.851385119
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.2559121786
Short name T498
Test name
Test status
Simulation time 132146107 ps
CPU time 0.9 seconds
Started Jun 13 02:29:58 PM PDT 24
Finished Jun 13 02:29:59 PM PDT 24
Peak memory 197792 kb
Host smart-8a550dfb-b207-405b-8030-2d451164a8ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559121786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.2559121786
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.3479626374
Short name T228
Test name
Test status
Simulation time 78777488 ps
CPU time 1.28 seconds
Started Jun 13 02:11:45 PM PDT 24
Finished Jun 13 02:11:48 PM PDT 24
Peak memory 197216 kb
Host smart-5bb05d4b-df5b-4e1f-922b-0e9111d83b9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479626374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.3479626374
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.3560347840
Short name T262
Test name
Test status
Simulation time 257786472 ps
CPU time 2.65 seconds
Started Jun 13 01:31:41 PM PDT 24
Finished Jun 13 01:31:45 PM PDT 24
Peak memory 198064 kb
Host smart-9df33b40-e51d-4464-9b32-1fa1d57336e7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560347840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.3560347840
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.3422948405
Short name T397
Test name
Test status
Simulation time 145018961 ps
CPU time 1 seconds
Started Jun 13 12:48:59 PM PDT 24
Finished Jun 13 12:49:01 PM PDT 24
Peak memory 195548 kb
Host smart-3a4bc72a-4256-4aec-9eac-eb0742b9a52e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422948405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.3422948405
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.3618180464
Short name T684
Test name
Test status
Simulation time 19421401 ps
CPU time 0.7 seconds
Started Jun 13 02:01:55 PM PDT 24
Finished Jun 13 02:01:56 PM PDT 24
Peak memory 194296 kb
Host smart-878bb029-8b6f-4525-a595-c839545a0826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618180464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.3618180464
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.1652050807
Short name T599
Test name
Test status
Simulation time 196994155 ps
CPU time 1.15 seconds
Started Jun 13 01:42:20 PM PDT 24
Finished Jun 13 01:42:21 PM PDT 24
Peak memory 196024 kb
Host smart-4a276ac7-8e58-420d-b6b8-c260e1bcadce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652050807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.1652050807
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.3615520754
Short name T596
Test name
Test status
Simulation time 2169552730 ps
CPU time 7.1 seconds
Started Jun 13 02:15:33 PM PDT 24
Finished Jun 13 02:15:42 PM PDT 24
Peak memory 198088 kb
Host smart-e3e9c3dc-025e-4386-9fb5-fd4d142b6966
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615520754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.3615520754
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.2987366147
Short name T102
Test name
Test status
Simulation time 128675611 ps
CPU time 1.42 seconds
Started Jun 13 02:01:32 PM PDT 24
Finished Jun 13 02:01:34 PM PDT 24
Peak memory 196016 kb
Host smart-de63b264-065b-4017-802b-dcb38da9ed65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987366147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.2987366147
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.3620421555
Short name T247
Test name
Test status
Simulation time 47546976 ps
CPU time 1.12 seconds
Started Jun 13 02:01:54 PM PDT 24
Finished Jun 13 02:01:56 PM PDT 24
Peak memory 195720 kb
Host smart-8ea02b0f-ec13-4864-8fc9-78131489dd17
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620421555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.3620421555
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.169337822
Short name T537
Test name
Test status
Simulation time 19146452722 ps
CPU time 48.96 seconds
Started Jun 13 01:11:09 PM PDT 24
Finished Jun 13 01:12:01 PM PDT 24
Peak memory 198124 kb
Host smart-799ca760-4a1f-4bf4-9897-7807cb240712
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169337822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.g
pio_stress_all.169337822
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.3518245685
Short name T457
Test name
Test status
Simulation time 22776644 ps
CPU time 0.55 seconds
Started Jun 13 12:46:04 PM PDT 24
Finished Jun 13 12:46:06 PM PDT 24
Peak memory 193752 kb
Host smart-bba2f94e-ecf1-4dcb-8805-466b0637b336
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518245685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.3518245685
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.2328437492
Short name T309
Test name
Test status
Simulation time 67990914 ps
CPU time 1.07 seconds
Started Jun 13 12:46:02 PM PDT 24
Finished Jun 13 12:46:03 PM PDT 24
Peak memory 195816 kb
Host smart-2b134e1a-ac48-4d63-813b-f26442936469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328437492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.2328437492
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.352582483
Short name T462
Test name
Test status
Simulation time 67603276 ps
CPU time 3.38 seconds
Started Jun 13 12:46:05 PM PDT 24
Finished Jun 13 12:46:10 PM PDT 24
Peak memory 195816 kb
Host smart-f5e65469-3ce1-447e-b848-41fd8a7bd844
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352582483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stress
.352582483
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.3690228266
Short name T21
Test name
Test status
Simulation time 278817294 ps
CPU time 0.83 seconds
Started Jun 13 12:46:02 PM PDT 24
Finished Jun 13 12:46:04 PM PDT 24
Peak memory 195776 kb
Host smart-f57895fa-366f-48d6-8a2d-8801ac4448bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690228266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.3690228266
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.1582505091
Short name T260
Test name
Test status
Simulation time 61801767 ps
CPU time 0.7 seconds
Started Jun 13 12:46:03 PM PDT 24
Finished Jun 13 12:46:04 PM PDT 24
Peak memory 194156 kb
Host smart-e12292e3-38d0-4078-8c17-e8b58ba15556
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582505091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.1582505091
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.2408242142
Short name T476
Test name
Test status
Simulation time 159535417 ps
CPU time 1.89 seconds
Started Jun 13 12:46:00 PM PDT 24
Finished Jun 13 12:46:02 PM PDT 24
Peak memory 197296 kb
Host smart-85e93d90-6085-410c-b371-3d55e82560e4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408242142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.2408242142
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.3696046519
Short name T526
Test name
Test status
Simulation time 80729733 ps
CPU time 1.93 seconds
Started Jun 13 12:46:06 PM PDT 24
Finished Jun 13 12:46:09 PM PDT 24
Peak memory 195968 kb
Host smart-f6c9ad7a-2aff-4a6c-8194-5f18d303d990
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696046519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
3696046519
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.1117549133
Short name T664
Test name
Test status
Simulation time 57568307 ps
CPU time 1.06 seconds
Started Jun 13 12:46:17 PM PDT 24
Finished Jun 13 12:46:18 PM PDT 24
Peak memory 196444 kb
Host smart-91e53672-6d29-48a1-9325-63528f3f2bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117549133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.1117549133
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.477314575
Short name T470
Test name
Test status
Simulation time 82397365 ps
CPU time 0.72 seconds
Started Jun 13 12:46:01 PM PDT 24
Finished Jun 13 12:46:02 PM PDT 24
Peak memory 195148 kb
Host smart-97c5c2b1-4c4f-430f-a55a-f724bfd3e3fd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477314575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup_
pulldown.477314575
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.2071240890
Short name T148
Test name
Test status
Simulation time 547768406 ps
CPU time 2.82 seconds
Started Jun 13 12:46:04 PM PDT 24
Finished Jun 13 12:46:09 PM PDT 24
Peak memory 197808 kb
Host smart-6a10a490-35c2-4414-ae9c-cf324cac194d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071240890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.2071240890
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.3179155980
Short name T522
Test name
Test status
Simulation time 48616431 ps
CPU time 1.16 seconds
Started Jun 13 12:46:04 PM PDT 24
Finished Jun 13 12:46:07 PM PDT 24
Peak memory 195640 kb
Host smart-7cc1ea5e-995c-4cda-81fb-397d516e77cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179155980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.3179155980
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.1400882894
Short name T688
Test name
Test status
Simulation time 54050039 ps
CPU time 1.16 seconds
Started Jun 13 12:46:04 PM PDT 24
Finished Jun 13 12:46:06 PM PDT 24
Peak memory 195640 kb
Host smart-1287f6d5-2b45-404c-bb54-5eabfb3be548
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400882894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.1400882894
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.2639428129
Short name T242
Test name
Test status
Simulation time 8963141048 ps
CPU time 132.68 seconds
Started Jun 13 12:46:04 PM PDT 24
Finished Jun 13 12:48:18 PM PDT 24
Peak memory 197920 kb
Host smart-d075851a-bbaa-40b4-92c9-31bd72cc5c6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639428129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.2639428129
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.2993301669
Short name T623
Test name
Test status
Simulation time 11489212 ps
CPU time 0.55 seconds
Started Jun 13 12:46:08 PM PDT 24
Finished Jun 13 12:46:10 PM PDT 24
Peak memory 193696 kb
Host smart-b31af4cc-d939-4f74-818f-c766c57f5e05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993301669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.2993301669
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.1760094077
Short name T267
Test name
Test status
Simulation time 98697442 ps
CPU time 0.74 seconds
Started Jun 13 12:46:07 PM PDT 24
Finished Jun 13 12:46:08 PM PDT 24
Peak memory 194080 kb
Host smart-021ec08d-d4ed-43d0-9eb0-660fc4cfcd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760094077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.1760094077
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.1375825293
Short name T438
Test name
Test status
Simulation time 8787103508 ps
CPU time 20.56 seconds
Started Jun 13 12:46:10 PM PDT 24
Finished Jun 13 12:46:31 PM PDT 24
Peak memory 197404 kb
Host smart-e53ab249-1eaf-447d-b2c0-af04784e3aed
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375825293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.1375825293
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.3567928636
Short name T697
Test name
Test status
Simulation time 90451203 ps
CPU time 0.86 seconds
Started Jun 13 12:46:10 PM PDT 24
Finished Jun 13 12:46:12 PM PDT 24
Peak memory 195824 kb
Host smart-0ca4b880-6e84-4d64-97a3-fce1b06daf87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567928636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.3567928636
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.1512388534
Short name T588
Test name
Test status
Simulation time 59277628 ps
CPU time 1.13 seconds
Started Jun 13 12:46:09 PM PDT 24
Finished Jun 13 12:46:11 PM PDT 24
Peak memory 195752 kb
Host smart-d6f50895-11b2-4dc1-8df3-91da4a5f5e27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512388534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.1512388534
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.2062286428
Short name T135
Test name
Test status
Simulation time 1378912036 ps
CPU time 3.33 seconds
Started Jun 13 12:46:08 PM PDT 24
Finished Jun 13 12:46:13 PM PDT 24
Peak memory 198092 kb
Host smart-c9733785-8a65-4ea1-9b46-d21e6dd06f83
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062286428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.2062286428
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.2827199433
Short name T213
Test name
Test status
Simulation time 142142961 ps
CPU time 2.74 seconds
Started Jun 13 12:46:10 PM PDT 24
Finished Jun 13 12:46:13 PM PDT 24
Peak memory 197056 kb
Host smart-f6a7cf1c-f898-4107-8205-2fafa1467761
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827199433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
2827199433
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.537449666
Short name T670
Test name
Test status
Simulation time 62662333 ps
CPU time 1.15 seconds
Started Jun 13 12:46:03 PM PDT 24
Finished Jun 13 12:46:05 PM PDT 24
Peak memory 195988 kb
Host smart-8c527f48-f82b-4a36-8717-2a7ef2727dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537449666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.537449666
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.3546395812
Short name T271
Test name
Test status
Simulation time 261182039 ps
CPU time 1.22 seconds
Started Jun 13 12:46:06 PM PDT 24
Finished Jun 13 12:46:08 PM PDT 24
Peak memory 196596 kb
Host smart-0db5eb66-8ba5-4204-91ca-c173791207a4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546395812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.3546395812
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.1237377507
Short name T103
Test name
Test status
Simulation time 75971182 ps
CPU time 3.33 seconds
Started Jun 13 12:46:12 PM PDT 24
Finished Jun 13 12:46:16 PM PDT 24
Peak memory 197820 kb
Host smart-12cd95b4-bf37-4c69-b138-e6ac3a22cd3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237377507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.1237377507
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.4284880174
Short name T250
Test name
Test status
Simulation time 96904984 ps
CPU time 1.56 seconds
Started Jun 13 12:46:03 PM PDT 24
Finished Jun 13 12:46:06 PM PDT 24
Peak memory 196792 kb
Host smart-3e1aea55-eb19-4832-af7b-330fe227e6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284880174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.4284880174
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.391563017
Short name T495
Test name
Test status
Simulation time 60062490 ps
CPU time 1.07 seconds
Started Jun 13 12:46:08 PM PDT 24
Finished Jun 13 12:46:10 PM PDT 24
Peak memory 195644 kb
Host smart-3edd4c90-746c-4b46-bbc0-b5137f89a545
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391563017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.391563017
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.3225368827
Short name T387
Test name
Test status
Simulation time 9262828992 ps
CPU time 134.11 seconds
Started Jun 13 12:46:07 PM PDT 24
Finished Jun 13 12:48:22 PM PDT 24
Peak memory 198072 kb
Host smart-f88bc0df-6235-4f3a-be38-7f10180b9a65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225368827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.3225368827
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.1044500896
Short name T56
Test name
Test status
Simulation time 134868576184 ps
CPU time 724.66 seconds
Started Jun 13 12:46:13 PM PDT 24
Finished Jun 13 12:58:19 PM PDT 24
Peak memory 198056 kb
Host smart-32bc6ac8-711f-43d5-8476-bf209e446f2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1044500896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.1044500896
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.2775696888
Short name T575
Test name
Test status
Simulation time 13401873 ps
CPU time 0.58 seconds
Started Jun 13 12:46:12 PM PDT 24
Finished Jun 13 12:46:13 PM PDT 24
Peak memory 193700 kb
Host smart-48420211-5b79-49c1-b99c-bb770665214d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775696888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.2775696888
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.497509840
Short name T178
Test name
Test status
Simulation time 174437271 ps
CPU time 0.93 seconds
Started Jun 13 12:46:10 PM PDT 24
Finished Jun 13 12:46:11 PM PDT 24
Peak memory 196628 kb
Host smart-9caa228f-46e9-4e58-9b64-78e7e3d365e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497509840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.497509840
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.2665140548
Short name T55
Test name
Test status
Simulation time 113297857 ps
CPU time 3.67 seconds
Started Jun 13 12:46:10 PM PDT 24
Finished Jun 13 12:46:14 PM PDT 24
Peak memory 195752 kb
Host smart-14fd8b73-85d2-467e-bdb0-df6f2f63298c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665140548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.2665140548
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.985409865
Short name T370
Test name
Test status
Simulation time 115465403 ps
CPU time 1.13 seconds
Started Jun 13 12:46:11 PM PDT 24
Finished Jun 13 12:46:13 PM PDT 24
Peak memory 196512 kb
Host smart-3a675775-6ec4-42f7-8445-55c6baec1939
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985409865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.985409865
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.2654392927
Short name T477
Test name
Test status
Simulation time 340285136 ps
CPU time 1.25 seconds
Started Jun 13 12:46:09 PM PDT 24
Finished Jun 13 12:46:11 PM PDT 24
Peak memory 196124 kb
Host smart-ff110be3-eed3-4d88-b11b-19d7bb6764b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654392927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.2654392927
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.1008232904
Short name T298
Test name
Test status
Simulation time 73032006 ps
CPU time 2.87 seconds
Started Jun 13 12:46:08 PM PDT 24
Finished Jun 13 12:46:12 PM PDT 24
Peak memory 196472 kb
Host smart-85d26ec6-af32-490a-bbf2-5192ef816fa2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008232904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.1008232904
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.3721587575
Short name T270
Test name
Test status
Simulation time 1025213967 ps
CPU time 3.42 seconds
Started Jun 13 12:46:12 PM PDT 24
Finished Jun 13 12:46:16 PM PDT 24
Peak memory 197080 kb
Host smart-44740f40-8b3a-49f0-8cac-ac7551aee47a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721587575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
3721587575
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.684805590
Short name T66
Test name
Test status
Simulation time 65658031 ps
CPU time 0.98 seconds
Started Jun 13 12:46:07 PM PDT 24
Finished Jun 13 12:46:09 PM PDT 24
Peak memory 196652 kb
Host smart-dbc89f64-bd66-499e-bd75-79e9e8216080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684805590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.684805590
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.830891307
Short name T580
Test name
Test status
Simulation time 90550770 ps
CPU time 1 seconds
Started Jun 13 12:46:12 PM PDT 24
Finished Jun 13 12:46:13 PM PDT 24
Peak memory 195860 kb
Host smart-bdb7facb-aa50-41f8-be1b-6515dcbe4c18
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830891307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup_
pulldown.830891307
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.505304494
Short name T617
Test name
Test status
Simulation time 612552450 ps
CPU time 2.13 seconds
Started Jun 13 12:46:13 PM PDT 24
Finished Jun 13 12:46:16 PM PDT 24
Peak memory 197904 kb
Host smart-128d1348-49bd-4f02-a3ce-0852df7603fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505304494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand
om_long_reg_writes_reg_reads.505304494
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.970292440
Short name T549
Test name
Test status
Simulation time 74443753 ps
CPU time 1.17 seconds
Started Jun 13 12:46:08 PM PDT 24
Finished Jun 13 12:46:10 PM PDT 24
Peak memory 195792 kb
Host smart-4b065f79-155a-49ac-ab0c-9ceff008ba22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970292440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.970292440
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.2230095733
Short name T283
Test name
Test status
Simulation time 45641617 ps
CPU time 1.28 seconds
Started Jun 13 12:46:05 PM PDT 24
Finished Jun 13 12:46:08 PM PDT 24
Peak memory 195816 kb
Host smart-989634e0-e539-4fb7-a5cc-e439fd2cfc30
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230095733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.2230095733
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.1906060713
Short name T212
Test name
Test status
Simulation time 999751356 ps
CPU time 28.37 seconds
Started Jun 13 12:46:14 PM PDT 24
Finished Jun 13 12:46:43 PM PDT 24
Peak memory 198012 kb
Host smart-7d896854-81ba-4c3a-9291-55120855b45b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906060713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.1906060713
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.2716690532
Short name T374
Test name
Test status
Simulation time 13662023 ps
CPU time 0.62 seconds
Started Jun 13 12:46:22 PM PDT 24
Finished Jun 13 12:46:23 PM PDT 24
Peak memory 193776 kb
Host smart-5ee5d961-3342-4373-8a7b-6685a61355c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716690532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.2716690532
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.329261100
Short name T396
Test name
Test status
Simulation time 146848833 ps
CPU time 0.9 seconds
Started Jun 13 12:46:19 PM PDT 24
Finished Jun 13 12:46:20 PM PDT 24
Peak memory 196464 kb
Host smart-ea18deb6-05a6-48a3-9e5d-f53a5de249ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329261100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.329261100
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.1976059170
Short name T511
Test name
Test status
Simulation time 432011972 ps
CPU time 11.69 seconds
Started Jun 13 12:46:14 PM PDT 24
Finished Jun 13 12:46:27 PM PDT 24
Peak memory 198000 kb
Host smart-3599bd28-fab3-467a-9c48-79de2823211e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976059170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.1976059170
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.66861252
Short name T3
Test name
Test status
Simulation time 153928961 ps
CPU time 0.8 seconds
Started Jun 13 12:46:13 PM PDT 24
Finished Jun 13 12:46:14 PM PDT 24
Peak memory 195572 kb
Host smart-c788e594-26d0-40a3-a047-095c046aa7c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66861252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.66861252
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.615758011
Short name T121
Test name
Test status
Simulation time 83116840 ps
CPU time 0.95 seconds
Started Jun 13 12:46:12 PM PDT 24
Finished Jun 13 12:46:14 PM PDT 24
Peak memory 195912 kb
Host smart-7f13ec4a-fd7d-4395-a572-a5c2298b428c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615758011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.615758011
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.192379671
Short name T234
Test name
Test status
Simulation time 35427622 ps
CPU time 1.57 seconds
Started Jun 13 12:46:15 PM PDT 24
Finished Jun 13 12:46:17 PM PDT 24
Peak memory 196448 kb
Host smart-c540a17c-cf3a-4c33-9c21-7aa64b357e50
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192379671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.gpio_intr_with_filter_rand_intr_event.192379671
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.4272737675
Short name T177
Test name
Test status
Simulation time 121109503 ps
CPU time 1.91 seconds
Started Jun 13 12:46:14 PM PDT 24
Finished Jun 13 12:46:16 PM PDT 24
Peak memory 196648 kb
Host smart-6fc00745-4b47-4923-8350-ee6038ba4e53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272737675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
4272737675
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.853041108
Short name T224
Test name
Test status
Simulation time 19332392 ps
CPU time 0.83 seconds
Started Jun 13 12:46:15 PM PDT 24
Finished Jun 13 12:46:16 PM PDT 24
Peak memory 195976 kb
Host smart-1cfd5da6-b6ab-40e6-bb96-9c9326014ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853041108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.853041108
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.764226305
Short name T328
Test name
Test status
Simulation time 71249242 ps
CPU time 0.85 seconds
Started Jun 13 12:46:14 PM PDT 24
Finished Jun 13 12:46:15 PM PDT 24
Peak memory 196428 kb
Host smart-f37a5509-27c5-46cd-8efe-3bdc5866e0b3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764226305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup_
pulldown.764226305
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.3953562377
Short name T143
Test name
Test status
Simulation time 277770108 ps
CPU time 4.48 seconds
Started Jun 13 12:46:15 PM PDT 24
Finished Jun 13 12:46:20 PM PDT 24
Peak memory 197932 kb
Host smart-7c4390d6-2b69-422a-8113-46e822ee119a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953562377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.3953562377
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.1451676815
Short name T609
Test name
Test status
Simulation time 221913658 ps
CPU time 1.03 seconds
Started Jun 13 12:46:20 PM PDT 24
Finished Jun 13 12:46:21 PM PDT 24
Peak memory 195708 kb
Host smart-7c0bff40-b6cb-4b75-8150-9a285be46471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451676815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.1451676815
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.3963750739
Short name T13
Test name
Test status
Simulation time 29545259 ps
CPU time 0.94 seconds
Started Jun 13 12:46:20 PM PDT 24
Finished Jun 13 12:46:21 PM PDT 24
Peak memory 196392 kb
Host smart-42cd9b2d-e750-4e8c-b65c-22f6cd88c7a6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963750739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.3963750739
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.4035790571
Short name T244
Test name
Test status
Simulation time 28522353610 ps
CPU time 225.32 seconds
Started Jun 13 12:46:13 PM PDT 24
Finished Jun 13 12:49:59 PM PDT 24
Peak memory 198016 kb
Host smart-a5fe0628-e4d6-4bfa-8ab7-938df21209da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035790571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.4035790571
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.2070868905
Short name T29
Test name
Test status
Simulation time 63295006683 ps
CPU time 586.68 seconds
Started Jun 13 12:46:22 PM PDT 24
Finished Jun 13 12:56:10 PM PDT 24
Peak memory 198148 kb
Host smart-23226cd9-f6ed-4747-aff5-603baba2f4e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2070868905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.2070868905
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.4160038602
Short name T352
Test name
Test status
Simulation time 17660916 ps
CPU time 0.57 seconds
Started Jun 13 12:46:24 PM PDT 24
Finished Jun 13 12:46:25 PM PDT 24
Peak memory 194432 kb
Host smart-eeb7a71f-5c0b-4e28-bbaf-311bb9a60b2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160038602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.4160038602
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.1081098814
Short name T161
Test name
Test status
Simulation time 60247052 ps
CPU time 0.94 seconds
Started Jun 13 12:46:23 PM PDT 24
Finished Jun 13 12:46:25 PM PDT 24
Peak memory 195788 kb
Host smart-c6ec252e-d1b7-44ca-a527-711daf9da622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081098814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.1081098814
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.1354202451
Short name T539
Test name
Test status
Simulation time 175656467 ps
CPU time 9.28 seconds
Started Jun 13 12:46:24 PM PDT 24
Finished Jun 13 12:46:34 PM PDT 24
Peak memory 196884 kb
Host smart-a484e44c-c195-4678-8c34-69a95978ebf6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354202451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.1354202451
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.449400845
Short name T124
Test name
Test status
Simulation time 115182981 ps
CPU time 0.65 seconds
Started Jun 13 12:46:22 PM PDT 24
Finished Jun 13 12:46:24 PM PDT 24
Peak memory 194388 kb
Host smart-692056b1-e774-4d8d-bf4a-3a6f621fa96d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449400845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.449400845
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.548592032
Short name T393
Test name
Test status
Simulation time 148886051 ps
CPU time 1.14 seconds
Started Jun 13 12:46:23 PM PDT 24
Finished Jun 13 12:46:25 PM PDT 24
Peak memory 195888 kb
Host smart-4fea477b-ef16-47c3-8542-cc9f3545e916
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548592032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.548592032
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.3956784314
Short name T64
Test name
Test status
Simulation time 290733656 ps
CPU time 3.03 seconds
Started Jun 13 12:46:23 PM PDT 24
Finished Jun 13 12:46:27 PM PDT 24
Peak memory 198084 kb
Host smart-0a78e1ce-3c76-4c70-8d2e-3be95c0762e3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956784314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.3956784314
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.2336038904
Short name T409
Test name
Test status
Simulation time 728310025 ps
CPU time 2.7 seconds
Started Jun 13 12:46:22 PM PDT 24
Finished Jun 13 12:46:26 PM PDT 24
Peak memory 198152 kb
Host smart-a9dfbcfb-40a5-48c7-8b55-0f3a22c2498b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336038904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
2336038904
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.3929499945
Short name T164
Test name
Test status
Simulation time 44127393 ps
CPU time 0.77 seconds
Started Jun 13 12:46:22 PM PDT 24
Finished Jun 13 12:46:24 PM PDT 24
Peak memory 195288 kb
Host smart-bdc0510c-76e2-4ecf-bcce-9186a2963e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929499945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.3929499945
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.530133709
Short name T658
Test name
Test status
Simulation time 36596674 ps
CPU time 0.8 seconds
Started Jun 13 12:46:24 PM PDT 24
Finished Jun 13 12:46:25 PM PDT 24
Peak memory 195248 kb
Host smart-f4134ba2-7917-481d-8a9a-cb3a3caa7b36
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530133709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup_
pulldown.530133709
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.352210946
Short name T146
Test name
Test status
Simulation time 76151764 ps
CPU time 3.54 seconds
Started Jun 13 12:46:22 PM PDT 24
Finished Jun 13 12:46:26 PM PDT 24
Peak memory 197936 kb
Host smart-a018141e-3353-4b44-ace8-e48c8c6e2ed0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352210946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand
om_long_reg_writes_reg_reads.352210946
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.2386966164
Short name T423
Test name
Test status
Simulation time 30321890 ps
CPU time 0.97 seconds
Started Jun 13 12:46:21 PM PDT 24
Finished Jun 13 12:46:23 PM PDT 24
Peak memory 195856 kb
Host smart-5d04f30b-1f54-4428-9559-327d5518e4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386966164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.2386966164
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.4238590360
Short name T689
Test name
Test status
Simulation time 172118901 ps
CPU time 0.94 seconds
Started Jun 13 12:46:21 PM PDT 24
Finished Jun 13 12:46:22 PM PDT 24
Peak memory 196420 kb
Host smart-43ff719b-45f4-46c2-8dd0-5b5a0438cece
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238590360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.4238590360
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.45299389
Short name T469
Test name
Test status
Simulation time 70139635814 ps
CPU time 143.59 seconds
Started Jun 13 12:46:24 PM PDT 24
Finished Jun 13 12:48:48 PM PDT 24
Peak memory 198064 kb
Host smart-332a5922-5c53-4c01-87fa-770227f69fad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45299389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpi
o_stress_all.45299389
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.602212459
Short name T871
Test name
Test status
Simulation time 261076064 ps
CPU time 1.16 seconds
Started Jun 13 12:42:35 PM PDT 24
Finished Jun 13 12:42:37 PM PDT 24
Peak memory 196352 kb
Host smart-bbb57024-5dac-4577-ba48-1dfdb9ae0fa6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=602212459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.602212459
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2810087946
Short name T905
Test name
Test status
Simulation time 67084234 ps
CPU time 1.17 seconds
Started Jun 13 12:42:33 PM PDT 24
Finished Jun 13 12:42:35 PM PDT 24
Peak memory 196284 kb
Host smart-f01d5f26-a683-4874-9655-65a684f5ce9e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810087946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2810087946
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.4032008568
Short name T911
Test name
Test status
Simulation time 161614797 ps
CPU time 1.52 seconds
Started Jun 13 12:42:33 PM PDT 24
Finished Jun 13 12:42:35 PM PDT 24
Peak memory 197164 kb
Host smart-9cfb400b-e0d9-4149-ad24-4a8a59624281
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4032008568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.4032008568
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.779476110
Short name T928
Test name
Test status
Simulation time 45211653 ps
CPU time 1.27 seconds
Started Jun 13 12:42:35 PM PDT 24
Finished Jun 13 12:42:36 PM PDT 24
Peak memory 197736 kb
Host smart-57090488-f027-4f26-8911-10ee94798850
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779476110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.779476110
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2714401497
Short name T918
Test name
Test status
Simulation time 80875026 ps
CPU time 1.15 seconds
Started Jun 13 12:42:55 PM PDT 24
Finished Jun 13 12:42:56 PM PDT 24
Peak memory 197788 kb
Host smart-babba4bd-c7b6-4f56-b25a-ca2dbbf844f4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2714401497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.2714401497
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2726354110
Short name T858
Test name
Test status
Simulation time 296292790 ps
CPU time 1.39 seconds
Started Jun 13 12:42:55 PM PDT 24
Finished Jun 13 12:42:56 PM PDT 24
Peak memory 197732 kb
Host smart-99026eec-9dda-4e86-9f29-55e50d40c684
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726354110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2726354110
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.595514854
Short name T861
Test name
Test status
Simulation time 71693068 ps
CPU time 1.28 seconds
Started Jun 13 12:42:55 PM PDT 24
Finished Jun 13 12:42:57 PM PDT 24
Peak memory 196288 kb
Host smart-6912a73c-e3c6-456f-ad17-22c43ea16ffd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=595514854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.595514854
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1401779521
Short name T841
Test name
Test status
Simulation time 47729360 ps
CPU time 0.98 seconds
Started Jun 13 12:42:55 PM PDT 24
Finished Jun 13 12:42:57 PM PDT 24
Peak memory 196408 kb
Host smart-4ce92210-11f5-4ef8-8e6f-dbe20d9976eb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401779521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1401779521
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3631695978
Short name T923
Test name
Test status
Simulation time 92102784 ps
CPU time 1.29 seconds
Started Jun 13 12:42:53 PM PDT 24
Finished Jun 13 12:42:55 PM PDT 24
Peak memory 197804 kb
Host smart-2a69811b-e41a-47d9-95b7-b46cd20193f6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3631695978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.3631695978
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1798947799
Short name T931
Test name
Test status
Simulation time 34424949 ps
CPU time 0.77 seconds
Started Jun 13 12:42:52 PM PDT 24
Finished Jun 13 12:42:53 PM PDT 24
Peak memory 195192 kb
Host smart-a86c87c8-750f-41e0-8799-e3b820b26e94
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798947799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1798947799
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2244677042
Short name T933
Test name
Test status
Simulation time 118416399 ps
CPU time 1.03 seconds
Started Jun 13 12:42:53 PM PDT 24
Finished Jun 13 12:42:54 PM PDT 24
Peak memory 195580 kb
Host smart-21e7ca6b-fb76-47c0-b864-071c8f2b80b7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2244677042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.2244677042
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.432221317
Short name T894
Test name
Test status
Simulation time 126726606 ps
CPU time 1.2 seconds
Started Jun 13 12:42:54 PM PDT 24
Finished Jun 13 12:42:55 PM PDT 24
Peak memory 196312 kb
Host smart-9c8d7977-974e-472b-8f08-8792e35ec02e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432221317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.432221317
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1329964633
Short name T904
Test name
Test status
Simulation time 28986898 ps
CPU time 0.95 seconds
Started Jun 13 12:42:53 PM PDT 24
Finished Jun 13 12:42:55 PM PDT 24
Peak memory 196176 kb
Host smart-dbfe05c7-76fc-471a-92f8-28e492f81d32
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1329964633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.1329964633
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1726295870
Short name T850
Test name
Test status
Simulation time 34816750 ps
CPU time 0.9 seconds
Started Jun 13 12:42:53 PM PDT 24
Finished Jun 13 12:42:55 PM PDT 24
Peak memory 195256 kb
Host smart-ea097583-94c4-4c1e-8696-da743d848c15
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726295870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1726295870
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.447394907
Short name T865
Test name
Test status
Simulation time 65459734 ps
CPU time 1.04 seconds
Started Jun 13 12:42:59 PM PDT 24
Finished Jun 13 12:43:00 PM PDT 24
Peak memory 195476 kb
Host smart-ed93ac71-3838-47b1-855d-5689fc167c2b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=447394907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.447394907
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.293264931
Short name T849
Test name
Test status
Simulation time 171943865 ps
CPU time 1.04 seconds
Started Jun 13 12:42:59 PM PDT 24
Finished Jun 13 12:43:00 PM PDT 24
Peak memory 196368 kb
Host smart-d75e3873-a503-42e6-b187-19703bf008ab
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293264931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.293264931
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3034530352
Short name T938
Test name
Test status
Simulation time 169209907 ps
CPU time 1.29 seconds
Started Jun 13 12:42:59 PM PDT 24
Finished Jun 13 12:43:01 PM PDT 24
Peak memory 196308 kb
Host smart-78dd7af9-7a79-4c5e-a465-41b6ceca9245
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3034530352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.3034530352
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.127862054
Short name T883
Test name
Test status
Simulation time 130013193 ps
CPU time 0.97 seconds
Started Jun 13 12:43:00 PM PDT 24
Finished Jun 13 12:43:02 PM PDT 24
Peak memory 195112 kb
Host smart-5d9cf32f-50db-4d30-bcdc-5e82445a32e2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127862054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.127862054
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3470868365
Short name T863
Test name
Test status
Simulation time 323738968 ps
CPU time 1.14 seconds
Started Jun 13 12:43:01 PM PDT 24
Finished Jun 13 12:43:03 PM PDT 24
Peak memory 195404 kb
Host smart-6ec6f9e3-de69-4df9-b3ab-b610224b63c4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3470868365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.3470868365
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3989207023
Short name T929
Test name
Test status
Simulation time 286125820 ps
CPU time 1.12 seconds
Started Jun 13 12:43:00 PM PDT 24
Finished Jun 13 12:43:02 PM PDT 24
Peak memory 196380 kb
Host smart-82df2e2b-2e3c-4ad3-8d9b-0f318c70282a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989207023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3989207023
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1964205299
Short name T899
Test name
Test status
Simulation time 55018013 ps
CPU time 1.11 seconds
Started Jun 13 12:42:59 PM PDT 24
Finished Jun 13 12:43:01 PM PDT 24
Peak memory 196492 kb
Host smart-8982a907-8037-4b9d-b52d-b7c89dcf3cdf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1964205299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.1964205299
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3872978764
Short name T847
Test name
Test status
Simulation time 252686556 ps
CPU time 1.38 seconds
Started Jun 13 12:43:00 PM PDT 24
Finished Jun 13 12:43:02 PM PDT 24
Peak memory 195468 kb
Host smart-02caf1c7-c5eb-4f8f-ae47-da657faea7c9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872978764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3872978764
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.588180948
Short name T919
Test name
Test status
Simulation time 72111148 ps
CPU time 0.93 seconds
Started Jun 13 12:43:00 PM PDT 24
Finished Jun 13 12:43:02 PM PDT 24
Peak memory 197644 kb
Host smart-5acb84e2-8af3-42ed-87cd-c33c2a31d08d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=588180948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.588180948
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2165058426
Short name T851
Test name
Test status
Simulation time 50180247 ps
CPU time 1.09 seconds
Started Jun 13 12:43:26 PM PDT 24
Finished Jun 13 12:43:27 PM PDT 24
Peak memory 197764 kb
Host smart-42c45640-db37-4f1b-8239-02c0f70d14bc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165058426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2165058426
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1297424224
Short name T869
Test name
Test status
Simulation time 78013885 ps
CPU time 1.32 seconds
Started Jun 13 12:42:34 PM PDT 24
Finished Jun 13 12:42:36 PM PDT 24
Peak memory 197784 kb
Host smart-c47a5a3f-ff74-4f98-b09d-5e96da3ab47a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1297424224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.1297424224
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3966677971
Short name T922
Test name
Test status
Simulation time 33291009 ps
CPU time 0.99 seconds
Started Jun 13 12:42:32 PM PDT 24
Finished Jun 13 12:42:33 PM PDT 24
Peak memory 195556 kb
Host smart-e1caf4da-e2e0-4f81-88e6-913c4bc217bd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966677971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3966677971
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3154564858
Short name T924
Test name
Test status
Simulation time 56713443 ps
CPU time 1.18 seconds
Started Jun 13 12:43:00 PM PDT 24
Finished Jun 13 12:43:02 PM PDT 24
Peak memory 196408 kb
Host smart-ce2ebcc0-52c5-453b-b70b-391040fb1f55
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3154564858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.3154564858
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3164250725
Short name T848
Test name
Test status
Simulation time 138277184 ps
CPU time 0.9 seconds
Started Jun 13 12:43:08 PM PDT 24
Finished Jun 13 12:43:09 PM PDT 24
Peak memory 195328 kb
Host smart-86b4eb28-8ba3-4ef7-89c0-032f060d4626
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164250725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3164250725
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2850948670
Short name T896
Test name
Test status
Simulation time 85217424 ps
CPU time 0.75 seconds
Started Jun 13 12:43:06 PM PDT 24
Finished Jun 13 12:43:08 PM PDT 24
Peak memory 195252 kb
Host smart-8464e1a1-5ae3-4c05-9a87-1f9080ac06b4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2850948670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.2850948670
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3247409871
Short name T925
Test name
Test status
Simulation time 113787957 ps
CPU time 0.8 seconds
Started Jun 13 12:43:07 PM PDT 24
Finished Jun 13 12:43:09 PM PDT 24
Peak memory 195308 kb
Host smart-21ec4b61-c9d6-489f-8c75-2d7c37d87fff
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247409871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3247409871
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.4164100187
Short name T857
Test name
Test status
Simulation time 51415161 ps
CPU time 1.05 seconds
Started Jun 13 12:43:08 PM PDT 24
Finished Jun 13 12:43:10 PM PDT 24
Peak memory 196436 kb
Host smart-fb009c67-5f5a-491f-8659-8c3cff2b2120
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4164100187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.4164100187
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4013322473
Short name T914
Test name
Test status
Simulation time 52774059 ps
CPU time 1 seconds
Started Jun 13 12:43:13 PM PDT 24
Finished Jun 13 12:43:14 PM PDT 24
Peak memory 197660 kb
Host smart-886a1538-715a-4e5d-94ba-56a2d613bf2e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013322473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4013322473
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.355501567
Short name T916
Test name
Test status
Simulation time 465942466 ps
CPU time 1.31 seconds
Started Jun 13 12:43:15 PM PDT 24
Finished Jun 13 12:43:16 PM PDT 24
Peak memory 195672 kb
Host smart-6181e3ff-4d51-4e1a-87f0-3b3f24b9e6b7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=355501567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.355501567
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.721979037
Short name T855
Test name
Test status
Simulation time 230592648 ps
CPU time 1.2 seconds
Started Jun 13 12:43:16 PM PDT 24
Finished Jun 13 12:43:18 PM PDT 24
Peak memory 196832 kb
Host smart-3ca64f87-2903-4241-b315-ac227e668023
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721979037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.721979037
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1323051475
Short name T886
Test name
Test status
Simulation time 56335784 ps
CPU time 1.09 seconds
Started Jun 13 12:43:17 PM PDT 24
Finished Jun 13 12:43:18 PM PDT 24
Peak memory 195560 kb
Host smart-f6c02e01-3550-4751-b7db-ec3018b5756a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1323051475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.1323051475
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1936447460
Short name T862
Test name
Test status
Simulation time 56127049 ps
CPU time 1.27 seconds
Started Jun 13 12:43:14 PM PDT 24
Finished Jun 13 12:43:15 PM PDT 24
Peak memory 195672 kb
Host smart-96bbe32e-e1fd-4235-a1b1-a7b23b57f0c8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936447460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1936447460
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2659781670
Short name T887
Test name
Test status
Simulation time 52797218 ps
CPU time 1.04 seconds
Started Jun 13 12:43:37 PM PDT 24
Finished Jun 13 12:43:39 PM PDT 24
Peak memory 195732 kb
Host smart-d19875ba-0997-4ccf-b253-d24200ca289c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2659781670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.2659781670
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2773285643
Short name T912
Test name
Test status
Simulation time 24644855 ps
CPU time 0.8 seconds
Started Jun 13 12:43:15 PM PDT 24
Finished Jun 13 12:43:17 PM PDT 24
Peak memory 195264 kb
Host smart-8f8b5183-0555-4996-8e01-b07aae8c390d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773285643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2773285643
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3581356266
Short name T891
Test name
Test status
Simulation time 34622253 ps
CPU time 0.67 seconds
Started Jun 13 12:43:15 PM PDT 24
Finished Jun 13 12:43:16 PM PDT 24
Peak memory 194132 kb
Host smart-a780b116-d707-4a81-8cce-bb7c6d4dabba
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3581356266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.3581356266
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1740590095
Short name T879
Test name
Test status
Simulation time 130419188 ps
CPU time 1.32 seconds
Started Jun 13 12:43:15 PM PDT 24
Finished Jun 13 12:43:17 PM PDT 24
Peak memory 197784 kb
Host smart-93130ad9-14dd-469d-92b4-5e337b8b8602
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740590095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1740590095
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1355681201
Short name T900
Test name
Test status
Simulation time 197098106 ps
CPU time 0.89 seconds
Started Jun 13 12:43:16 PM PDT 24
Finished Jun 13 12:43:17 PM PDT 24
Peak memory 195904 kb
Host smart-912c4b3f-2f3b-4986-9fc4-7dd2527fce31
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1355681201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.1355681201
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2619923516
Short name T842
Test name
Test status
Simulation time 60891845 ps
CPU time 1.11 seconds
Started Jun 13 12:43:17 PM PDT 24
Finished Jun 13 12:43:18 PM PDT 24
Peak memory 196160 kb
Host smart-22865bd9-9f48-4052-8315-aeed311f257d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619923516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2619923516
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.589829431
Short name T882
Test name
Test status
Simulation time 73687568 ps
CPU time 1.32 seconds
Started Jun 13 12:43:15 PM PDT 24
Finished Jun 13 12:43:16 PM PDT 24
Peak memory 196184 kb
Host smart-d8333c50-be43-417f-a43d-185415801274
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=589829431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.589829431
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.454533064
Short name T854
Test name
Test status
Simulation time 67243769 ps
CPU time 0.99 seconds
Started Jun 13 12:43:14 PM PDT 24
Finished Jun 13 12:43:16 PM PDT 24
Peak memory 195556 kb
Host smart-17622a61-4303-469d-af9e-5b57162c4c1e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454533064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.454533064
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.128548216
Short name T845
Test name
Test status
Simulation time 161140773 ps
CPU time 1.26 seconds
Started Jun 13 12:43:17 PM PDT 24
Finished Jun 13 12:43:19 PM PDT 24
Peak memory 197680 kb
Host smart-7f456169-220f-4313-96c0-f2ec09cd6a0f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=128548216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.128548216
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1040242180
Short name T917
Test name
Test status
Simulation time 70060044 ps
CPU time 0.76 seconds
Started Jun 13 12:43:15 PM PDT 24
Finished Jun 13 12:43:16 PM PDT 24
Peak memory 195968 kb
Host smart-5242cc49-65e8-4993-bb4f-0d6136f55287
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040242180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1040242180
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.654050256
Short name T870
Test name
Test status
Simulation time 164805884 ps
CPU time 1.18 seconds
Started Jun 13 12:42:32 PM PDT 24
Finished Jun 13 12:42:34 PM PDT 24
Peak memory 197740 kb
Host smart-1b6b28b1-f39a-4678-85a3-243d94f8456e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=654050256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.654050256
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1584781254
Short name T932
Test name
Test status
Simulation time 69757489 ps
CPU time 1.2 seconds
Started Jun 13 12:42:34 PM PDT 24
Finished Jun 13 12:42:36 PM PDT 24
Peak memory 197768 kb
Host smart-2b3775d9-b051-4757-8122-c4d14ed4d42c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584781254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1584781254
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1585290789
Short name T920
Test name
Test status
Simulation time 112995563 ps
CPU time 1.05 seconds
Started Jun 13 12:43:13 PM PDT 24
Finished Jun 13 12:43:15 PM PDT 24
Peak memory 196268 kb
Host smart-a4b1ab97-c911-44b3-948e-f41633bb1bba
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1585290789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.1585290789
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3228091135
Short name T910
Test name
Test status
Simulation time 45346477 ps
CPU time 1.31 seconds
Started Jun 13 12:43:15 PM PDT 24
Finished Jun 13 12:43:17 PM PDT 24
Peak memory 196536 kb
Host smart-cdf8a347-49d6-4d1e-a6f9-d0b12c5783ea
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228091135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3228091135
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.3321793326
Short name T840
Test name
Test status
Simulation time 47560493 ps
CPU time 0.95 seconds
Started Jun 13 12:43:20 PM PDT 24
Finished Jun 13 12:43:22 PM PDT 24
Peak memory 195240 kb
Host smart-019b0efe-7785-41bd-8b38-7515514b9bee
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3321793326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.3321793326
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.874367536
Short name T909
Test name
Test status
Simulation time 33752262 ps
CPU time 1.02 seconds
Started Jun 13 12:43:20 PM PDT 24
Finished Jun 13 12:43:22 PM PDT 24
Peak memory 196392 kb
Host smart-e76ad33a-524a-457b-a138-cbc1605a8264
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874367536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.874367536
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1628870923
Short name T913
Test name
Test status
Simulation time 97757847 ps
CPU time 0.84 seconds
Started Jun 13 12:43:20 PM PDT 24
Finished Jun 13 12:43:22 PM PDT 24
Peak memory 195104 kb
Host smart-50b36895-2586-4f66-b752-6fa7be61c6ae
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1628870923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.1628870923
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3546119218
Short name T866
Test name
Test status
Simulation time 61256912 ps
CPU time 1.25 seconds
Started Jun 13 12:43:21 PM PDT 24
Finished Jun 13 12:43:22 PM PDT 24
Peak memory 196580 kb
Host smart-a15bf2c8-867f-43a4-aee1-b34115c0ad24
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546119218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3546119218
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.4291682101
Short name T885
Test name
Test status
Simulation time 144167345 ps
CPU time 1.16 seconds
Started Jun 13 12:43:20 PM PDT 24
Finished Jun 13 12:43:21 PM PDT 24
Peak memory 196444 kb
Host smart-05ee1caa-a290-43ee-a714-ea82f24d95f0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4291682101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.4291682101
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1541185198
Short name T868
Test name
Test status
Simulation time 225668994 ps
CPU time 1.16 seconds
Started Jun 13 12:43:22 PM PDT 24
Finished Jun 13 12:43:24 PM PDT 24
Peak memory 196404 kb
Host smart-8edbeb8c-385d-4b04-923a-a04e071c064a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541185198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1541185198
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3643312131
Short name T898
Test name
Test status
Simulation time 445834349 ps
CPU time 1.24 seconds
Started Jun 13 12:43:22 PM PDT 24
Finished Jun 13 12:43:23 PM PDT 24
Peak memory 195392 kb
Host smart-5d116ac7-b238-41ca-b426-6e9e5ba1e895
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3643312131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.3643312131
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1037188793
Short name T874
Test name
Test status
Simulation time 90900636 ps
CPU time 0.99 seconds
Started Jun 13 12:43:21 PM PDT 24
Finished Jun 13 12:43:22 PM PDT 24
Peak memory 195412 kb
Host smart-736aed8f-4aa1-436c-8664-3980e59b3580
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037188793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1037188793
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3238972852
Short name T853
Test name
Test status
Simulation time 196904179 ps
CPU time 1.07 seconds
Started Jun 13 12:43:21 PM PDT 24
Finished Jun 13 12:43:22 PM PDT 24
Peak memory 196552 kb
Host smart-d604d6b5-c60d-4ff0-9348-f197071b0cc1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3238972852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.3238972852
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.67394864
Short name T860
Test name
Test status
Simulation time 52492092 ps
CPU time 0.99 seconds
Started Jun 13 12:43:21 PM PDT 24
Finished Jun 13 12:43:23 PM PDT 24
Peak memory 197728 kb
Host smart-c33356fe-f7cd-4856-944a-8eb708319f0f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67394864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.67394864
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2822589260
Short name T892
Test name
Test status
Simulation time 373063744 ps
CPU time 1.63 seconds
Started Jun 13 12:43:20 PM PDT 24
Finished Jun 13 12:43:22 PM PDT 24
Peak memory 196324 kb
Host smart-2d8e3ce0-6303-468e-acc2-4960c514cf96
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2822589260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.2822589260
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3654069868
Short name T844
Test name
Test status
Simulation time 144627064 ps
CPU time 1.01 seconds
Started Jun 13 12:43:21 PM PDT 24
Finished Jun 13 12:43:22 PM PDT 24
Peak memory 196528 kb
Host smart-5098c54e-6833-4dec-95c5-b8ce31c15926
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654069868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3654069868
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1046365601
Short name T880
Test name
Test status
Simulation time 218798518 ps
CPU time 0.95 seconds
Started Jun 13 12:43:19 PM PDT 24
Finished Jun 13 12:43:20 PM PDT 24
Peak memory 196440 kb
Host smart-d8916e12-26a0-471a-bf8b-cb555e2b3a2c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1046365601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.1046365601
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.834727254
Short name T927
Test name
Test status
Simulation time 35081848 ps
CPU time 1.06 seconds
Started Jun 13 12:43:22 PM PDT 24
Finished Jun 13 12:43:23 PM PDT 24
Peak memory 196248 kb
Host smart-972e226b-3188-4bb5-8727-d178d3c0bf20
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834727254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.834727254
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3475434775
Short name T873
Test name
Test status
Simulation time 26503222 ps
CPU time 0.88 seconds
Started Jun 13 12:43:28 PM PDT 24
Finished Jun 13 12:43:29 PM PDT 24
Peak memory 196460 kb
Host smart-862cee96-09a3-4907-b5a2-cbf5fec7a9e3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3475434775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.3475434775
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2624906323
Short name T881
Test name
Test status
Simulation time 37349081 ps
CPU time 0.94 seconds
Started Jun 13 12:43:26 PM PDT 24
Finished Jun 13 12:43:27 PM PDT 24
Peak memory 195200 kb
Host smart-97d37941-e63c-49b8-b40f-4cc642b3d4ef
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624906323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2624906323
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3889685111
Short name T867
Test name
Test status
Simulation time 89247958 ps
CPU time 1 seconds
Started Jun 13 12:43:30 PM PDT 24
Finished Jun 13 12:43:31 PM PDT 24
Peak memory 197676 kb
Host smart-01614a63-4ee9-4325-983a-93cdbdba253b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3889685111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.3889685111
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1703757129
Short name T907
Test name
Test status
Simulation time 33982261 ps
CPU time 0.89 seconds
Started Jun 13 12:43:28 PM PDT 24
Finished Jun 13 12:43:30 PM PDT 24
Peak memory 195440 kb
Host smart-caac7154-c2f7-4b94-b940-e3f5e03bdcb1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703757129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1703757129
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1130439782
Short name T890
Test name
Test status
Simulation time 27474500 ps
CPU time 0.99 seconds
Started Jun 13 12:42:39 PM PDT 24
Finished Jun 13 12:42:40 PM PDT 24
Peak memory 196248 kb
Host smart-5d3de2c9-4712-4f8c-a7b1-e1b7fb6f4c14
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1130439782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.1130439782
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2420263190
Short name T921
Test name
Test status
Simulation time 147595690 ps
CPU time 0.96 seconds
Started Jun 13 12:42:44 PM PDT 24
Finished Jun 13 12:42:45 PM PDT 24
Peak memory 196340 kb
Host smart-1955c928-4c7a-4848-970f-0816bb7c1136
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420263190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2420263190
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2686517056
Short name T878
Test name
Test status
Simulation time 439801181 ps
CPU time 1.09 seconds
Started Jun 13 12:43:29 PM PDT 24
Finished Jun 13 12:43:30 PM PDT 24
Peak memory 195480 kb
Host smart-52b2b9d7-b6cc-4b9c-ab8d-93e258ac7701
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2686517056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.2686517056
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2696186082
Short name T877
Test name
Test status
Simulation time 173436733 ps
CPU time 1.02 seconds
Started Jun 13 12:43:28 PM PDT 24
Finished Jun 13 12:43:30 PM PDT 24
Peak memory 195532 kb
Host smart-ab16ef2c-69fe-489e-8000-5045c9f3865c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696186082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2696186082
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1282013196
Short name T906
Test name
Test status
Simulation time 205277156 ps
CPU time 1.28 seconds
Started Jun 13 12:43:32 PM PDT 24
Finished Jun 13 12:43:34 PM PDT 24
Peak memory 196464 kb
Host smart-8cf8b120-8fab-407e-8d76-ae8d259e0ed6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1282013196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.1282013196
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3980008707
Short name T908
Test name
Test status
Simulation time 32975516 ps
CPU time 1.08 seconds
Started Jun 13 12:43:28 PM PDT 24
Finished Jun 13 12:43:29 PM PDT 24
Peak memory 196388 kb
Host smart-5c2001cd-cf8f-4d5b-9f54-c3fd768ac2ad
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980008707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3980008707
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1647842574
Short name T839
Test name
Test status
Simulation time 267774912 ps
CPU time 1.22 seconds
Started Jun 13 12:43:32 PM PDT 24
Finished Jun 13 12:43:34 PM PDT 24
Peak memory 196396 kb
Host smart-a1bc4673-9c3c-4c8f-9124-6b540aeceec7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1647842574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.1647842574
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1857048011
Short name T937
Test name
Test status
Simulation time 32300431 ps
CPU time 1.03 seconds
Started Jun 13 12:43:28 PM PDT 24
Finished Jun 13 12:43:29 PM PDT 24
Peak memory 196908 kb
Host smart-06f4d27e-d867-471a-aa2f-30d72adf0228
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857048011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1857048011
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.54374823
Short name T859
Test name
Test status
Simulation time 274952237 ps
CPU time 1.44 seconds
Started Jun 13 12:43:35 PM PDT 24
Finished Jun 13 12:43:37 PM PDT 24
Peak memory 196468 kb
Host smart-b81b5d15-4e17-4afa-8a18-802731557f4a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=54374823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.54374823
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3409701243
Short name T935
Test name
Test status
Simulation time 71890695 ps
CPU time 1.2 seconds
Started Jun 13 12:43:35 PM PDT 24
Finished Jun 13 12:43:36 PM PDT 24
Peak memory 196448 kb
Host smart-87171d97-6543-456e-acaa-72e32156b6ec
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409701243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3409701243
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.21429379
Short name T901
Test name
Test status
Simulation time 55986092 ps
CPU time 1.1 seconds
Started Jun 13 12:43:34 PM PDT 24
Finished Jun 13 12:43:35 PM PDT 24
Peak memory 195640 kb
Host smart-704de2d5-ebf7-43d8-83d1-ade791a4df93
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=21429379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.21429379
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2219596483
Short name T902
Test name
Test status
Simulation time 42663498 ps
CPU time 1.31 seconds
Started Jun 13 12:43:35 PM PDT 24
Finished Jun 13 12:43:37 PM PDT 24
Peak memory 195400 kb
Host smart-210645a4-2397-4e3e-a569-e05afc3d97e0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219596483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2219596483
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1204846783
Short name T875
Test name
Test status
Simulation time 27783755 ps
CPU time 0.83 seconds
Started Jun 13 12:43:38 PM PDT 24
Finished Jun 13 12:43:39 PM PDT 24
Peak memory 195140 kb
Host smart-557430f3-a038-4483-b15d-04bcac0ca9ab
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1204846783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.1204846783
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1304915966
Short name T846
Test name
Test status
Simulation time 68543416 ps
CPU time 1.17 seconds
Started Jun 13 12:43:35 PM PDT 24
Finished Jun 13 12:43:37 PM PDT 24
Peak memory 197312 kb
Host smart-6970d15a-25e9-4c4d-8166-9a627d042e63
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304915966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1304915966
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.25637116
Short name T852
Test name
Test status
Simulation time 463387995 ps
CPU time 1.07 seconds
Started Jun 13 12:43:35 PM PDT 24
Finished Jun 13 12:43:36 PM PDT 24
Peak memory 196340 kb
Host smart-5da40361-1214-4981-b5a3-bec633750554
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=25637116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.25637116
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2667850963
Short name T864
Test name
Test status
Simulation time 65000004 ps
CPU time 1.22 seconds
Started Jun 13 12:43:37 PM PDT 24
Finished Jun 13 12:43:38 PM PDT 24
Peak memory 196328 kb
Host smart-80f4f3c6-7be7-47c7-a18f-8914272cc521
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667850963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2667850963
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.917926191
Short name T936
Test name
Test status
Simulation time 210574354 ps
CPU time 1.15 seconds
Started Jun 13 12:43:34 PM PDT 24
Finished Jun 13 12:43:36 PM PDT 24
Peak memory 196380 kb
Host smart-945fbb5e-3fca-441a-9e39-0722648444f2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=917926191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.917926191
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1536466210
Short name T856
Test name
Test status
Simulation time 180736047 ps
CPU time 1.05 seconds
Started Jun 13 12:43:35 PM PDT 24
Finished Jun 13 12:43:37 PM PDT 24
Peak memory 195372 kb
Host smart-73773b95-10be-42d5-972d-12fb6ea8c69a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536466210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1536466210
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3128894376
Short name T884
Test name
Test status
Simulation time 42989954 ps
CPU time 0.88 seconds
Started Jun 13 12:43:35 PM PDT 24
Finished Jun 13 12:43:36 PM PDT 24
Peak memory 196012 kb
Host smart-ab433307-8b65-44ca-8ffe-225593740e74
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3128894376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3128894376
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.802275554
Short name T915
Test name
Test status
Simulation time 102846083 ps
CPU time 1.18 seconds
Started Jun 13 12:43:36 PM PDT 24
Finished Jun 13 12:43:38 PM PDT 24
Peak memory 197256 kb
Host smart-224302a8-d00c-4ce0-be7d-1048be50ba88
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802275554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.802275554
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2202563846
Short name T889
Test name
Test status
Simulation time 787653861 ps
CPU time 0.91 seconds
Started Jun 13 12:43:35 PM PDT 24
Finished Jun 13 12:43:37 PM PDT 24
Peak memory 195236 kb
Host smart-dcae324e-a35b-43e0-8e4f-0e6849a689a8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2202563846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.2202563846
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2897826578
Short name T903
Test name
Test status
Simulation time 35140756 ps
CPU time 0.99 seconds
Started Jun 13 12:43:34 PM PDT 24
Finished Jun 13 12:43:35 PM PDT 24
Peak memory 196316 kb
Host smart-a0526716-7a36-4c33-9daf-4e6c128cbd4c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897826578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2897826578
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1903852845
Short name T926
Test name
Test status
Simulation time 62283350 ps
CPU time 1.13 seconds
Started Jun 13 12:42:40 PM PDT 24
Finished Jun 13 12:42:42 PM PDT 24
Peak memory 197736 kb
Host smart-32c3480e-f3b3-40a6-88c0-b3d2b719b3c8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1903852845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.1903852845
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3137927266
Short name T843
Test name
Test status
Simulation time 80065223 ps
CPU time 1.14 seconds
Started Jun 13 12:42:44 PM PDT 24
Finished Jun 13 12:42:45 PM PDT 24
Peak memory 196540 kb
Host smart-a5e95f71-c08d-4025-a1d4-f5ac4caabcd1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137927266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3137927266
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2672540846
Short name T897
Test name
Test status
Simulation time 30545050 ps
CPU time 0.99 seconds
Started Jun 13 12:42:45 PM PDT 24
Finished Jun 13 12:42:47 PM PDT 24
Peak memory 197816 kb
Host smart-a22f19de-f803-429e-bdfe-0245c89f7f37
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2672540846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.2672540846
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.942263728
Short name T893
Test name
Test status
Simulation time 74646072 ps
CPU time 1.35 seconds
Started Jun 13 12:42:47 PM PDT 24
Finished Jun 13 12:42:49 PM PDT 24
Peak memory 196660 kb
Host smart-e715b8b4-abdd-4a22-a29b-a039c057a4be
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942263728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.942263728
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.44881413
Short name T895
Test name
Test status
Simulation time 50264810 ps
CPU time 1.27 seconds
Started Jun 13 12:42:45 PM PDT 24
Finished Jun 13 12:42:47 PM PDT 24
Peak memory 196804 kb
Host smart-adf2d48a-6111-4b18-a7fc-c28dcc908022
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=44881413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.44881413
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2469976554
Short name T888
Test name
Test status
Simulation time 241716286 ps
CPU time 1.2 seconds
Started Jun 13 12:42:45 PM PDT 24
Finished Jun 13 12:42:47 PM PDT 24
Peak memory 195424 kb
Host smart-b23700b3-14d4-4802-b7c4-b19b4a279f2e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469976554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2469976554
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3521643321
Short name T930
Test name
Test status
Simulation time 311460653 ps
CPU time 1.44 seconds
Started Jun 13 12:42:47 PM PDT 24
Finished Jun 13 12:42:49 PM PDT 24
Peak memory 197668 kb
Host smart-eb6b060e-76ac-4478-9eb2-2ce44205eb8f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3521643321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.3521643321
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3389924190
Short name T872
Test name
Test status
Simulation time 30917629 ps
CPU time 0.91 seconds
Started Jun 13 12:42:46 PM PDT 24
Finished Jun 13 12:42:47 PM PDT 24
Peak memory 196168 kb
Host smart-615755ea-ab9f-430c-a612-c90d2a0ffe59
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389924190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3389924190
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2857327837
Short name T934
Test name
Test status
Simulation time 128457247 ps
CPU time 1.02 seconds
Started Jun 13 12:42:44 PM PDT 24
Finished Jun 13 12:42:46 PM PDT 24
Peak memory 196460 kb
Host smart-faf3d5c2-3aec-4410-9925-b58260808e12
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2857327837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.2857327837
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2962296516
Short name T876
Test name
Test status
Simulation time 243636530 ps
CPU time 1.22 seconds
Started Jun 13 12:42:58 PM PDT 24
Finished Jun 13 12:43:00 PM PDT 24
Peak memory 196548 kb
Host smart-a475b213-8546-497d-adc4-e3d370663484
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962296516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2962296516
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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