Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3553041	1			T24	1		T25	1		T26	102
all_pins[1]	3553041	1			T24	1		T25	1		T26	102
all_pins[2]	3553041	1			T24	1		T25	1		T26	102
all_pins[3]	3553041	1			T24	1		T25	1		T26	102
all_pins[4]	3553041	1			T24	1		T25	1		T26	102
all_pins[5]	3553041	1			T24	1		T25	1		T26	102
all_pins[6]	3553041	1			T24	1		T25	1		T26	102
all_pins[7]	3553041	1			T24	1		T25	1		T26	102
all_pins[8]	3553041	1			T24	1		T25	1		T26	102
all_pins[9]	3553041	1			T24	1		T25	1		T26	102
all_pins[10]	3553041	1			T24	1		T25	1		T26	102
all_pins[11]	3553041	1			T24	1		T25	1		T26	102
all_pins[12]	3553041	1			T24	1		T25	1		T26	102
all_pins[13]	3553041	1			T24	1		T25	1		T26	102
all_pins[14]	3553041	1			T24	1		T25	1		T26	102
all_pins[15]	3553041	1			T24	1		T25	1		T26	102
all_pins[16]	3553041	1			T24	1		T25	1		T26	102
all_pins[17]	3553041	1			T24	1		T25	1		T26	102
all_pins[18]	3553041	1			T24	1		T25	1		T26	102
all_pins[19]	3553041	1			T24	1		T25	1		T26	102
all_pins[20]	3553041	1			T24	1		T25	1		T26	102
all_pins[21]	3553041	1			T24	1		T25	1		T26	102
all_pins[22]	3553041	1			T24	1		T25	1		T26	102
all_pins[23]	3553041	1			T24	1		T25	1		T26	102
all_pins[24]	3553041	1			T24	1		T25	1		T26	102
all_pins[25]	3553041	1			T24	1		T25	1		T26	102
all_pins[26]	3553041	1			T24	1		T25	1		T26	102
all_pins[27]	3553041	1			T24	1		T25	1		T26	102
all_pins[28]	3553041	1			T24	1		T25	1		T26	102
all_pins[29]	3553041	1			T24	1		T25	1		T26	102
all_pins[30]	3553041	1			T24	1		T25	1		T26	102
all_pins[31]	3553041	1			T24	1		T25	1		T26	102

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	70613127	1			T24	32		T25	32		T26	1664
values[0x1]	43084185	1			T26	1600		T27	2547		T28	9555
transitions[0x0=>0x1]	25805465	1			T26	802		T27	1607		T28	5899
transitions[0x1=>0x0]	25805307	1			T26	801		T27	1606		T28	5899

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2205461	1			T24	1		T25	1		T26	59
all_pins[0]	values[0x1]	1347580	1			T26	43		T27	54		T28	274
all_pins[0]	transitions[0x0=>0x1]	832936	1			T26	29		T27	19		T28	123
all_pins[0]	transitions[0x1=>0x0]	834640	1			T26	33		T27	40		T28	186
all_pins[1]	values[0x0]	2209376	1			T24	1		T25	1		T26	58
all_pins[1]	values[0x1]	1343665	1			T26	44		T27	85		T28	305
all_pins[1]	transitions[0x0=>0x1]	802932	1			T26	26		T27	55		T28	212
all_pins[1]	transitions[0x1=>0x0]	806847	1			T26	25		T27	24		T28	181
all_pins[2]	values[0x0]	2202429	1			T24	1		T25	1		T26	51
all_pins[2]	values[0x1]	1350612	1			T26	51		T27	100		T28	290
all_pins[2]	transitions[0x0=>0x1]	808699	1			T26	30		T27	60		T28	182
all_pins[2]	transitions[0x1=>0x0]	801752	1			T26	23		T27	45		T28	197
all_pins[3]	values[0x0]	2207832	1			T24	1		T25	1		T26	53
all_pins[3]	values[0x1]	1345209	1			T26	49		T27	61		T28	335
all_pins[3]	transitions[0x0=>0x1]	803239	1			T26	21		T27	31		T28	237
all_pins[3]	transitions[0x1=>0x0]	808642	1			T26	23		T27	70		T28	192
all_pins[4]	values[0x0]	2202419	1			T24	1		T25	1		T26	50
all_pins[4]	values[0x1]	1350622	1			T26	52		T27	96		T28	260
all_pins[4]	transitions[0x0=>0x1]	807613	1			T26	24		T27	73		T28	164
all_pins[4]	transitions[0x1=>0x0]	802200	1			T26	21		T27	38		T28	239
all_pins[5]	values[0x0]	2208435	1			T24	1		T25	1		T26	43
all_pins[5]	values[0x1]	1344606	1			T26	59		T27	100		T28	237
all_pins[5]	transitions[0x0=>0x1]	802080	1			T26	24		T27	45		T28	164
all_pins[5]	transitions[0x1=>0x0]	808096	1			T26	17		T27	41		T28	187
all_pins[6]	values[0x0]	2209278	1			T24	1		T25	1		T26	50
all_pins[6]	values[0x1]	1343763	1			T26	52		T27	110		T28	269
all_pins[6]	transitions[0x0=>0x1]	804984	1			T26	22		T27	57		T28	184
all_pins[6]	transitions[0x1=>0x0]	805827	1			T26	29		T27	47		T28	152
all_pins[7]	values[0x0]	2202729	1			T24	1		T25	1		T26	52
all_pins[7]	values[0x1]	1350312	1			T26	50		T27	75		T28	334
all_pins[7]	transitions[0x0=>0x1]	806423	1			T26	28		T27	29		T28	224
all_pins[7]	transitions[0x1=>0x0]	799874	1			T26	30		T27	64		T28	159
all_pins[8]	values[0x0]	2205959	1			T24	1		T25	1		T26	52
all_pins[8]	values[0x1]	1347082	1			T26	50		T27	69		T28	225
all_pins[8]	transitions[0x0=>0x1]	803059	1			T26	23		T27	55		T28	115
all_pins[8]	transitions[0x1=>0x0]	806289	1			T26	23		T27	61		T28	224
all_pins[9]	values[0x0]	2208091	1			T24	1		T25	1		T26	51
all_pins[9]	values[0x1]	1344950	1			T26	51		T27	60		T28	340
all_pins[9]	transitions[0x0=>0x1]	805287	1			T26	24		T27	46		T28	243
all_pins[9]	transitions[0x1=>0x0]	807419	1			T26	23		T27	55		T28	128
all_pins[10]	values[0x0]	2202974	1			T24	1		T25	1		T26	51
all_pins[10]	values[0x1]	1350067	1			T26	51		T27	88		T28	323
all_pins[10]	transitions[0x0=>0x1]	809386	1			T26	24		T27	65		T28	185
all_pins[10]	transitions[0x1=>0x0]	804269	1			T26	24		T27	37		T28	202
all_pins[11]	values[0x0]	2211203	1			T24	1		T25	1		T26	52
all_pins[11]	values[0x1]	1341838	1			T26	50		T27	86		T28	256
all_pins[11]	transitions[0x0=>0x1]	802018	1			T26	21		T27	43		T28	124
all_pins[11]	transitions[0x1=>0x0]	810247	1			T26	22		T27	45		T28	191
all_pins[12]	values[0x0]	2207444	1			T24	1		T25	1		T26	57
all_pins[12]	values[0x1]	1345597	1			T26	45		T27	65		T28	322
all_pins[12]	transitions[0x0=>0x1]	806225	1			T26	17		T27	47		T28	207
all_pins[12]	transitions[0x1=>0x0]	802466	1			T26	22		T27	68		T28	141
all_pins[13]	values[0x0]	2205244	1			T24	1		T25	1		T26	45
all_pins[13]	values[0x1]	1347797	1			T26	57		T27	97		T28	242
all_pins[13]	transitions[0x0=>0x1]	806064	1			T26	32		T27	72		T28	141
all_pins[13]	transitions[0x1=>0x0]	803864	1			T26	20		T27	40		T28	221
all_pins[14]	values[0x0]	2208374	1			T24	1		T25	1		T26	55
all_pins[14]	values[0x1]	1344667	1			T26	47		T27	76		T28	363
all_pins[14]	transitions[0x0=>0x1]	803697	1			T26	18		T27	39		T28	225
all_pins[14]	transitions[0x1=>0x0]	806827	1			T26	28		T27	60		T28	104
all_pins[15]	values[0x0]	2210220	1			T24	1		T25	1		T26	48
all_pins[15]	values[0x1]	1342821	1			T26	54		T27	97		T28	273
all_pins[15]	transitions[0x0=>0x1]	805371	1			T26	35		T27	53		T28	152
all_pins[15]	transitions[0x1=>0x0]	807217	1			T26	28		T27	32		T28	242
all_pins[16]	values[0x0]	2205911	1			T24	1		T25	1		T26	53
all_pins[16]	values[0x1]	1347130	1			T26	49		T27	63		T28	321
all_pins[16]	transitions[0x0=>0x1]	807632	1			T26	26		T27	46		T28	229
all_pins[16]	transitions[0x1=>0x0]	803323	1			T26	31		T27	80		T28	181
all_pins[17]	values[0x0]	2207046	1			T24	1		T25	1		T26	48
all_pins[17]	values[0x1]	1345995	1			T26	54		T27	95		T28	302
all_pins[17]	transitions[0x0=>0x1]	804350	1			T26	24		T27	79		T28	175
all_pins[17]	transitions[0x1=>0x0]	805485	1			T26	19		T27	47		T28	194
all_pins[18]	values[0x0]	2205241	1			T24	1		T25	1		T26	48
all_pins[18]	values[0x1]	1347800	1			T26	54		T27	56		T28	310
all_pins[18]	transitions[0x0=>0x1]	806427	1			T26	23		T27	44		T28	179
all_pins[18]	transitions[0x1=>0x0]	804622	1			T26	23		T27	83		T28	171
all_pins[19]	values[0x0]	2210972	1			T24	1		T25	1		T26	53
all_pins[19]	values[0x1]	1342069	1			T26	49		T27	84		T28	291
all_pins[19]	transitions[0x0=>0x1]	801442	1			T26	23		T27	69		T28	182
all_pins[19]	transitions[0x1=>0x0]	807173	1			T26	28		T27	41		T28	201
all_pins[20]	values[0x0]	2203912	1			T24	1		T25	1		T26	62
all_pins[20]	values[0x1]	1349129	1			T26	40		T27	66		T28	315
all_pins[20]	transitions[0x0=>0x1]	810245	1			T26	20		T27	42		T28	190
all_pins[20]	transitions[0x1=>0x0]	803185	1			T26	29		T27	60		T28	166
all_pins[21]	values[0x0]	2209989	1			T24	1		T25	1		T26	58
all_pins[21]	values[0x1]	1343052	1			T26	44		T27	57		T28	303
all_pins[21]	transitions[0x0=>0x1]	804200	1			T26	29		T27	34		T28	190
all_pins[21]	transitions[0x1=>0x0]	810277	1			T26	25		T27	43		T28	202
all_pins[22]	values[0x0]	2207330	1			T24	1		T25	1		T26	55
all_pins[22]	values[0x1]	1345711	1			T26	47		T27	89		T28	261
all_pins[22]	transitions[0x0=>0x1]	809447	1			T26	24		T27	60		T28	147
all_pins[22]	transitions[0x1=>0x0]	806788	1			T26	21		T27	28		T28	189
all_pins[23]	values[0x0]	2208740	1			T24	1		T25	1		T26	50
all_pins[23]	values[0x1]	1344301	1			T26	52		T27	88		T28	321
all_pins[23]	transitions[0x0=>0x1]	804751	1			T26	24		T27	58		T28	199
all_pins[23]	transitions[0x1=>0x0]	806161	1			T26	19		T27	59		T28	139
all_pins[24]	values[0x0]	2209563	1			T24	1		T25	1		T26	48
all_pins[24]	values[0x1]	1343478	1			T26	54		T27	75		T28	353
all_pins[24]	transitions[0x0=>0x1]	803726	1			T26	29		T27	40		T28	200
all_pins[24]	transitions[0x1=>0x0]	804549	1			T26	27		T27	53		T28	168
all_pins[25]	values[0x0]	2204812	1			T24	1		T25	1		T26	47
all_pins[25]	values[0x1]	1348229	1			T26	55		T27	80		T28	299
all_pins[25]	transitions[0x0=>0x1]	809649	1			T26	27		T27	46		T28	152
all_pins[25]	transitions[0x1=>0x0]	804898	1			T26	26		T27	41		T28	206
all_pins[26]	values[0x0]	2208133	1			T24	1		T25	1		T26	61
all_pins[26]	values[0x1]	1344908	1			T26	41		T27	73		T28	251
all_pins[26]	transitions[0x0=>0x1]	805120	1			T26	22		T27	53		T28	164
all_pins[26]	transitions[0x1=>0x0]	808441	1			T26	36		T27	60		T28	212
all_pins[27]	values[0x0]	2206510	1			T24	1		T25	1		T26	63
all_pins[27]	values[0x1]	1346531	1			T26	39		T27	65		T28	326
all_pins[27]	transitions[0x0=>0x1]	806947	1			T26	25		T27	35		T28	246
all_pins[27]	transitions[0x1=>0x0]	805324	1			T26	27		T27	43		T28	171
all_pins[28]	values[0x0]	2207363	1			T24	1		T25	1		T26	49
all_pins[28]	values[0x1]	1345678	1			T26	53		T27	119		T28	209
all_pins[28]	transitions[0x0=>0x1]	802559	1			T26	34		T27	84		T28	127
all_pins[28]	transitions[0x1=>0x0]	803412	1			T26	20		T27	30		T28	244
all_pins[29]	values[0x0]	2202861	1			T24	1		T25	1		T26	44
all_pins[29]	values[0x1]	1350180	1			T26	58		T27	68		T28	346
all_pins[29]	transitions[0x0=>0x1]	808227	1			T26	27		T27	28		T28	243
all_pins[29]	transitions[0x1=>0x0]	803725	1			T26	22		T27	79		T28	106
all_pins[30]	values[0x0]	2203677	1			T24	1		T25	1		T26	44
all_pins[30]	values[0x1]	1349364	1			T26	58		T27	74		T28	362
all_pins[30]	transitions[0x0=>0x1]	806467	1			T26	25		T27	54		T28	206
all_pins[30]	transitions[0x1=>0x0]	807283	1			T26	25		T27	48		T28	190
all_pins[31]	values[0x0]	2203599	1			T24	1		T25	1		T26	54
all_pins[31]	values[0x1]	1349442	1			T26	48		T27	76		T28	337
all_pins[31]	transitions[0x0=>0x1]	804263	1			T26	22		T27	46		T28	188
all_pins[31]	transitions[0x1=>0x0]	804185	1			T26	32		T27	44		T28	213