Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	12110107	1			T24	258		T25	298		T26	57695
all_values[1]	12110107	1			T24	258		T25	298		T26	57695
all_values[2]	12110107	1			T24	258		T25	298		T26	57695
all_values[3]	12110107	1			T24	258		T25	298		T26	57695
all_values[4]	12110107	1			T24	258		T25	298		T26	57695
all_values[5]	12110107	1			T24	258		T25	298		T26	57695
all_values[6]	12110107	1			T24	258		T25	298		T26	57695
all_values[7]	12110107	1			T24	258		T25	298		T26	57695
all_values[8]	12110107	1			T24	258		T25	298		T26	57695
all_values[9]	12110107	1			T24	258		T25	298		T26	57695
all_values[10]	12110107	1			T24	258		T25	298		T26	57695
all_values[11]	12110107	1			T24	258		T25	298		T26	57695
all_values[12]	12110107	1			T24	258		T25	298		T26	57695
all_values[13]	12110107	1			T24	258		T25	298		T26	57695
all_values[14]	12110107	1			T24	258		T25	298		T26	57695
all_values[15]	12110107	1			T24	258		T25	298		T26	57695
all_values[16]	12110107	1			T24	258		T25	298		T26	57695
all_values[17]	12110107	1			T24	258		T25	298		T26	57695
all_values[18]	12110107	1			T24	258		T25	298		T26	57695
all_values[19]	12110107	1			T24	258		T25	298		T26	57695
all_values[20]	12110107	1			T24	258		T25	298		T26	57695
all_values[21]	12110107	1			T24	258		T25	298		T26	57695
all_values[22]	12110107	1			T24	258		T25	298		T26	57695
all_values[23]	12110107	1			T24	258		T25	298		T26	57695
all_values[24]	12110107	1			T24	258		T25	298		T26	57695
all_values[25]	12110107	1			T24	258		T25	298		T26	57695
all_values[26]	12110107	1			T24	258		T25	298		T26	57695
all_values[27]	12110107	1			T24	258		T25	298		T26	57695
all_values[28]	12110107	1			T24	258		T25	298		T26	57695
all_values[29]	12110107	1			T24	258		T25	298		T26	57695
all_values[30]	12110107	1			T24	258		T25	298		T26	57695
all_values[31]	12110107	1			T24	258		T25	298		T26	57695

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

226473979

1

T24

8256

T25

9536

T26

184624

auto[1]

161049445

1

T27

5802

T28

31721

T32

187217

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

96364187

1

T24

8256

T25

9536

T26

184624

auto[1]

291159237

1

T27

9892

T28

56262

T32

337974

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

383284693

1

T24

8256

T25

9536

T26

184624

auto[1]

4238731

1

T28

2492

T32

49555

T33

141

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2522667	1			T24	258		T25	298		T26	57695
all_values[0]	auto[0]	auto[0]	auto[1]	4483824	1			T27	197		T28	928		T32	51583
all_values[0]	auto[0]	auto[1]	auto[0]	485947	1			T27	21		T28	97		T32	5902
all_values[0]	auto[0]	auto[1]	auto[1]	4485305	1			T27	90		T28	767		T32	51996
all_values[0]	auto[1]	auto[0]	auto[1]	66586	1			T28	43		T32	783		T33	2
all_values[0]	auto[1]	auto[1]	auto[1]	65778	1			T28	41		T32	741		T33	2
all_values[1]	auto[0]	auto[0]	auto[0]	2534296	1			T24	258		T25	298		T26	57695
all_values[1]	auto[0]	auto[0]	auto[1]	4476930	1			T27	152		T28	824		T32	49940
all_values[1]	auto[0]	auto[1]	auto[0]	485909	1			T27	26		T28	115		T32	6244
all_values[1]	auto[0]	auto[1]	auto[1]	4480874	1			T27	158		T28	863		T32	53455
all_values[1]	auto[1]	auto[0]	auto[1]	66365	1			T28	38		T32	757		T33	3
all_values[1]	auto[1]	auto[1]	auto[1]	65733	1			T28	37		T32	766		T33	1
all_values[2]	auto[0]	auto[0]	auto[0]	2522871	1			T24	258		T25	298		T26	57695
all_values[2]	auto[0]	auto[0]	auto[1]	4462370	1			T27	127		T28	817		T32	50433
all_values[2]	auto[0]	auto[1]	auto[0]	495604	1			T27	39		T28	137		T32	6334
all_values[2]	auto[0]	auto[1]	auto[1]	4496659	1			T27	185		T28	813		T32	52642
all_values[2]	auto[1]	auto[0]	auto[1]	66168	1			T28	33		T32	802		T33	5
all_values[2]	auto[1]	auto[1]	auto[1]	66435	1			T28	40		T32	769		T33	3
all_values[3]	auto[0]	auto[0]	auto[0]	2514558	1			T24	258		T25	298		T26	57695
all_values[3]	auto[0]	auto[0]	auto[1]	4500753	1			T27	144		T28	702		T32	51680
all_values[3]	auto[0]	auto[1]	auto[0]	482512	1			T27	29		T28	134		T32	6498
all_values[3]	auto[0]	auto[1]	auto[1]	4479871	1			T27	130		T28	957		T32	51741
all_values[3]	auto[1]	auto[0]	auto[1]	66410	1			T28	36		T32	773		T33	4
all_values[3]	auto[1]	auto[1]	auto[1]	66003	1			T28	47		T32	783		T1	17
all_values[4]	auto[0]	auto[0]	auto[0]	2525756	1			T24	258		T25	298		T26	57695
all_values[4]	auto[0]	auto[0]	auto[1]	4481846	1			T27	110		T28	827		T32	51239
all_values[4]	auto[0]	auto[1]	auto[0]	493638	1			T27	35		T28	123		T32	5560
all_values[4]	auto[0]	auto[1]	auto[1]	4476156	1			T27	194		T28	814		T32	53404
all_values[4]	auto[1]	auto[0]	auto[1]	66723	1			T28	43		T32	810		T33	2
all_values[4]	auto[1]	auto[1]	auto[1]	65988	1			T28	34		T32	784		T33	1
all_values[5]	auto[0]	auto[0]	auto[0]	2524166	1			T24	258		T25	298		T26	57695
all_values[5]	auto[0]	auto[0]	auto[1]	4497424	1			T27	118		T28	1039		T32	51469
all_values[5]	auto[0]	auto[1]	auto[0]	486536	1			T27	18		T28	85		T32	5621
all_values[5]	auto[0]	auto[1]	auto[1]	4469555	1			T27	195		T28	681		T32	52817
all_values[5]	auto[1]	auto[0]	auto[1]	67113	1			T28	62		T32	775		T33	1
all_values[5]	auto[1]	auto[1]	auto[1]	65313	1			T28	22		T32	733		T33	4
all_values[6]	auto[0]	auto[0]	auto[0]	2515064	1			T24	258		T25	298		T26	57695
all_values[6]	auto[0]	auto[0]	auto[1]	4511633	1			T27	126		T28	963		T32	53224
all_values[6]	auto[0]	auto[1]	auto[0]	489567	1			T27	22		T28	117		T32	5690
all_values[6]	auto[0]	auto[1]	auto[1]	4461581	1			T27	208		T28	760		T32	51234
all_values[6]	auto[1]	auto[0]	auto[1]	66436	1			T28	36		T32	744		T33	5
all_values[6]	auto[1]	auto[1]	auto[1]	65826	1			T28	40		T32	819		T33	1
all_values[7]	auto[0]	auto[0]	auto[0]	2517418	1			T24	258		T25	298		T26	57695
all_values[7]	auto[0]	auto[0]	auto[1]	4478107	1			T27	171		T28	608		T32	53748
all_values[7]	auto[0]	auto[1]	auto[0]	493102	1			T27	27		T28	216		T32	5623
all_values[7]	auto[0]	auto[1]	auto[1]	4489621	1			T27	129		T28	921		T32	50335
all_values[7]	auto[1]	auto[0]	auto[1]	65775	1			T28	31		T32	775		T33	1
all_values[7]	auto[1]	auto[1]	auto[1]	66084	1			T28	46		T32	775		T33	2
all_values[8]	auto[0]	auto[0]	auto[0]	2523604	1			T24	258		T25	298		T26	57695
all_values[8]	auto[0]	auto[0]	auto[1]	4478310	1			T27	217		T28	1003		T32	52744
all_values[8]	auto[0]	auto[1]	auto[0]	493024	1			T27	8		T28	129		T32	6435
all_values[8]	auto[0]	auto[1]	auto[1]	4482565	1			T27	133		T28	665		T32	51098
all_values[8]	auto[1]	auto[0]	auto[1]	66325	1			T28	44		T32	815		T33	3
all_values[8]	auto[1]	auto[1]	auto[1]	66279	1			T28	35		T32	764		T33	2
all_values[9]	auto[0]	auto[0]	auto[0]	2524560	1			T24	258		T25	298		T26	57695
all_values[9]	auto[0]	auto[0]	auto[1]	4488726	1			T27	161		T28	747		T32	51075
all_values[9]	auto[0]	auto[1]	auto[0]	490407	1			T27	45		T28	157		T32	6173
all_values[9]	auto[0]	auto[1]	auto[1]	4473957	1			T27	121		T28	933		T32	52620
all_values[9]	auto[1]	auto[0]	auto[1]	66384	1			T28	39		T32	729		T33	4
all_values[9]	auto[1]	auto[1]	auto[1]	66073	1			T28	39		T32	789		T33	1
all_values[10]	auto[0]	auto[0]	auto[0]	2517872	1			T24	258		T25	298		T26	57695
all_values[10]	auto[0]	auto[0]	auto[1]	4474242	1			T27	127		T28	817		T32	52023
all_values[10]	auto[0]	auto[1]	auto[0]	500310	1			T27	29		T28	112		T32	5520
all_values[10]	auto[0]	auto[1]	auto[1]	4485150	1			T27	188		T28	901		T32	52641
all_values[10]	auto[1]	auto[0]	auto[1]	66303	1			T28	38		T32	810		T33	2
all_values[10]	auto[1]	auto[1]	auto[1]	66230	1			T28	39		T32	737		T1	28
all_values[11]	auto[0]	auto[0]	auto[0]	2528979	1			T24	258		T25	298		T26	57695
all_values[11]	auto[0]	auto[0]	auto[1]	4492818	1			T27	157		T28	935		T32	52951
all_values[11]	auto[0]	auto[1]	auto[0]	496759	1			T27	38		T28	127		T32	5741
all_values[11]	auto[0]	auto[1]	auto[1]	4459278	1			T27	155		T28	702		T32	51190
all_values[11]	auto[1]	auto[0]	auto[1]	66880	1			T28	47		T32	774		T33	5
all_values[11]	auto[1]	auto[1]	auto[1]	65393	1			T28	25		T32	761		T1	23
all_values[12]	auto[0]	auto[0]	auto[0]	2526073	1			T24	258		T25	298		T26	57695
all_values[12]	auto[0]	auto[0]	auto[1]	4475938	1			T27	162		T28	823		T32	50623
all_values[12]	auto[0]	auto[1]	auto[0]	490123	1			T27	40		T28	90		T32	6557
all_values[12]	auto[0]	auto[1]	auto[1]	4485608	1			T27	126		T28	883		T32	53075
all_values[12]	auto[1]	auto[0]	auto[1]	66450	1			T28	36		T32	758		T33	1
all_values[12]	auto[1]	auto[1]	auto[1]	65915	1			T28	46		T32	806		T33	3
all_values[13]	auto[0]	auto[0]	auto[0]	2521090	1			T24	258		T25	298		T26	57695
all_values[13]	auto[0]	auto[0]	auto[1]	4484593	1			T27	128		T28	924		T32	52518
all_values[13]	auto[0]	auto[1]	auto[0]	491480	1			T27	21		T28	115		T32	5963
all_values[13]	auto[0]	auto[1]	auto[1]	4480156	1			T27	183		T28	746		T32	51741
all_values[13]	auto[1]	auto[0]	auto[1]	66481	1			T28	44		T32	785		T33	2
all_values[13]	auto[1]	auto[1]	auto[1]	66307	1			T28	27		T32	787		T33	2
all_values[14]	auto[0]	auto[0]	auto[0]	2520869	1			T24	258		T25	298		T26	57695
all_values[14]	auto[0]	auto[0]	auto[1]	4507735	1			T27	164		T28	799		T32	51632
all_values[14]	auto[0]	auto[1]	auto[0]	485034	1			T27	50		T28	87		T32	5929
all_values[14]	auto[0]	auto[1]	auto[1]	4464368	1			T27	149		T28	972		T32	52687
all_values[14]	auto[1]	auto[0]	auto[1]	66557	1			T28	41		T32	817		T33	5
all_values[14]	auto[1]	auto[1]	auto[1]	65544	1			T28	43		T32	706		T33	2
all_values[15]	auto[0]	auto[0]	auto[0]	2517929	1			T24	258		T25	298		T26	57695
all_values[15]	auto[0]	auto[0]	auto[1]	4508856	1			T27	147		T28	1000		T32	53287
all_values[15]	auto[0]	auto[1]	auto[0]	490614	1			T27	29		T28	89		T32	5742
all_values[15]	auto[0]	auto[1]	auto[1]	4460740	1			T27	182		T28	756		T32	50408
all_values[15]	auto[1]	auto[0]	auto[1]	66115	1			T28	54		T32	772		T33	3
all_values[15]	auto[1]	auto[1]	auto[1]	65853	1			T28	30		T32	781		T33	1
all_values[16]	auto[0]	auto[0]	auto[0]	2524163	1			T24	258		T25	298		T26	57695
all_values[16]	auto[0]	auto[0]	auto[1]	4498382	1			T27	144		T28	841		T32	52838
all_values[16]	auto[0]	auto[1]	auto[0]	490618	1			T27	54		T28	102		T32	5395
all_values[16]	auto[0]	auto[1]	auto[1]	4464693	1			T27	136		T28	873		T32	51608
all_values[16]	auto[1]	auto[0]	auto[1]	66499	1			T28	40		T32	774		T33	4
all_values[16]	auto[1]	auto[1]	auto[1]	65752	1			T28	40		T32	817		T1	26
all_values[17]	auto[0]	auto[0]	auto[0]	2513713	1			T24	258		T25	298		T26	57695
all_values[17]	auto[0]	auto[0]	auto[1]	4524005	1			T27	151		T28	839		T32	54047
all_values[17]	auto[0]	auto[1]	auto[0]	479815	1			T27	30		T28	117		T32	5578
all_values[17]	auto[0]	auto[1]	auto[1]	4460011	1			T27	156		T28	840		T32	50822
all_values[17]	auto[1]	auto[0]	auto[1]	66499	1			T28	40		T32	775		T33	4
all_values[17]	auto[1]	auto[1]	auto[1]	66064	1			T28	39		T32	790		T33	2
all_values[18]	auto[0]	auto[0]	auto[0]	2521279	1			T24	258		T25	298		T26	57695
all_values[18]	auto[0]	auto[0]	auto[1]	4489134	1			T27	172		T28	869		T32	53558
all_values[18]	auto[0]	auto[1]	auto[0]	483733	1			T27	54		T28	79		T32	5748
all_values[18]	auto[0]	auto[1]	auto[1]	4483252	1			T27	107		T28	834		T32	50272
all_values[18]	auto[1]	auto[0]	auto[1]	66522	1			T28	46		T32	679		T33	2
all_values[18]	auto[1]	auto[1]	auto[1]	66187	1			T28	36		T32	799		T33	2
all_values[19]	auto[0]	auto[0]	auto[0]	2516516	1			T24	258		T25	298		T26	57695
all_values[19]	auto[0]	auto[0]	auto[1]	4519304	1			T27	173		T28	781		T32	51968
all_values[19]	auto[0]	auto[1]	auto[0]	488287	1			T27	24		T28	136		T32	5624
all_values[19]	auto[0]	auto[1]	auto[1]	4453721	1			T27	151		T28	871		T32	52832
all_values[19]	auto[1]	auto[0]	auto[1]	66464	1			T28	43		T32	768		T33	3
all_values[19]	auto[1]	auto[1]	auto[1]	65815	1			T28	39		T32	775		T33	1
all_values[20]	auto[0]	auto[0]	auto[0]	2524084	1			T24	258		T25	298		T26	57695
all_values[20]	auto[0]	auto[0]	auto[1]	4485289	1			T27	186		T28	896		T32	52552
all_values[20]	auto[0]	auto[1]	auto[0]	488469	1			T27	20		T28	68		T32	5979
all_values[20]	auto[0]	auto[1]	auto[1]	4480036	1			T27	119		T28	821		T32	51268
all_values[20]	auto[1]	auto[0]	auto[1]	65636	1			T28	37		T32	778		T33	3
all_values[20]	auto[1]	auto[1]	auto[1]	66593	1			T28	47		T32	768		T33	2
all_values[21]	auto[0]	auto[0]	auto[0]	2529377	1			T24	258		T25	298		T26	57695
all_values[21]	auto[0]	auto[0]	auto[1]	4482634	1			T27	194		T28	857		T32	52878
all_values[21]	auto[0]	auto[1]	auto[0]	488750	1			T27	25		T28	72		T32	5692
all_values[21]	auto[0]	auto[1]	auto[1]	4476850	1			T27	109		T28	883		T32	51352
all_values[21]	auto[1]	auto[0]	auto[1]	66632	1			T28	35		T32	776		T33	1
all_values[21]	auto[1]	auto[1]	auto[1]	65864	1			T28	39		T32	767		T33	3
all_values[22]	auto[0]	auto[0]	auto[0]	2522570	1			T24	258		T25	298		T26	57695
all_values[22]	auto[0]	auto[0]	auto[1]	4459488	1			T27	131		T28	867		T32	55544
all_values[22]	auto[0]	auto[1]	auto[0]	488842	1			T27	60		T28	134		T32	6291
all_values[22]	auto[0]	auto[1]	auto[1]	4506550	1			T27	159		T28	794		T32	47912
all_values[22]	auto[1]	auto[0]	auto[1]	66589	1			T28	48		T32	794		T33	1
all_values[22]	auto[1]	auto[1]	auto[1]	66068	1			T28	31		T32	715		T1	22
all_values[23]	auto[0]	auto[0]	auto[0]	2525743	1			T24	258		T25	298		T26	57695
all_values[23]	auto[0]	auto[0]	auto[1]	4476284	1			T27	178		T28	747		T32	51591
all_values[23]	auto[0]	auto[1]	auto[0]	486670	1			T27	16		T28	133		T32	5909
all_values[23]	auto[0]	auto[1]	auto[1]	4488705	1			T27	170		T28	890		T32	52637
all_values[23]	auto[1]	auto[0]	auto[1]	66884	1			T28	38		T32	859		T1	16
all_values[23]	auto[1]	auto[1]	auto[1]	65821	1			T28	33		T32	723		T1	27
all_values[24]	auto[0]	auto[0]	auto[0]	2526484	1			T24	258		T25	298		T26	57695
all_values[24]	auto[0]	auto[0]	auto[1]	4490057	1			T27	133		T28	732		T32	51532
all_values[24]	auto[0]	auto[1]	auto[0]	482756	1			T27	52		T28	155		T32	5897
all_values[24]	auto[0]	auto[1]	auto[1]	4478268	1			T27	151		T28	940		T32	52872
all_values[24]	auto[1]	auto[0]	auto[1]	66295	1			T28	39		T32	806		T33	4
all_values[24]	auto[1]	auto[1]	auto[1]	66247	1			T28	43		T32	722		T33	1
all_values[25]	auto[0]	auto[0]	auto[0]	2527567	1			T24	258		T25	298		T26	57695
all_values[25]	auto[0]	auto[0]	auto[1]	4477653	1			T27	175		T28	763		T32	51409
all_values[25]	auto[0]	auto[1]	auto[0]	493718	1			T27	25		T28	107		T32	5836
all_values[25]	auto[0]	auto[1]	auto[1]	4478128	1			T27	135		T28	917		T32	52618
all_values[25]	auto[1]	auto[0]	auto[1]	66318	1			T28	32		T32	792		T33	5
all_values[25]	auto[1]	auto[1]	auto[1]	66723	1			T28	43		T32	746		T33	1
all_values[26]	auto[0]	auto[0]	auto[0]	2524878	1			T24	258		T25	298		T26	57695
all_values[26]	auto[0]	auto[0]	auto[1]	4504826	1			T27	203		T28	1064		T32	52371
all_values[26]	auto[0]	auto[1]	auto[0]	482228	1			T27	11		T28	88		T32	5677
all_values[26]	auto[0]	auto[1]	auto[1]	4465318	1			T27	138		T28	652		T32	51661
all_values[26]	auto[1]	auto[0]	auto[1]	66606	1			T28	38		T32	806		T33	4
all_values[26]	auto[1]	auto[1]	auto[1]	66251	1			T28	21		T32	790		T33	1
all_values[27]	auto[0]	auto[0]	auto[0]	2525008	1			T24	258		T25	298		T26	57695
all_values[27]	auto[0]	auto[0]	auto[1]	4464052	1			T27	220		T28	632		T32	52259
all_values[27]	auto[0]	auto[1]	auto[0]	484261	1			T27	12		T28	202		T32	5688
all_values[27]	auto[0]	auto[1]	auto[1]	4504544	1			T27	118		T28	944		T32	52048
all_values[27]	auto[1]	auto[0]	auto[1]	65858	1			T28	30		T32	743		T33	3
all_values[27]	auto[1]	auto[1]	auto[1]	66384	1			T28	42		T32	773		T1	20
all_values[28]	auto[0]	auto[0]	auto[0]	2521935	1			T24	258		T25	298		T26	57695
all_values[28]	auto[0]	auto[0]	auto[1]	4489407	1			T27	138		T28	986		T32	53463
all_values[28]	auto[0]	auto[1]	auto[0]	488780	1			T27	18		T28	151		T32	5585
all_values[28]	auto[0]	auto[1]	auto[1]	4477797	1			T27	208		T28	581		T32	50969
all_values[28]	auto[1]	auto[0]	auto[1]	66607	1			T28	52		T32	797		T33	3
all_values[28]	auto[1]	auto[1]	auto[1]	65581	1			T28	38		T32	755		T33	1
all_values[29]	auto[0]	auto[0]	auto[0]	2521408	1			T24	258		T25	298		T26	57695
all_values[29]	auto[0]	auto[0]	auto[1]	4508737	1			T27	147		T28	820		T32	50999
all_values[29]	auto[0]	auto[1]	auto[0]	482787	1			T27	37		T28	71		T32	5668
all_values[29]	auto[0]	auto[1]	auto[1]	4464247	1			T27	144		T28	891		T32	53506
all_values[29]	auto[1]	auto[0]	auto[1]	66948	1			T28	21		T32	830		T33	3
all_values[29]	auto[1]	auto[1]	auto[1]	65980	1			T28	57		T32	726		T33	2
all_values[30]	auto[0]	auto[0]	auto[0]	2517186	1			T24	258		T25	298		T26	57695
all_values[30]	auto[0]	auto[0]	auto[1]	4464393	1			T27	172		T28	754		T32	53429
all_values[30]	auto[0]	auto[1]	auto[0]	493585	1			T27	34		T28	134		T32	6292
all_values[30]	auto[0]	auto[1]	auto[1]	4502326	1			T27	134		T28	976		T32	50038
all_values[30]	auto[1]	auto[0]	auto[1]	66322	1			T28	38		T32	785		T33	5
all_values[30]	auto[1]	auto[1]	auto[1]	66295	1			T28	34		T32	794		T33	3
all_values[31]	auto[0]	auto[0]	auto[0]	2518673	1			T24	258		T25	298		T26	57695
all_values[31]	auto[0]	auto[0]	auto[1]	4491726	1			T27	161		T28	830		T32	50260
all_values[31]	auto[0]	auto[1]	auto[0]	491966	1			T27	47		T28	92		T32	5902
all_values[31]	auto[0]	auto[1]	auto[1]	4475140	1			T27	145		T28	895		T32	53820
all_values[31]	auto[1]	auto[0]	auto[1]	66397	1			T28	36		T32	753		T33	3
all_values[31]	auto[1]	auto[1]	auto[1]	66205	1			T28	41		T32	800		T33	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal