Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[1]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[2]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[3]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[4]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[5]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[6]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[7]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[8]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[9]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[10]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[11]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[12]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[13]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[14]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[15]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[16]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[17]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[18]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[19]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[20]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[21]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[22]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[23]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[24]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[25]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[26]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[27]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[28]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[29]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[30]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[31]	11881962	1			T24	454		T25	578		T26	57695

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

225080470

1

T24

4146

T25

14500

T26

923274

auto[1]

155142314

1

T24

10382

T25

3996

T26

922966

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

306597436

1

T24

8349

T25

13382

T26

184624

auto[1]

73625348

1

T24

6179

T25

5114

T28

24525

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

284923478

1

T24

8414

T25

9443

T26

184624

auto[1]

95299306

1

T24

6114

T25

9053

T28

29949

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4428972	1			T24	29		T25	194		T26	29330
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3321563	1			T24	130		T25	23		T26	28365
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1160997	1			T24	132		T25	122		T28	464
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1447953	1			T25	129		T28	18		T31	54
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	378947	1			T24	82		T25	31		T28	403
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1143530	1			T24	81		T25	79		T28	380
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4413310	1			T24	30		T25	203		T26	28941
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3333417	1			T24	103		T25	35		T26	28754
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1157410	1			T24	86		T25	68		T28	462
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1452431	1			T25	205		T28	29		T31	58
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	379906	1			T24	116		T25	24		T28	532
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1145488	1			T24	119		T25	43		T28	367
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4428597	1			T24	27		T25	142		T26	27793
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3320725	1			T24	146		T25	17		T26	29902
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1159109	1			T24	94		T25	63		T28	362
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1448736	1			T25	196		T28	19		T31	68
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	380613	1			T24	93		T25	38		T28	537
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1144182	1			T24	94		T25	122		T28	389
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4425254	1			T24	30		T25	184		T26	28469
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3320117	1			T24	139		T25	23		T26	29226
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1156531	1			T24	82		T25	90		T28	341
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1452748	1			T25	182		T28	22		T31	43
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	380895	1			T24	88		T25	25		T28	621
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1146417	1			T24	115		T25	74		T28	301
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4419235	1			T24	29		T25	190		T26	27007
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3320430	1			T24	144		T25	20		T26	30688
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1155323	1			T24	114		T25	75		T28	415
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1452470	1			T25	193		T28	21		T31	53
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	381088	1			T24	96		T25	21		T28	522
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1153416	1			T24	71		T25	79		T28	369
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4420240	1			T24	26		T25	164		T26	29473
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3320292	1			T24	133		T25	18		T26	28222
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1154075	1			T24	87		T25	67		T28	407
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1456900	1			T25	201		T28	11		T31	56
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	380657	1			T24	114		T25	15		T28	467
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1149798	1			T24	94		T25	113		T28	361
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4422834	1			T24	29		T25	143		T26	28958
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3322187	1			T24	128		T25	6		T26	28737
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1157253	1			T24	89		T25	79		T28	413
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1450689	1			T25	231		T28	23		T31	53
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	380762	1			T24	92		T25	36		T28	475
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1148237	1			T24	116		T25	83		T28	373
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4428129	1			T24	28		T25	200		T26	29919
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3317087	1			T24	127		T25	21		T26	27776
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1162323	1			T24	100		T25	88		T28	418
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1449598	1			T25	177		T28	23		T31	44
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	378003	1			T24	99		T25	26		T28	382
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1146822	1			T24	100		T25	66		T28	531
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4429088	1			T24	29		T25	199		T26	29923
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3316770	1			T24	128		T25	22		T26	27772
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1159718	1			T24	110		T25	70		T28	406
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1449039	1			T25	186		T28	14		T31	74
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	379644	1			T24	108		T25	29		T28	557
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1147703	1			T24	79		T25	72		T28	291
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4429368	1			T24	31		T25	211		T26	29399
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3316793	1			T24	137		T25	33		T26	28296
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1158771	1			T24	86		T25	80		T28	410
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1445537	1			T25	152		T28	30		T31	62
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	379976	1			T24	114		T25	26		T28	508
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1151517	1			T24	86		T25	76		T28	394
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4417206	1			T24	22		T25	222		T26	27506
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3328604	1			T24	152		T25	25		T26	30189
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1156923	1			T24	100		T25	94		T28	447
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1451243	1			T25	151		T28	26		T31	59
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	379662	1			T24	96		T25	14		T28	553
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1148324	1			T24	84		T25	72		T28	374
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4436771	1			T24	35		T25	225		T26	30684
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3310586	1			T24	126		T25	23		T26	27011
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1159047	1			T24	118		T25	77		T28	302
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1451996	1			T25	190		T28	21		T31	47
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	379342	1			T24	76		T25	18		T28	583
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1144220	1			T24	99		T25	45		T28	369
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4420535	1			T24	32		T25	186		T26	29463
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3322016	1			T24	142		T25	19		T26	28232
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1156914	1			T24	104		T25	79		T28	351
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1450177	1			T25	193		T28	30		T31	41
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	379392	1			T24	100		T25	26		T28	473
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1152928	1			T24	76		T25	75		T28	544
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4426094	1			T24	32		T25	178		T26	28950
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3316250	1			T24	142		T25	16		T26	28745
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1157878	1			T24	116		T25	94		T28	463
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1448782	1			T25	200		T28	26		T31	45
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	382378	1			T24	84		T25	27		T28	398
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1150580	1			T24	80		T25	63		T28	400
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4430957	1			T24	32		T25	263		T26	29579
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3313586	1			T24	115		T25	33		T26	28116
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1159814	1			T24	91		T25	113		T28	314
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1453103	1			T25	98		T28	34		T31	15
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	379063	1			T24	94		T25	14		T28	630
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1145439	1			T24	122		T25	57		T28	387
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4433933	1			T24	32		T25	140		T26	29644
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3317620	1			T24	135		T25	21		T26	28051
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1154642	1			T24	88		T25	71		T28	384
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1451263	1			T25	199		T28	13		T31	45
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	379727	1			T24	98		T25	36		T28	457
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1144777	1			T24	101		T25	111		T28	409
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4422109	1			T24	31		T25	182		T26	27883
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3328778	1			T24	109		T25	21		T26	29812
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1151805	1			T24	94		T25	70		T28	322
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1452970	1			T25	188		T28	26		T31	45
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	382136	1			T24	126		T25	19		T28	527
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1144164	1			T24	94		T25	98		T28	366
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4419714	1			T24	29		T25	211		T26	27572
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3326569	1			T24	142		T25	33		T26	30123
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1151826	1			T24	96		T25	102		T28	349
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1458149	1			T25	131		T28	19		T31	30
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	382160	1			T24	95		T25	15		T28	545
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1143544	1			T24	92		T25	86		T28	425
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4423612	1			T24	34		T25	136		T26	28651
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3328432	1			T24	145		T25	23		T26	29044
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1152195	1			T24	100		T25	60		T28	418
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1458162	1			T25	209		T28	16		T31	38
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	381031	1			T24	91		T25	35		T28	451
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1138530	1			T24	84		T25	115		T28	373
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4435065	1			T24	25		T25	167		T26	28156
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3312267	1			T24	144		T25	16		T26	29539
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1155230	1			T24	110		T25	102		T28	321
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1456259	1			T25	199		T28	15		T31	36
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	380777	1			T24	93		T25	23		T28	528
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1142364	1			T24	82		T25	71		T28	440
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4433561	1			T24	29		T25	213		T26	28734
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3323918	1			T24	162		T25	22		T26	28961
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1154795	1			T24	67		T25	76		T28	251
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1448465	1			T25	146		T28	25		T31	40
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	382421	1			T24	114		T25	26		T28	691
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1138802	1			T24	82		T25	95		T28	357
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4416600	1			T24	32		T25	161		T26	25968
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3334212	1			T24	133		T25	22		T26	31727
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1149964	1			T24	73		T25	85		T28	438
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1456322	1			T25	212		T28	22		T31	73
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	382003	1			T24	104		T25	16		T28	522
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1142861	1			T24	112		T25	82		T28	390
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4419940	1			T24	34		T25	178		T26	27631
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3325081	1			T24	143		T25	28		T26	30064
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1154767	1			T24	66		T25	76		T28	396
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1453848	1			T25	195		T28	20		T31	37
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	383143	1			T24	109		T25	24		T28	592
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1145183	1			T24	102		T25	77		T28	311
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4425430	1			T24	21		T25	222		T26	29801
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3321737	1			T24	128		T25	16		T26	27894
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1157026	1			T24	114		T25	67		T28	352
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1454471	1			T25	198		T28	22		T31	42
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	383719	1			T24	93		T25	25		T28	579
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1139579	1			T24	98		T25	50		T28	371
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4430278	1			T24	35		T25	188		T26	29660
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3328381	1			T24	123		T25	39		T26	28035
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1150522	1			T24	100		T25	72		T28	449
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1454139	1			T25	176		T28	21		T31	31
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	378841	1			T24	104		T25	28		T28	469
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1139801	1			T24	92		T25	75		T28	391
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4429606	1			T24	32		T25	212		T26	28512
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3322830	1			T24	133		T25	24		T26	29183
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1153325	1			T24	117		T25	128		T28	365
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1453534	1			T25	161		T28	11		T31	34
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	381101	1			T24	80		T25	16		T28	481
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1141566	1			T24	92		T25	37		T28	339
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4428071	1			T24	33		T25	206		T26	29191
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3325646	1			T24	148		T25	25		T26	28504
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1154085	1			T24	86		T25	90		T28	290
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1451931	1			T25	184		T28	34		T31	49
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	382727	1			T24	101		T25	17		T28	585
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1139502	1			T24	86		T25	56		T28	385
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4420362	1			T24	30		T25	213		T26	29077
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3326804	1			T24	117		T25	33		T26	28618
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1153530	1			T24	136		T25	99		T28	408
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1452651	1			T25	116		T28	28		T31	33
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	381211	1			T24	78		T25	17		T28	551
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1147404	1			T24	93		T25	100		T28	402
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4418510	1			T24	27		T25	165		T26	30881
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3321685	1			T24	132		T25	23		T26	26814
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1158114	1			T24	116		T25	84		T28	378
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1455031	1			T25	181		T28	29		T31	44
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	381809	1			T24	91		T25	37		T28	541
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1146813	1			T24	88		T25	88		T28	368
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4431821	1			T24	33		T25	220		T26	29036
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3322151	1			T24	133		T25	15		T26	28659
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1152312	1			T24	96		T25	38		T28	390
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1453974	1			T25	171		T28	26		T31	37
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	380177	1			T24	108		T25	28		T28	471
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1141527	1			T24	84		T25	106		T28	378
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4427889	1			T24	31		T25	215		T26	27566
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3325993	1			T24	124		T25	16		T26	30129
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1158176	1			T24	115		T25	79		T28	280
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1445616	1			T25	199		T28	20		T31	57
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	379628	1			T24	78		T25	28		T28	591
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1144660	1			T24	106		T25	41		T28	399
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4429387	1			T24	28		T25	164		T26	29917
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3324358	1			T24	125		T25	14		T26	27778
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1149715	1			T24	106		T25	63		T28	338
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1455690	1			T25	233		T28	34		T31	55
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	381257	1			T24	109		T25	18		T28	578
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1141555	1			T24	86		T25	86		T28	487

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal