Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[1]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[2]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[3]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[4]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[5]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[6]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[7]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[8]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[9]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[10]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[11]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[12]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[13]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[14]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[15]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[16]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[17]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[18]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[19]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[20]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[21]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[22]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[23]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[24]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[25]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[26]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[27]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[28]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[29]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[30]	11881962	1			T24	454		T25	578		T26	57695
bins_for_gpio_bits[31]	11881962	1			T24	454		T25	578		T26	57695

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

225080470

1

T24

4146

T25

14500

T26

923274

auto[1]

155142314

1

T24

10382

T25

3996

T26

922966

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

225071774

1

T24

4153

T25

14500

T26

923274

auto[1]

155151010

1

T24

10375

T25

3996

T26

922966

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	6833703	1			T24	134		T25	432		T26	29330
bins_for_gpio_bits[0]	auto[0]	auto[1]	203905	1			T24	27		T25	13		T28	62
bins_for_gpio_bits[0]	auto[1]	auto[0]	204219	1			T24	27		T25	13		T28	62
bins_for_gpio_bits[0]	auto[1]	auto[1]	4640135	1			T24	266		T25	120		T26	28365
bins_for_gpio_bits[1]	auto[0]	auto[0]	6819021	1			T24	91		T25	466		T26	28941
bins_for_gpio_bits[1]	auto[0]	auto[1]	203849	1			T24	25		T25	10		T28	59
bins_for_gpio_bits[1]	auto[1]	auto[0]	204130	1			T24	25		T25	10		T28	58
bins_for_gpio_bits[1]	auto[1]	auto[1]	4654962	1			T24	313		T25	92		T26	28754
bins_for_gpio_bits[2]	auto[0]	auto[0]	6832402	1			T24	98		T25	387		T26	27793
bins_for_gpio_bits[2]	auto[0]	auto[1]	203784	1			T24	23		T25	14		T28	58
bins_for_gpio_bits[2]	auto[1]	auto[0]	204040	1			T24	23		T25	14		T28	58
bins_for_gpio_bits[2]	auto[1]	auto[1]	4641736	1			T24	310		T25	163		T26	29902
bins_for_gpio_bits[3]	auto[0]	auto[0]	6830235	1			T24	84		T25	444		T26	28469
bins_for_gpio_bits[3]	auto[0]	auto[1]	204004	1			T24	28		T25	12		T28	52
bins_for_gpio_bits[3]	auto[1]	auto[0]	204298	1			T24	28		T25	12		T28	51
bins_for_gpio_bits[3]	auto[1]	auto[1]	4643425	1			T24	314		T25	110		T26	29226
bins_for_gpio_bits[4]	auto[0]	auto[0]	6822513	1			T24	122		T25	444		T26	27007
bins_for_gpio_bits[4]	auto[0]	auto[1]	204262	1			T24	21		T25	14		T28	50
bins_for_gpio_bits[4]	auto[1]	auto[0]	204515	1			T24	21		T25	14		T28	50
bins_for_gpio_bits[4]	auto[1]	auto[1]	4650672	1			T24	290		T25	106		T26	30688
bins_for_gpio_bits[5]	auto[0]	auto[0]	6826983	1			T24	94		T25	415		T26	29473
bins_for_gpio_bits[5]	auto[0]	auto[1]	203968	1			T24	20		T25	17		T28	59
bins_for_gpio_bits[5]	auto[1]	auto[0]	204232	1			T24	19		T25	17		T28	59
bins_for_gpio_bits[5]	auto[1]	auto[1]	4646779	1			T24	321		T25	129		T26	28222
bins_for_gpio_bits[6]	auto[0]	auto[0]	6825662	1			T24	94		T25	437		T26	28958
bins_for_gpio_bits[6]	auto[0]	auto[1]	204855	1			T24	25		T25	16		T28	62
bins_for_gpio_bits[6]	auto[1]	auto[0]	205114	1			T24	24		T25	16		T28	61
bins_for_gpio_bits[6]	auto[1]	auto[1]	4646331	1			T24	311		T25	109		T26	28737
bins_for_gpio_bits[7]	auto[0]	auto[0]	6835071	1			T24	99		T25	453		T26	29919
bins_for_gpio_bits[7]	auto[0]	auto[1]	204725	1			T24	29		T25	12		T28	55
bins_for_gpio_bits[7]	auto[1]	auto[0]	204979	1			T24	29		T25	12		T28	55
bins_for_gpio_bits[7]	auto[1]	auto[1]	4637187	1			T24	297		T25	101		T26	27776
bins_for_gpio_bits[8]	auto[0]	auto[0]	6833655	1			T24	116		T25	445		T26	29923
bins_for_gpio_bits[8]	auto[0]	auto[1]	203892	1			T24	23		T25	10		T28	59
bins_for_gpio_bits[8]	auto[1]	auto[0]	204190	1			T24	23		T25	10		T28	59
bins_for_gpio_bits[8]	auto[1]	auto[1]	4640225	1			T24	292		T25	113		T26	27772
bins_for_gpio_bits[9]	auto[0]	auto[0]	6828756	1			T24	93		T25	431		T26	29399
bins_for_gpio_bits[9]	auto[0]	auto[1]	204639	1			T24	24		T25	12		T28	55
bins_for_gpio_bits[9]	auto[1]	auto[0]	204920	1			T24	24		T25	12		T28	55
bins_for_gpio_bits[9]	auto[1]	auto[1]	4643647	1			T24	313		T25	123		T26	28296
bins_for_gpio_bits[10]	auto[0]	auto[0]	6820756	1			T24	97		T25	454		T26	27506
bins_for_gpio_bits[10]	auto[0]	auto[1]	204387	1			T24	25		T25	13		T28	58
bins_for_gpio_bits[10]	auto[1]	auto[0]	204616	1			T24	25		T25	13		T28	58
bins_for_gpio_bits[10]	auto[1]	auto[1]	4652203	1			T24	307		T25	98		T26	30189
bins_for_gpio_bits[11]	auto[0]	auto[0]	6844135	1			T24	126		T25	481		T26	30684
bins_for_gpio_bits[11]	auto[0]	auto[1]	203395	1			T24	27		T25	11		T28	52
bins_for_gpio_bits[11]	auto[1]	auto[0]	203679	1			T24	27		T25	11		T28	51
bins_for_gpio_bits[11]	auto[1]	auto[1]	4630753	1			T24	274		T25	75		T26	27011
bins_for_gpio_bits[12]	auto[0]	auto[0]	6822701	1			T24	114		T25	444		T26	29463
bins_for_gpio_bits[12]	auto[0]	auto[1]	204657	1			T24	22		T25	14		T28	54
bins_for_gpio_bits[12]	auto[1]	auto[0]	204925	1			T24	22		T25	14		T28	53
bins_for_gpio_bits[12]	auto[1]	auto[1]	4649679	1			T24	296		T25	106		T26	28232
bins_for_gpio_bits[13]	auto[0]	auto[0]	6828471	1			T24	119		T25	462		T26	28950
bins_for_gpio_bits[13]	auto[0]	auto[1]	204042	1			T24	29		T25	10		T28	59
bins_for_gpio_bits[13]	auto[1]	auto[0]	204283	1			T24	29		T25	10		T28	59
bins_for_gpio_bits[13]	auto[1]	auto[1]	4645166	1			T24	277		T25	96		T26	28745
bins_for_gpio_bits[14]	auto[0]	auto[0]	6839624	1			T24	103		T25	466		T26	29579
bins_for_gpio_bits[14]	auto[0]	auto[1]	203976	1			T24	21		T25	8		T28	48
bins_for_gpio_bits[14]	auto[1]	auto[0]	204250	1			T24	20		T25	8		T28	48
bins_for_gpio_bits[14]	auto[1]	auto[1]	4634112	1			T24	310		T25	96		T26	28116
bins_for_gpio_bits[15]	auto[0]	auto[0]	6835421	1			T24	99		T25	392		T26	29644
bins_for_gpio_bits[15]	auto[0]	auto[1]	204135	1			T24	21		T25	18		T28	60
bins_for_gpio_bits[15]	auto[1]	auto[0]	204417	1			T24	21		T25	18		T28	60
bins_for_gpio_bits[15]	auto[1]	auto[1]	4637989	1			T24	313		T25	150		T26	28051
bins_for_gpio_bits[16]	auto[0]	auto[0]	6822524	1			T24	106		T25	422		T26	27883
bins_for_gpio_bits[16]	auto[0]	auto[1]	204106	1			T24	19		T25	18		T28	51
bins_for_gpio_bits[16]	auto[1]	auto[0]	204360	1			T24	19		T25	18		T28	50
bins_for_gpio_bits[16]	auto[1]	auto[1]	4650972	1			T24	310		T25	120		T26	29812
bins_for_gpio_bits[17]	auto[0]	auto[0]	6825040	1			T24	104		T25	429		T26	27572
bins_for_gpio_bits[17]	auto[0]	auto[1]	204379	1			T24	21		T25	15		T28	50
bins_for_gpio_bits[17]	auto[1]	auto[0]	204649	1			T24	21		T25	15		T28	49
bins_for_gpio_bits[17]	auto[1]	auto[1]	4647894	1			T24	308		T25	119		T26	30123
bins_for_gpio_bits[18]	auto[0]	auto[0]	6829498	1			T24	105		T25	387		T26	28651
bins_for_gpio_bits[18]	auto[0]	auto[1]	204212	1			T24	29		T25	18		T28	67
bins_for_gpio_bits[18]	auto[1]	auto[0]	204471	1			T24	29		T25	18		T28	67
bins_for_gpio_bits[18]	auto[1]	auto[1]	4643781	1			T24	291		T25	155		T26	29044
bins_for_gpio_bits[19]	auto[0]	auto[0]	6841955	1			T24	110		T25	452		T26	28156
bins_for_gpio_bits[19]	auto[0]	auto[1]	204365	1			T24	25		T25	16		T28	48
bins_for_gpio_bits[19]	auto[1]	auto[0]	204599	1			T24	25		T25	16		T28	48
bins_for_gpio_bits[19]	auto[1]	auto[1]	4631043	1			T24	294		T25	94		T26	29539
bins_for_gpio_bits[20]	auto[0]	auto[0]	6833028	1			T24	75		T25	423		T26	28734
bins_for_gpio_bits[20]	auto[0]	auto[1]	203526	1			T24	22		T25	12		T28	44
bins_for_gpio_bits[20]	auto[1]	auto[0]	203793	1			T24	21		T25	12		T28	44
bins_for_gpio_bits[20]	auto[1]	auto[1]	4641615	1			T24	336		T25	131		T26	28961
bins_for_gpio_bits[21]	auto[0]	auto[0]	6818425	1			T24	82		T25	444		T26	25968
bins_for_gpio_bits[21]	auto[0]	auto[1]	204179	1			T24	24		T25	14		T28	53
bins_for_gpio_bits[21]	auto[1]	auto[0]	204461	1			T24	23		T25	14		T28	52
bins_for_gpio_bits[21]	auto[1]	auto[1]	4654897	1			T24	325		T25	106		T26	31727
bins_for_gpio_bits[22]	auto[0]	auto[0]	6823957	1			T24	79		T25	432		T26	27631
bins_for_gpio_bits[22]	auto[0]	auto[1]	204320	1			T24	21		T25	17		T28	54
bins_for_gpio_bits[22]	auto[1]	auto[0]	204598	1			T24	21		T25	17		T28	53
bins_for_gpio_bits[22]	auto[1]	auto[1]	4649087	1			T24	333		T25	112		T26	30064
bins_for_gpio_bits[23]	auto[0]	auto[0]	6832466	1			T24	103		T25	473		T26	29801
bins_for_gpio_bits[23]	auto[0]	auto[1]	204178	1			T24	32		T25	14		T28	52
bins_for_gpio_bits[23]	auto[1]	auto[0]	204461	1			T24	32		T25	14		T28	52
bins_for_gpio_bits[23]	auto[1]	auto[1]	4640857	1			T24	287		T25	77		T26	27894
bins_for_gpio_bits[24]	auto[0]	auto[0]	6830357	1			T24	111		T25	425		T26	29660
bins_for_gpio_bits[24]	auto[0]	auto[1]	204289	1			T24	24		T25	11		T28	61
bins_for_gpio_bits[24]	auto[1]	auto[0]	204582	1			T24	24		T25	11		T28	61
bins_for_gpio_bits[24]	auto[1]	auto[1]	4642734	1			T24	295		T25	131		T26	28035
bins_for_gpio_bits[25]	auto[0]	auto[0]	6832232	1			T24	120		T25	489		T26	28512
bins_for_gpio_bits[25]	auto[0]	auto[1]	203925	1			T24	30		T25	12		T28	50
bins_for_gpio_bits[25]	auto[1]	auto[0]	204233	1			T24	29		T25	12		T28	49
bins_for_gpio_bits[25]	auto[1]	auto[1]	4641572	1			T24	275		T25	65		T26	29183
bins_for_gpio_bits[26]	auto[0]	auto[0]	6830304	1			T24	97		T25	470		T26	29191
bins_for_gpio_bits[26]	auto[0]	auto[1]	203490	1			T24	22		T25	10		T28	49
bins_for_gpio_bits[26]	auto[1]	auto[0]	203783	1			T24	22		T25	10		T28	49
bins_for_gpio_bits[26]	auto[1]	auto[1]	4644385	1			T24	313		T25	88		T26	28504
bins_for_gpio_bits[27]	auto[0]	auto[0]	6822034	1			T24	143		T25	411		T26	29077
bins_for_gpio_bits[27]	auto[0]	auto[1]	204214	1			T24	23		T25	17		T28	49
bins_for_gpio_bits[27]	auto[1]	auto[0]	204509	1			T24	23		T25	17		T28	49
bins_for_gpio_bits[27]	auto[1]	auto[1]	4651205	1			T24	265		T25	133		T26	28618
bins_for_gpio_bits[28]	auto[0]	auto[0]	6826580	1			T24	116		T25	415		T26	30881
bins_for_gpio_bits[28]	auto[0]	auto[1]	204820	1			T24	27		T25	15		T28	56
bins_for_gpio_bits[28]	auto[1]	auto[0]	205075	1			T24	27		T25	15		T28	55
bins_for_gpio_bits[28]	auto[1]	auto[1]	4645487	1			T24	284		T25	133		T26	26814
bins_for_gpio_bits[29]	auto[0]	auto[0]	6834147	1			T24	102		T25	416		T26	29036
bins_for_gpio_bits[29]	auto[0]	auto[1]	203678	1			T24	27		T25	13		T28	59
bins_for_gpio_bits[29]	auto[1]	auto[0]	203960	1			T24	27		T25	13		T28	59
bins_for_gpio_bits[29]	auto[1]	auto[1]	4640177	1			T24	298		T25	136		T26	28659
bins_for_gpio_bits[30]	auto[0]	auto[0]	6826911	1			T24	116		T25	481		T26	27566
bins_for_gpio_bits[30]	auto[0]	auto[1]	204493	1			T24	31		T25	12		T28	52
bins_for_gpio_bits[30]	auto[1]	auto[0]	204770	1			T24	30		T25	12		T28	52
bins_for_gpio_bits[30]	auto[1]	auto[1]	4645788	1			T24	277		T25	73		T26	30129
bins_for_gpio_bits[31]	auto[0]	auto[0]	6830637	1			T24	109		T25	444		T26	29917
bins_for_gpio_bits[31]	auto[0]	auto[1]	203921	1			T24	25		T25	16		T28	50
bins_for_gpio_bits[31]	auto[1]	auto[0]	204155	1			T24	25		T25	16		T28	50
bins_for_gpio_bits[31]	auto[1]	auto[1]	4643249	1			T24	295		T25	102		T26	27778