Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7073077 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5037030 |
1 |
|
|
T27 |
111 |
|
T28 |
905 |
|
T32 |
58639 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11469304 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
640803 |
1 |
|
|
T27 |
8 |
|
T28 |
43 |
|
T32 |
7908 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7079897 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5030210 |
1 |
|
|
T27 |
193 |
|
T28 |
982 |
|
T32 |
59888 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2188899 |
1 |
|
|
T27 |
115 |
|
T28 |
491 |
|
T32 |
25869 |
| auto[1] |
auto[0] |
auto[1] |
319213 |
1 |
|
|
T27 |
4 |
|
T28 |
19 |
|
T32 |
3861 |
| auto[1] |
auto[1] |
auto[0] |
2200508 |
1 |
|
|
T27 |
70 |
|
T28 |
448 |
|
T32 |
26111 |
| auto[1] |
auto[1] |
auto[1] |
321590 |
1 |
|
|
T27 |
4 |
|
T28 |
24 |
|
T32 |
4047 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7077591 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5032516 |
1 |
|
|
T27 |
184 |
|
T28 |
1015 |
|
T32 |
60465 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11470027 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
640080 |
1 |
|
|
T27 |
11 |
|
T28 |
34 |
|
T32 |
7725 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7080543 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5029564 |
1 |
|
|
T27 |
210 |
|
T28 |
937 |
|
T32 |
59399 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2190842 |
1 |
|
|
T27 |
105 |
|
T28 |
403 |
|
T32 |
25425 |
| auto[1] |
auto[0] |
auto[1] |
318533 |
1 |
|
|
T27 |
7 |
|
T28 |
9 |
|
T32 |
3738 |
| auto[1] |
auto[1] |
auto[0] |
2198642 |
1 |
|
|
T27 |
94 |
|
T28 |
500 |
|
T32 |
26249 |
| auto[1] |
auto[1] |
auto[1] |
321547 |
1 |
|
|
T27 |
4 |
|
T28 |
25 |
|
T32 |
3987 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7058417 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5051690 |
1 |
|
|
T27 |
217 |
|
T28 |
1052 |
|
T32 |
58898 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11471855 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
638252 |
1 |
|
|
T27 |
12 |
|
T28 |
45 |
|
T32 |
7698 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7100097 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5010010 |
1 |
|
|
T27 |
191 |
|
T28 |
956 |
|
T32 |
57988 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2182525 |
1 |
|
|
T27 |
85 |
|
T28 |
397 |
|
T32 |
25473 |
| auto[1] |
auto[0] |
auto[1] |
318113 |
1 |
|
|
T27 |
7 |
|
T28 |
21 |
|
T32 |
3801 |
| auto[1] |
auto[1] |
auto[0] |
2189233 |
1 |
|
|
T27 |
94 |
|
T28 |
514 |
|
T32 |
24817 |
| auto[1] |
auto[1] |
auto[1] |
320139 |
1 |
|
|
T27 |
5 |
|
T28 |
24 |
|
T32 |
3897 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7088677 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5021430 |
1 |
|
|
T27 |
193 |
|
T28 |
854 |
|
T32 |
57692 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11470395 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
639712 |
1 |
|
|
T27 |
13 |
|
T28 |
33 |
|
T32 |
7622 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7085590 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5024517 |
1 |
|
|
T27 |
195 |
|
T28 |
923 |
|
T32 |
58695 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2195131 |
1 |
|
|
T27 |
83 |
|
T28 |
540 |
|
T32 |
25874 |
| auto[1] |
auto[0] |
auto[1] |
319586 |
1 |
|
|
T27 |
3 |
|
T28 |
21 |
|
T32 |
3914 |
| auto[1] |
auto[1] |
auto[0] |
2189674 |
1 |
|
|
T27 |
99 |
|
T28 |
350 |
|
T32 |
25199 |
| auto[1] |
auto[1] |
auto[1] |
320126 |
1 |
|
|
T27 |
10 |
|
T28 |
12 |
|
T32 |
3708 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7068461 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5041646 |
1 |
|
|
T27 |
166 |
|
T28 |
1019 |
|
T32 |
60438 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11470675 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
639432 |
1 |
|
|
T27 |
7 |
|
T28 |
37 |
|
T32 |
7845 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7095755 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5014352 |
1 |
|
|
T27 |
221 |
|
T28 |
1005 |
|
T32 |
59855 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2181281 |
1 |
|
|
T27 |
120 |
|
T28 |
486 |
|
T32 |
25275 |
| auto[1] |
auto[0] |
auto[1] |
318337 |
1 |
|
|
T27 |
6 |
|
T28 |
18 |
|
T32 |
3802 |
| auto[1] |
auto[1] |
auto[0] |
2193639 |
1 |
|
|
T27 |
94 |
|
T28 |
482 |
|
T32 |
26735 |
| auto[1] |
auto[1] |
auto[1] |
321095 |
1 |
|
|
T27 |
1 |
|
T28 |
19 |
|
T32 |
4043 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7072164 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5037943 |
1 |
|
|
T27 |
204 |
|
T28 |
888 |
|
T32 |
58491 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11467943 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
642164 |
1 |
|
|
T27 |
6 |
|
T28 |
40 |
|
T32 |
7935 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7078469 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5031638 |
1 |
|
|
T27 |
145 |
|
T28 |
1038 |
|
T32 |
59912 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2191567 |
1 |
|
|
T27 |
44 |
|
T28 |
569 |
|
T32 |
25940 |
| auto[1] |
auto[0] |
auto[1] |
320792 |
1 |
|
|
T27 |
2 |
|
T28 |
26 |
|
T32 |
3980 |
| auto[1] |
auto[1] |
auto[0] |
2197907 |
1 |
|
|
T27 |
95 |
|
T28 |
429 |
|
T32 |
26037 |
| auto[1] |
auto[1] |
auto[1] |
321372 |
1 |
|
|
T27 |
4 |
|
T28 |
14 |
|
T32 |
3955 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7095161 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5014946 |
1 |
|
|
T27 |
199 |
|
T28 |
1102 |
|
T32 |
59322 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11460605 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
649502 |
1 |
|
|
T27 |
8 |
|
T28 |
30 |
|
T32 |
7862 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7027459 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5082648 |
1 |
|
|
T27 |
150 |
|
T28 |
961 |
|
T32 |
59745 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2230241 |
1 |
|
|
T27 |
70 |
|
T28 |
446 |
|
T32 |
25920 |
| auto[1] |
auto[0] |
auto[1] |
326794 |
1 |
|
|
T27 |
2 |
|
T28 |
13 |
|
T32 |
3907 |
| auto[1] |
auto[1] |
auto[0] |
2202905 |
1 |
|
|
T27 |
72 |
|
T28 |
485 |
|
T32 |
25963 |
| auto[1] |
auto[1] |
auto[1] |
322708 |
1 |
|
|
T27 |
6 |
|
T28 |
17 |
|
T32 |
3955 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7092900 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5017207 |
1 |
|
|
T27 |
211 |
|
T28 |
875 |
|
T32 |
56931 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11472949 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
637158 |
1 |
|
|
T27 |
10 |
|
T28 |
30 |
|
T32 |
7695 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7111792 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
4998315 |
1 |
|
|
T27 |
193 |
|
T28 |
816 |
|
T32 |
58239 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2188700 |
1 |
|
|
T27 |
83 |
|
T28 |
417 |
|
T32 |
26237 |
| auto[1] |
auto[0] |
auto[1] |
319710 |
1 |
|
|
T27 |
3 |
|
T28 |
18 |
|
T32 |
4068 |
| auto[1] |
auto[1] |
auto[0] |
2172457 |
1 |
|
|
T27 |
100 |
|
T28 |
369 |
|
T32 |
24307 |
| auto[1] |
auto[1] |
auto[1] |
317448 |
1 |
|
|
T27 |
7 |
|
T28 |
12 |
|
T32 |
3627 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7089044 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5021063 |
1 |
|
|
T27 |
190 |
|
T28 |
1015 |
|
T32 |
57820 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11471166 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
638941 |
1 |
|
|
T27 |
13 |
|
T28 |
49 |
|
T32 |
7557 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7093020 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5017087 |
1 |
|
|
T27 |
174 |
|
T28 |
1157 |
|
T32 |
58530 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2195443 |
1 |
|
|
T27 |
79 |
|
T28 |
541 |
|
T32 |
26188 |
| auto[1] |
auto[0] |
auto[1] |
320720 |
1 |
|
|
T27 |
5 |
|
T28 |
24 |
|
T32 |
3955 |
| auto[1] |
auto[1] |
auto[0] |
2182703 |
1 |
|
|
T27 |
82 |
|
T28 |
567 |
|
T32 |
24785 |
| auto[1] |
auto[1] |
auto[1] |
318221 |
1 |
|
|
T27 |
8 |
|
T28 |
25 |
|
T32 |
3602 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7104217 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5005890 |
1 |
|
|
T27 |
186 |
|
T28 |
996 |
|
T32 |
57190 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11465501 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
644606 |
1 |
|
|
T27 |
11 |
|
T28 |
36 |
|
T32 |
7491 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7061294 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5048813 |
1 |
|
|
T27 |
154 |
|
T28 |
853 |
|
T32 |
57174 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2213518 |
1 |
|
|
T27 |
77 |
|
T28 |
426 |
|
T32 |
25053 |
| auto[1] |
auto[0] |
auto[1] |
324400 |
1 |
|
|
T27 |
7 |
|
T28 |
21 |
|
T32 |
3790 |
| auto[1] |
auto[1] |
auto[0] |
2190689 |
1 |
|
|
T27 |
66 |
|
T28 |
391 |
|
T32 |
24630 |
| auto[1] |
auto[1] |
auto[1] |
320206 |
1 |
|
|
T27 |
4 |
|
T28 |
15 |
|
T32 |
3701 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7076935 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5033172 |
1 |
|
|
T27 |
161 |
|
T28 |
949 |
|
T32 |
56819 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11466898 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
643209 |
1 |
|
|
T27 |
10 |
|
T28 |
52 |
|
T32 |
7813 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7067444 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5042663 |
1 |
|
|
T27 |
208 |
|
T28 |
1139 |
|
T32 |
59209 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2199318 |
1 |
|
|
T27 |
107 |
|
T28 |
569 |
|
T32 |
26500 |
| auto[1] |
auto[0] |
auto[1] |
320801 |
1 |
|
|
T27 |
6 |
|
T28 |
28 |
|
T32 |
4103 |
| auto[1] |
auto[1] |
auto[0] |
2200136 |
1 |
|
|
T27 |
91 |
|
T28 |
518 |
|
T32 |
24896 |
| auto[1] |
auto[1] |
auto[1] |
322408 |
1 |
|
|
T27 |
4 |
|
T28 |
24 |
|
T32 |
3710 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7102284 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5007823 |
1 |
|
|
T27 |
175 |
|
T28 |
1046 |
|
T32 |
59231 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11470241 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
639866 |
1 |
|
|
T27 |
9 |
|
T28 |
28 |
|
T32 |
7406 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7091252 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5018855 |
1 |
|
|
T27 |
198 |
|
T28 |
852 |
|
T32 |
56935 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2205887 |
1 |
|
|
T27 |
111 |
|
T28 |
447 |
|
T32 |
25451 |
| auto[1] |
auto[0] |
auto[1] |
322702 |
1 |
|
|
T27 |
7 |
|
T28 |
16 |
|
T32 |
3852 |
| auto[1] |
auto[1] |
auto[0] |
2173102 |
1 |
|
|
T27 |
78 |
|
T28 |
377 |
|
T32 |
24078 |
| auto[1] |
auto[1] |
auto[1] |
317164 |
1 |
|
|
T27 |
2 |
|
T28 |
12 |
|
T32 |
3554 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7051409 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5058698 |
1 |
|
|
T27 |
224 |
|
T28 |
990 |
|
T32 |
59745 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11467713 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
642394 |
1 |
|
|
T27 |
7 |
|
T28 |
49 |
|
T32 |
7552 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7070010 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5040097 |
1 |
|
|
T27 |
168 |
|
T28 |
1146 |
|
T32 |
57765 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2205956 |
1 |
|
|
T27 |
52 |
|
T28 |
560 |
|
T32 |
24681 |
| auto[1] |
auto[0] |
auto[1] |
322631 |
1 |
|
|
T27 |
1 |
|
T28 |
29 |
|
T32 |
3678 |
| auto[1] |
auto[1] |
auto[0] |
2191747 |
1 |
|
|
T27 |
109 |
|
T28 |
537 |
|
T32 |
25532 |
| auto[1] |
auto[1] |
auto[1] |
319763 |
1 |
|
|
T27 |
6 |
|
T28 |
20 |
|
T32 |
3874 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7075009 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5035098 |
1 |
|
|
T27 |
139 |
|
T28 |
936 |
|
T32 |
58015 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11471122 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
638985 |
1 |
|
|
T27 |
13 |
|
T28 |
32 |
|
T32 |
7771 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7086485 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5023622 |
1 |
|
|
T27 |
234 |
|
T28 |
1078 |
|
T32 |
58756 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2189733 |
1 |
|
|
T27 |
154 |
|
T28 |
558 |
|
T32 |
25752 |
| auto[1] |
auto[0] |
auto[1] |
319446 |
1 |
|
|
T27 |
10 |
|
T28 |
22 |
|
T32 |
3938 |
| auto[1] |
auto[1] |
auto[0] |
2194904 |
1 |
|
|
T27 |
67 |
|
T28 |
488 |
|
T32 |
25233 |
| auto[1] |
auto[1] |
auto[1] |
319539 |
1 |
|
|
T27 |
3 |
|
T28 |
10 |
|
T32 |
3833 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7078643 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5031464 |
1 |
|
|
T27 |
134 |
|
T28 |
994 |
|
T32 |
57811 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11466501 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
643606 |
1 |
|
|
T27 |
5 |
|
T28 |
38 |
|
T32 |
7710 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7066245 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5043862 |
1 |
|
|
T27 |
118 |
|
T28 |
908 |
|
T32 |
56994 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2209722 |
1 |
|
|
T27 |
67 |
|
T28 |
429 |
|
T32 |
24788 |
| auto[1] |
auto[0] |
auto[1] |
323509 |
1 |
|
|
T27 |
3 |
|
T28 |
18 |
|
T32 |
3928 |
| auto[1] |
auto[1] |
auto[0] |
2190534 |
1 |
|
|
T27 |
46 |
|
T28 |
441 |
|
T32 |
24496 |
| auto[1] |
auto[1] |
auto[1] |
320097 |
1 |
|
|
T27 |
2 |
|
T28 |
20 |
|
T32 |
3782 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7048647 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5061460 |
1 |
|
|
T27 |
219 |
|
T28 |
959 |
|
T32 |
54918 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11464390 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
645717 |
1 |
|
|
T27 |
8 |
|
T28 |
38 |
|
T32 |
7763 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7060647 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5049460 |
1 |
|
|
T27 |
145 |
|
T28 |
830 |
|
T32 |
58902 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2202666 |
1 |
|
|
T27 |
50 |
|
T28 |
400 |
|
T32 |
27710 |
| auto[1] |
auto[0] |
auto[1] |
322690 |
1 |
|
|
T27 |
2 |
|
T28 |
17 |
|
T32 |
4310 |
| auto[1] |
auto[1] |
auto[0] |
2201077 |
1 |
|
|
T27 |
87 |
|
T28 |
392 |
|
T32 |
23429 |
| auto[1] |
auto[1] |
auto[1] |
323027 |
1 |
|
|
T27 |
6 |
|
T28 |
21 |
|
T32 |
3453 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7068911 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5041196 |
1 |
|
|
T27 |
186 |
|
T28 |
1056 |
|
T32 |
59269 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11469155 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
640952 |
1 |
|
|
T27 |
7 |
|
T28 |
38 |
|
T32 |
7800 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7085483 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5024624 |
1 |
|
|
T27 |
185 |
|
T28 |
954 |
|
T32 |
59611 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2183083 |
1 |
|
|
T27 |
102 |
|
T28 |
464 |
|
T32 |
25474 |
| auto[1] |
auto[0] |
auto[1] |
318365 |
1 |
|
|
T27 |
4 |
|
T28 |
14 |
|
T32 |
3735 |
| auto[1] |
auto[1] |
auto[0] |
2200589 |
1 |
|
|
T27 |
76 |
|
T28 |
452 |
|
T32 |
26337 |
| auto[1] |
auto[1] |
auto[1] |
322587 |
1 |
|
|
T27 |
3 |
|
T28 |
24 |
|
T32 |
4065 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7082836 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5027271 |
1 |
|
|
T27 |
203 |
|
T28 |
1138 |
|
T32 |
59491 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11468362 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
641745 |
1 |
|
|
T27 |
9 |
|
T28 |
45 |
|
T32 |
7563 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7078796 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5031311 |
1 |
|
|
T27 |
182 |
|
T28 |
1000 |
|
T32 |
57387 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2194964 |
1 |
|
|
T27 |
56 |
|
T28 |
420 |
|
T32 |
24673 |
| auto[1] |
auto[0] |
auto[1] |
320622 |
1 |
|
|
T27 |
3 |
|
T28 |
21 |
|
T32 |
3776 |
| auto[1] |
auto[1] |
auto[0] |
2194602 |
1 |
|
|
T27 |
117 |
|
T28 |
535 |
|
T32 |
25151 |
| auto[1] |
auto[1] |
auto[1] |
321123 |
1 |
|
|
T27 |
6 |
|
T28 |
24 |
|
T32 |
3787 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7071538 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5038569 |
1 |
|
|
T27 |
160 |
|
T28 |
1067 |
|
T32 |
59200 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11469386 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
640721 |
1 |
|
|
T27 |
7 |
|
T28 |
28 |
|
T32 |
7322 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7088618 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5021489 |
1 |
|
|
T27 |
165 |
|
T28 |
830 |
|
T32 |
56947 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2184392 |
1 |
|
|
T27 |
78 |
|
T28 |
430 |
|
T32 |
25110 |
| auto[1] |
auto[0] |
auto[1] |
319922 |
1 |
|
|
T27 |
4 |
|
T28 |
14 |
|
T32 |
3712 |
| auto[1] |
auto[1] |
auto[0] |
2196376 |
1 |
|
|
T27 |
80 |
|
T28 |
372 |
|
T32 |
24515 |
| auto[1] |
auto[1] |
auto[1] |
320799 |
1 |
|
|
T27 |
3 |
|
T28 |
14 |
|
T32 |
3610 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7096310 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5013797 |
1 |
|
|
T27 |
149 |
|
T28 |
761 |
|
T32 |
58128 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11471827 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
638280 |
1 |
|
|
T27 |
13 |
|
T28 |
43 |
|
T32 |
7569 |